Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	632632	1			T1	5210		T2	3		T3	2
all_pins[1]	632632	1			T1	5210		T2	3		T3	2
all_pins[2]	632632	1			T1	5210		T2	3		T3	2
all_pins[3]	632632	1			T1	5210		T2	3		T3	2
all_pins[4]	632632	1			T1	5210		T2	3		T3	2
all_pins[5]	632632	1			T1	5210		T2	3		T3	2
all_pins[6]	632632	1			T1	5210		T2	3		T3	2
all_pins[7]	632632	1			T1	5210		T2	3		T3	2
all_pins[8]	632632	1			T1	5210		T2	3		T3	2
all_pins[9]	632632	1			T1	5210		T2	3		T3	2
all_pins[10]	632632	1			T1	5210		T2	3		T3	2
all_pins[11]	632632	1			T1	5210		T2	3		T3	2
all_pins[12]	632632	1			T1	5210		T2	3		T3	2
all_pins[13]	632632	1			T1	5210		T2	3		T3	2
all_pins[14]	632632	1			T1	5210		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7824573	1			T1	62613		T2	39		T3	26
values[0x1]	1664907	1			T1	15537		T2	6		T3	4
transitions[0x0=>0x1]	1664210	1			T1	15537		T2	6		T3	4
transitions[0x1=>0x0]	1662890	1			T1	15536		T2	5		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	109825	1			T1	113		T2	1		T4	2373
all_pins[0]	values[0x1]	522807	1			T1	5097		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	522431	1			T1	5097		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	61	1			T28	1		T192	4		T288	1
all_pins[1]	values[0x0]	632195	1			T1	5210		T2	3		T3	2
all_pins[1]	values[0x1]	437	1			T32	7		T46	5		T27	11
all_pins[1]	transitions[0x0=>0x1]	418	1			T32	7		T46	5		T27	11
all_pins[1]	transitions[0x1=>0x0]	125	1			T289	1		T290	1		T291	1
all_pins[2]	values[0x0]	632488	1			T1	5210		T2	3		T3	2
all_pins[2]	values[0x1]	144	1			T289	1		T290	1		T291	1
all_pins[2]	transitions[0x0=>0x1]	123	1			T289	1		T290	1		T291	1
all_pins[2]	transitions[0x1=>0x0]	70	1			T192	3		T193	1		T292	4
all_pins[3]	values[0x0]	632541	1			T1	5210		T2	3		T3	2
all_pins[3]	values[0x1]	91	1			T192	4		T193	2		T292	4
all_pins[3]	transitions[0x0=>0x1]	77	1			T192	4		T193	1		T292	2
all_pins[3]	transitions[0x1=>0x0]	79	1			T25	2		T280	1		T192	2
all_pins[4]	values[0x0]	632539	1			T1	5210		T2	3		T3	2
all_pins[4]	values[0x1]	93	1			T25	2		T280	1		T192	2
all_pins[4]	transitions[0x0=>0x1]	71	1			T25	2		T280	1		T192	1
all_pins[4]	transitions[0x1=>0x0]	82	1			T192	4		T193	1		T37	2
all_pins[5]	values[0x0]	632528	1			T1	5210		T2	3		T3	2
all_pins[5]	values[0x1]	104	1			T192	5		T193	3		T37	2
all_pins[5]	transitions[0x0=>0x1]	82	1			T192	3		T193	3		T37	2
all_pins[5]	transitions[0x1=>0x0]	70	1			T191	1		T192	1		T37	3
all_pins[6]	values[0x0]	632540	1			T1	5210		T2	3		T3	2
all_pins[6]	values[0x1]	92	1			T191	1		T192	3		T37	3
all_pins[6]	transitions[0x0=>0x1]	68	1			T191	1		T192	3		T37	3
all_pins[6]	transitions[0x1=>0x0]	29574	1			T1	142		T2	1		T4	326
all_pins[7]	values[0x0]	603034	1			T1	5068		T2	2		T3	2
all_pins[7]	values[0x1]	29598	1			T1	142		T2	1		T4	326
all_pins[7]	transitions[0x0=>0x1]	29577	1			T1	142		T2	1		T4	326
all_pins[7]	transitions[0x1=>0x0]	61	1			T192	2		T193	1		T293	1
all_pins[8]	values[0x0]	632550	1			T1	5210		T2	3		T3	2
all_pins[8]	values[0x1]	82	1			T192	2		T193	2		T293	1
all_pins[8]	transitions[0x0=>0x1]	65	1			T192	2		T193	1		T293	1
all_pins[8]	transitions[0x1=>0x0]	485205	1			T1	5097		T2	1		T4	13969
all_pins[9]	values[0x0]	147410	1			T1	113		T2	2		T3	2
all_pins[9]	values[0x1]	485222	1			T1	5097		T2	1		T4	13969
all_pins[9]	transitions[0x0=>0x1]	485198	1			T1	5097		T2	1		T4	13969
all_pins[9]	transitions[0x1=>0x0]	60	1			T191	2		T192	1		T193	1
all_pins[10]	values[0x0]	632548	1			T1	5210		T2	3		T3	2
all_pins[10]	values[0x1]	84	1			T191	2		T192	1		T193	1
all_pins[10]	transitions[0x0=>0x1]	56	1			T191	2		T192	1		T193	1
all_pins[10]	transitions[0x1=>0x0]	625785	1			T1	5201		T2	2		T3	2
all_pins[11]	values[0x0]	6819	1			T1	9		T2	1		T4	9
all_pins[11]	values[0x1]	625813	1			T1	5201		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	625777	1			T1	5201		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	114	1			T59	1		T74	1		T75	1
all_pins[12]	values[0x0]	632482	1			T1	5210		T2	3		T3	2
all_pins[12]	values[0x1]	150	1			T59	1		T289	1		T74	1
all_pins[12]	transitions[0x0=>0x1]	135	1			T59	1		T289	1		T74	1
all_pins[12]	transitions[0x1=>0x0]	77	1			T191	1		T192	1		T37	3
all_pins[13]	values[0x0]	632540	1			T1	5210		T2	3		T3	2
all_pins[13]	values[0x1]	92	1			T191	1		T192	1		T37	3
all_pins[13]	transitions[0x0=>0x1]	68	1			T192	1		T37	3		T292	1
all_pins[13]	transitions[0x1=>0x0]	74	1			T192	2		T193	2		T37	1
all_pins[14]	values[0x0]	632534	1			T1	5210		T2	3		T3	2
all_pins[14]	values[0x1]	98	1			T191	1		T192	2		T193	2
all_pins[14]	transitions[0x0=>0x1]	64	1			T191	1		T192	2		T193	1
all_pins[14]	transitions[0x1=>0x0]	521453	1			T1	5096		T2	1		T3	1