Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	409	1			T191	7		T192	14		T193	7
all_values[1]	409	1			T191	7		T192	14		T193	7
all_values[2]	409	1			T191	7		T192	14		T193	7
all_values[3]	409	1			T191	7		T192	14		T193	7
all_values[4]	409	1			T191	7		T192	14		T193	7
all_values[5]	409	1			T191	7		T192	14		T193	7
all_values[6]	409	1			T191	7		T192	14		T193	7
all_values[7]	409	1			T191	7		T192	14		T193	7
all_values[8]	409	1			T191	7		T192	14		T193	7
all_values[9]	409	1			T191	7		T192	14		T193	7
all_values[10]	409	1			T191	7		T192	14		T193	7
all_values[11]	409	1			T191	7		T192	14		T193	7
all_values[12]	409	1			T191	7		T192	14		T193	7
all_values[13]	409	1			T191	7		T192	14		T193	7
all_values[14]	409	1			T191	7		T192	14		T193	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3255

1

T191

65

T192

114

T193

61

auto[1]

2880

1

T191

40

T192

96

T193

44

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

901

1

T191

19

T192

19

T193

8

auto[1]

5234

1

T191

86

T192

191

T193

97

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3577

1

T191

63

T192

119

T193

54

auto[1]

2558

1

T191

42

T192

91

T193

51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	27	1			T192	1		T193	1		T38	1
all_values[0]	auto[0]	auto[0]	auto[1]	90	1			T191	1		T192	4		T193	2
all_values[0]	auto[0]	auto[1]	auto[0]	40	1			T191	1		T127	1		T294	1
all_values[0]	auto[0]	auto[1]	auto[1]	96	1			T191	3		T192	3		T193	1
all_values[0]	auto[1]	auto[0]	auto[1]	87	1			T192	4		T193	1		T37	3
all_values[0]	auto[1]	auto[1]	auto[1]	69	1			T191	2		T192	2		T193	2
all_values[1]	auto[0]	auto[0]	auto[0]	47	1			T191	1		T193	1		T37	4
all_values[1]	auto[0]	auto[0]	auto[1]	84	1			T191	1		T192	1		T193	2
all_values[1]	auto[0]	auto[1]	auto[0]	22	1			T292	1		T293	4		T127	1
all_values[1]	auto[0]	auto[1]	auto[1]	88	1			T191	1		T192	4		T292	1
all_values[1]	auto[1]	auto[0]	auto[1]	94	1			T191	4		T192	7		T193	3
all_values[1]	auto[1]	auto[1]	auto[1]	74	1			T192	2		T193	1		T292	1
all_values[2]	auto[0]	auto[0]	auto[0]	30	1			T38	3		T295	1		T128	1
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T191	2		T192	5		T193	2
all_values[2]	auto[0]	auto[1]	auto[0]	22	1			T191	1		T296	1		T295	2
all_values[2]	auto[0]	auto[1]	auto[1]	93	1			T192	4		T193	1		T292	3
all_values[2]	auto[1]	auto[0]	auto[1]	99	1			T191	2		T192	1		T193	3
all_values[2]	auto[1]	auto[1]	auto[1]	88	1			T191	2		T192	4		T193	1
all_values[3]	auto[0]	auto[0]	auto[0]	30	1			T191	3		T38	1		T297	3
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T191	1		T192	2		T193	3
all_values[3]	auto[0]	auto[1]	auto[0]	18	1			T192	1		T296	1		T127	1
all_values[3]	auto[0]	auto[1]	auto[1]	100	1			T191	1		T192	4		T193	1
all_values[3]	auto[1]	auto[0]	auto[1]	94	1			T191	1		T192	2		T193	1
all_values[3]	auto[1]	auto[1]	auto[1]	82	1			T191	1		T192	5		T193	2
all_values[4]	auto[0]	auto[0]	auto[0]	27	1			T191	2		T192	1		T193	1
all_values[4]	auto[0]	auto[0]	auto[1]	102	1			T191	2		T192	3		T193	2
all_values[4]	auto[0]	auto[1]	auto[0]	27	1			T191	2		T296	1		T293	1
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T192	5		T193	1		T37	2
all_values[4]	auto[1]	auto[0]	auto[1]	91	1			T191	1		T192	4		T37	2
all_values[4]	auto[1]	auto[1]	auto[1]	65	1			T192	1		T193	3		T37	1
all_values[5]	auto[0]	auto[0]	auto[0]	41	1			T38	6		T295	5		T128	1
all_values[5]	auto[0]	auto[0]	auto[1]	90	1			T191	1		T192	4		T193	2
all_values[5]	auto[0]	auto[1]	auto[0]	26	1			T192	1		T296	1		T293	1
all_values[5]	auto[0]	auto[1]	auto[1]	82	1			T191	1		T192	3		T193	2
all_values[5]	auto[1]	auto[0]	auto[1]	100	1			T191	4		T192	4		T193	1
all_values[5]	auto[1]	auto[1]	auto[1]	70	1			T191	1		T192	2		T193	2
all_values[6]	auto[0]	auto[0]	auto[0]	43	1			T191	1		T127	1		T297	1
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T191	1		T192	3		T193	1
all_values[6]	auto[0]	auto[1]	auto[0]	24	1			T191	1		T293	1		T297	1
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T191	1		T192	4		T193	2
all_values[6]	auto[1]	auto[0]	auto[1]	103	1			T192	5		T193	4		T37	3
all_values[6]	auto[1]	auto[1]	auto[1]	85	1			T191	3		T192	2		T37	1
all_values[7]	auto[0]	auto[0]	auto[0]	32	1			T191	1		T192	2		T37	2
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T192	2		T193	2		T37	2
all_values[7]	auto[0]	auto[1]	auto[0]	26	1			T191	1		T192	2		T37	1
all_values[7]	auto[0]	auto[1]	auto[1]	87	1			T191	2		T192	4		T193	2
all_values[7]	auto[1]	auto[0]	auto[1]	97	1			T191	3		T192	2		T193	2
all_values[7]	auto[1]	auto[1]	auto[1]	80	1			T192	2		T193	1		T37	2
all_values[8]	auto[0]	auto[0]	auto[0]	34	1			T296	1		T38	1		T297	1
all_values[8]	auto[0]	auto[0]	auto[1]	108	1			T191	4		T192	5		T193	2
all_values[8]	auto[0]	auto[1]	auto[0]	29	1			T296	1		T293	1		T128	2
all_values[8]	auto[0]	auto[1]	auto[1]	78	1			T191	1		T192	3		T193	1
all_values[8]	auto[1]	auto[0]	auto[1]	92	1			T191	2		T192	1		T193	1
all_values[8]	auto[1]	auto[1]	auto[1]	68	1			T192	5		T193	3		T292	2
all_values[9]	auto[0]	auto[0]	auto[0]	41	1			T191	1		T192	6		T292	1
all_values[9]	auto[0]	auto[0]	auto[1]	83	1			T191	3		T192	2		T37	2
all_values[9]	auto[0]	auto[1]	auto[0]	19	1			T191	1		T192	1		T292	1
all_values[9]	auto[0]	auto[1]	auto[1]	94	1			T192	1		T193	3		T37	2
all_values[9]	auto[1]	auto[0]	auto[1]	108	1			T191	2		T192	3		T193	2
all_values[9]	auto[1]	auto[1]	auto[1]	64	1			T192	1		T193	2		T296	1
all_values[10]	auto[0]	auto[0]	auto[0]	36	1			T193	2		T37	3		T127	1
all_values[10]	auto[0]	auto[0]	auto[1]	95	1			T191	1		T192	3		T37	1
all_values[10]	auto[0]	auto[1]	auto[0]	31	1			T192	1		T193	2		T292	1
all_values[10]	auto[0]	auto[1]	auto[1]	84	1			T191	2		T192	3		T193	1
all_values[10]	auto[1]	auto[0]	auto[1]	91	1			T191	3		T192	4		T193	2
all_values[10]	auto[1]	auto[1]	auto[1]	72	1			T191	1		T192	3		T292	1
all_values[11]	auto[0]	auto[0]	auto[0]	36	1			T127	1		T38	1		T128	1
all_values[11]	auto[0]	auto[0]	auto[1]	101	1			T191	3		T192	2		T193	4
all_values[11]	auto[0]	auto[1]	auto[0]	10	1			T38	1		T298	1		T299	1
all_values[11]	auto[0]	auto[1]	auto[1]	90	1			T191	3		T192	3		T37	2
all_values[11]	auto[1]	auto[0]	auto[1]	82	1			T191	1		T192	4		T193	3
all_values[11]	auto[1]	auto[1]	auto[1]	90	1			T192	5		T37	1		T292	2
all_values[12]	auto[0]	auto[0]	auto[0]	29	1			T191	1		T37	2		T292	1
all_values[12]	auto[0]	auto[0]	auto[1]	72	1			T191	2		T192	2		T193	1
all_values[12]	auto[0]	auto[1]	auto[0]	25	1			T191	1		T37	1		T292	2
all_values[12]	auto[0]	auto[1]	auto[1]	112	1			T192	6		T193	3		T37	2
all_values[12]	auto[1]	auto[0]	auto[1]	93	1			T191	2		T192	4		T193	1
all_values[12]	auto[1]	auto[1]	auto[1]	78	1			T191	1		T192	2		T193	2
all_values[13]	auto[0]	auto[0]	auto[0]	40	1			T191	1		T37	1		T296	1
all_values[13]	auto[0]	auto[0]	auto[1]	92	1			T191	1		T192	9		T193	1
all_values[13]	auto[0]	auto[1]	auto[0]	28	1			T292	1		T296	3		T127	1
all_values[13]	auto[0]	auto[1]	auto[1]	82	1			T191	3		T192	1		T193	1
all_values[13]	auto[1]	auto[0]	auto[1]	80	1			T191	1		T192	4		T193	4
all_values[13]	auto[1]	auto[1]	auto[1]	87	1			T191	1		T193	1		T37	3
all_values[14]	auto[0]	auto[0]	auto[0]	32	1			T192	3		T193	1		T128	1
all_values[14]	auto[0]	auto[0]	auto[1]	78	1			T191	2		T192	1		T193	1
all_values[14]	auto[0]	auto[1]	auto[0]	29	1			T292	1		T38	4		T128	1
all_values[14]	auto[0]	auto[1]	auto[1]	95	1			T191	1		T192	4		T193	2
all_values[14]	auto[1]	auto[0]	auto[1]	97	1			T191	3		T192	4		T193	2
all_values[14]	auto[1]	auto[1]	auto[1]	78	1			T191	1		T192	2		T193	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal