Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	813613	1			T1	2		T2	14687		T3	1
all_values[1]	813613	1			T1	2		T2	14687		T3	1
all_values[2]	813613	1			T1	2		T2	14687		T3	1
all_values[3]	813613	1			T1	2		T2	14687		T3	1
all_values[4]	813613	1			T1	2		T2	14687		T3	1
all_values[5]	813613	1			T1	2		T2	14687		T3	1
all_values[6]	813613	1			T1	2		T2	14687		T3	1
all_values[7]	813613	1			T1	2		T2	14687		T3	1
all_values[8]	813613	1			T1	2		T2	14687		T3	1
all_values[9]	813613	1			T1	2		T2	14687		T3	1
all_values[10]	813613	1			T1	2		T2	14687		T3	1
all_values[11]	813613	1			T1	2		T2	14687		T3	1
all_values[12]	813613	1			T1	2		T2	14687		T3	1
all_values[13]	813613	1			T1	2		T2	14687		T3	1
all_values[14]	813613	1			T1	2		T2	14687		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10036175

1

T1

26

T2

176656

T3

13

auto[1]

2168020

1

T1

4

T2

43649

T3

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11842832

1

T1

30

T2

220305

T3

15

auto[1]

361363

1

T36

190

T176

88724

T177

119

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	107194	1			T2	436		T5	455		T6	5
all_values[0]	auto[0]	auto[1]	3672	1			T36	8		T176	771		T177	4
all_values[0]	auto[1]	auto[0]	682090	1			T1	2		T2	14251		T3	1
all_values[0]	auto[1]	auto[1]	20657	1			T36	4		T176	5165		T177	5
all_values[1]	auto[0]	auto[0]	789042	1			T1	2		T2	14687		T3	1
all_values[1]	auto[0]	auto[1]	24162	1			T36	8		T176	5932		T177	5
all_values[1]	auto[1]	auto[0]	241	1			T17	2		T261	4		T36	1
all_values[1]	auto[1]	auto[1]	168	1			T36	6		T176	5		T177	3
all_values[2]	auto[0]	auto[0]	789126	1			T1	2		T2	14687		T3	1
all_values[2]	auto[0]	auto[1]	24150	1			T36	6		T176	5932		T177	6
all_values[2]	auto[1]	auto[0]	190	1			T54	1		T119	2		T262	2
all_values[2]	auto[1]	auto[1]	147	1			T36	2		T176	6		T177	2
all_values[3]	auto[0]	auto[0]	789316	1			T1	2		T2	14687		T3	1
all_values[3]	auto[0]	auto[1]	24127	1			T36	5		T176	5932		T177	8
all_values[3]	auto[1]	auto[1]	170	1			T36	8		T176	5		T32	9
all_values[4]	auto[0]	auto[0]	789301	1			T1	2		T2	14687		T3	1
all_values[4]	auto[0]	auto[1]	24156	1			T36	8		T176	5933		T177	5
all_values[4]	auto[1]	auto[0]	19	1			T244	2		T247	3		T263	1
all_values[4]	auto[1]	auto[1]	137	1			T36	6		T176	5		T177	2
all_values[5]	auto[0]	auto[0]	789281	1			T1	2		T2	14687		T3	1
all_values[5]	auto[0]	auto[1]	24152	1			T36	9		T176	5930		T177	4
all_values[5]	auto[1]	auto[1]	180	1			T36	4		T176	7		T177	3
all_values[6]	auto[0]	auto[0]	790055	1			T1	2		T2	14687		T3	1
all_values[6]	auto[0]	auto[1]	23391	1			T36	8		T176	5935		T177	4
all_values[6]	auto[1]	auto[1]	167	1			T36	4		T176	3		T177	5
all_values[7]	auto[0]	auto[0]	759068	1			T1	2		T2	14552		T3	1
all_values[7]	auto[0]	auto[1]	22099	1			T36	2		T176	5529		T177	7
all_values[7]	auto[1]	auto[0]	30962	1			T2	135		T5	138		T7	107
all_values[7]	auto[1]	auto[1]	1484	1			T36	5		T176	409		T177	2
all_values[8]	auto[0]	auto[0]	789314	1			T1	2		T2	14687		T3	1
all_values[8]	auto[0]	auto[1]	24131	1			T36	11		T176	5930		T177	5
all_values[8]	auto[1]	auto[1]	168	1			T36	3		T176	7		T177	4
all_values[9]	auto[0]	auto[0]	186751	1			T1	2		T2	102		T3	1
all_values[9]	auto[0]	auto[1]	7127	1			T36	7		T176	755		T177	5
all_values[9]	auto[1]	auto[0]	602554	1			T2	14585		T5	9		T6	1
all_values[9]	auto[1]	auto[1]	17181	1			T36	7		T176	5183		T177	3
all_values[10]	auto[0]	auto[0]	790420	1			T1	2		T2	14687		T3	1
all_values[10]	auto[0]	auto[1]	23056	1			T36	6		T176	5599		T177	5
all_values[10]	auto[1]	auto[1]	137	1			T36	8		T176	2		T177	3
all_values[11]	auto[0]	auto[0]	2485	1			T2	9		T5	2		T6	5
all_values[11]	auto[0]	auto[1]	312	1			T36	9		T176	20		T177	5
all_values[11]	auto[1]	auto[0]	786797	1			T1	2		T2	14678		T3	1
all_values[11]	auto[1]	auto[1]	24019	1			T36	4		T176	5918		T177	3
all_values[12]	auto[0]	auto[0]	789970	1			T1	2		T2	14687		T3	1
all_values[12]	auto[0]	auto[1]	23449	1			T36	6		T176	5933		T177	3
all_values[12]	auto[1]	auto[0]	64	1			T54	1		T69	2		T60	1
all_values[12]	auto[1]	auto[1]	130	1			T36	8		T176	4		T177	1
all_values[13]	auto[0]	auto[0]	789303	1			T1	2		T2	14687		T3	1
all_values[13]	auto[0]	auto[1]	24129	1			T36	11		T176	5931		T177	4
all_values[13]	auto[1]	auto[1]	181	1			T36	3		T176	5		T177	4
all_values[14]	auto[0]	auto[0]	789289	1			T1	2		T2	14687		T3	1
all_values[14]	auto[0]	auto[1]	24147	1			T36	8		T176	5932		T177	7
all_values[14]	auto[1]	auto[1]	177	1			T36	6		T176	6		T177	2