Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	813613	1			T1	2		T2	14687		T3	1
all_pins[1]	813613	1			T1	2		T2	14687		T3	1
all_pins[2]	813613	1			T1	2		T2	14687		T3	1
all_pins[3]	813613	1			T1	2		T2	14687		T3	1
all_pins[4]	813613	1			T1	2		T2	14687		T3	1
all_pins[5]	813613	1			T1	2		T2	14687		T3	1
all_pins[6]	813613	1			T1	2		T2	14687		T3	1
all_pins[7]	813613	1			T1	2		T2	14687		T3	1
all_pins[8]	813613	1			T1	2		T2	14687		T3	1
all_pins[9]	813613	1			T1	2		T2	14687		T3	1
all_pins[10]	813613	1			T1	2		T2	14687		T3	1
all_pins[11]	813613	1			T1	2		T2	14687		T3	1
all_pins[12]	813613	1			T1	2		T2	14687		T3	1
all_pins[13]	813613	1			T1	2		T2	14687		T3	1
all_pins[14]	813613	1			T1	2		T2	14687		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10043194	1			T1	26		T2	176630		T3	13
values[0x1]	2161001	1			T1	4		T2	43675		T3	2
transitions[0x0=>0x1]	2160427	1			T1	4		T2	43675		T3	2
transitions[0x1=>0x0]	2159130	1			T1	3		T2	43674		T3	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	114889	1			T2	438		T5	455		T6	5
all_pins[0]	values[0x1]	698724	1			T1	2		T2	14249		T3	1
all_pins[0]	transitions[0x0=>0x1]	698442	1			T1	2		T2	14249		T3	1
all_pins[0]	transitions[0x1=>0x0]	76	1			T36	2		T176	2		T177	1
all_pins[1]	values[0x0]	813255	1			T1	2		T2	14687		T3	1
all_pins[1]	values[0x1]	358	1			T17	3		T261	5		T36	3
all_pins[1]	transitions[0x0=>0x1]	343	1			T17	3		T261	5		T36	3
all_pins[1]	transitions[0x1=>0x0]	111	1			T277	1		T278	1		T171	1
all_pins[2]	values[0x0]	813487	1			T1	2		T2	14687		T3	1
all_pins[2]	values[0x1]	126	1			T277	1		T278	1		T171	1
all_pins[2]	transitions[0x0=>0x1]	108	1			T277	1		T278	1		T171	1
all_pins[2]	transitions[0x1=>0x0]	76	1			T36	5		T176	2		T32	1
all_pins[3]	values[0x0]	813519	1			T1	2		T2	14687		T3	1
all_pins[3]	values[0x1]	94	1			T36	5		T176	3		T32	2
all_pins[3]	transitions[0x0=>0x1]	83	1			T36	5		T176	2		T32	2
all_pins[3]	transitions[0x1=>0x0]	73	1			T36	2		T176	2		T177	1
all_pins[4]	values[0x0]	813529	1			T1	2		T2	14687		T3	1
all_pins[4]	values[0x1]	84	1			T36	2		T176	3		T177	1
all_pins[4]	transitions[0x0=>0x1]	68	1			T36	1		T176	2		T177	1
all_pins[4]	transitions[0x1=>0x0]	89	1			T36	3		T176	3		T177	2
all_pins[5]	values[0x0]	813508	1			T1	2		T2	14687		T3	1
all_pins[5]	values[0x1]	105	1			T36	4		T176	4		T177	2
all_pins[5]	transitions[0x0=>0x1]	85	1			T36	3		T176	4		T177	2
all_pins[5]	transitions[0x1=>0x0]	62	1			T36	1		T177	3		T32	3
all_pins[6]	values[0x0]	813531	1			T1	2		T2	14687		T3	1
all_pins[6]	values[0x1]	82	1			T36	2		T177	3		T32	3
all_pins[6]	transitions[0x0=>0x1]	59	1			T36	2		T177	3		T32	3
all_pins[6]	transitions[0x1=>0x0]	34891	1			T2	162		T5	144		T7	131
all_pins[7]	values[0x0]	778699	1			T1	2		T2	14525		T3	1
all_pins[7]	values[0x1]	34914	1			T2	162		T5	144		T7	131
all_pins[7]	transitions[0x0=>0x1]	34889	1			T2	162		T5	144		T7	131
all_pins[7]	transitions[0x1=>0x0]	59	1			T36	1		T176	2		T32	3
all_pins[8]	values[0x0]	813529	1			T1	2		T2	14687		T3	1
all_pins[8]	values[0x1]	84	1			T36	1		T176	2		T177	1
all_pins[8]	transitions[0x0=>0x1]	63	1			T36	1		T176	1		T32	4
all_pins[8]	transitions[0x1=>0x0]	619646	1			T2	14586		T5	9		T6	1
all_pins[9]	values[0x0]	193946	1			T1	2		T2	101		T3	1
all_pins[9]	values[0x1]	619667	1			T2	14586		T5	9		T6	1
all_pins[9]	transitions[0x0=>0x1]	619650	1			T2	14586		T5	9		T6	1
all_pins[9]	transitions[0x1=>0x0]	48	1			T36	2		T177	2		T32	1
all_pins[10]	values[0x0]	813548	1			T1	2		T2	14687		T3	1
all_pins[10]	values[0x1]	65	1			T36	4		T177	3		T32	2
all_pins[10]	transitions[0x0=>0x1]	50	1			T36	2		T177	1		T32	2
all_pins[10]	transitions[0x1=>0x0]	806387	1			T1	2		T2	14678		T3	1
all_pins[11]	values[0x0]	7211	1			T2	9		T5	2		T6	5
all_pins[11]	values[0x1]	806402	1			T1	2		T2	14678		T3	1
all_pins[11]	transitions[0x0=>0x1]	806369	1			T1	2		T2	14678		T3	1
all_pins[11]	transitions[0x1=>0x0]	97	1			T54	1		T69	2		T60	1
all_pins[12]	values[0x0]	813483	1			T1	2		T2	14687		T3	1
all_pins[12]	values[0x1]	130	1			T54	1		T69	2		T60	1
all_pins[12]	transitions[0x0=>0x1]	111	1			T54	1		T69	2		T60	1
all_pins[12]	transitions[0x1=>0x0]	62	1			T36	1		T177	1		T32	1
all_pins[13]	values[0x0]	813532	1			T1	2		T2	14687		T3	1
all_pins[13]	values[0x1]	81	1			T36	1		T177	1		T32	1
all_pins[13]	transitions[0x0=>0x1]	59	1			T177	1		T32	1		T279	1
all_pins[13]	transitions[0x1=>0x0]	63	1			T36	4		T32	2		T279	2
all_pins[14]	values[0x0]	813528	1			T1	2		T2	14687		T3	1
all_pins[14]	values[0x1]	85	1			T36	5		T32	2		T279	2
all_pins[14]	transitions[0x0=>0x1]	48	1			T36	3		T123	3		T124	1
all_pins[14]	transitions[0x1=>0x0]	697390	1			T1	1		T2	14248		T4	1