Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	357	1			T36	11		T176	11		T177	7
all_values[1]	357	1			T36	11		T176	11		T177	7
all_values[2]	357	1			T36	11		T176	11		T177	7
all_values[3]	357	1			T36	11		T176	11		T177	7
all_values[4]	357	1			T36	11		T176	11		T177	7
all_values[5]	357	1			T36	11		T176	11		T177	7
all_values[6]	357	1			T36	11		T176	11		T177	7
all_values[7]	357	1			T36	11		T176	11		T177	7
all_values[8]	357	1			T36	11		T176	11		T177	7
all_values[9]	357	1			T36	11		T176	11		T177	7
all_values[10]	357	1			T36	11		T176	11		T177	7
all_values[11]	357	1			T36	11		T176	11		T177	7
all_values[12]	357	1			T36	11		T176	11		T177	7
all_values[13]	357	1			T36	11		T176	11		T177	7
all_values[14]	357	1			T36	11		T176	11		T177	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2925

1

T36

75

T176

122

T177

57

auto[1]

2430

1

T36

90

T176

43

T177

48

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

941

1

T36

18

T176

13

T177

16

auto[1]

4414

1

T36

147

T176

152

T177

89

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3206

1

T36

93

T176

97

T177

62

auto[1]

2149

1

T36

72

T176

68

T177

43

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	30	1			T36	2		T176	2		T32	1
all_values[0]	auto[0]	auto[0]	auto[1]	71	1			T36	3		T176	3		T177	1
all_values[0]	auto[0]	auto[1]	auto[0]	16	1			T32	1		T280	1		T281	1
all_values[0]	auto[0]	auto[1]	auto[1]	93	1			T36	2		T176	3		T177	1
all_values[0]	auto[1]	auto[0]	auto[1]	80	1			T36	1		T176	3		T177	4
all_values[0]	auto[1]	auto[1]	auto[1]	67	1			T36	3		T177	1		T32	1
all_values[1]	auto[0]	auto[0]	auto[0]	32	1			T176	1		T177	1		T279	1
all_values[1]	auto[0]	auto[0]	auto[1]	98	1			T36	1		T176	4		T177	2
all_values[1]	auto[0]	auto[1]	auto[0]	14	1			T123	3		T125	1		T128	1
all_values[1]	auto[0]	auto[1]	auto[1]	66	1			T36	4		T176	1		T177	1
all_values[1]	auto[1]	auto[0]	auto[1]	89	1			T36	4		T176	5		T177	2
all_values[1]	auto[1]	auto[1]	auto[1]	58	1			T36	2		T177	1		T32	2
all_values[2]	auto[0]	auto[0]	auto[0]	49	1			T36	5		T177	1		T32	1
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T36	1		T176	4		T177	1
all_values[2]	auto[0]	auto[1]	auto[0]	25	1			T32	1		T123	3		T282	2
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T36	3		T176	1		T177	3
all_values[2]	auto[1]	auto[0]	auto[1]	84	1			T36	2		T176	6		T177	1
all_values[2]	auto[1]	auto[1]	auto[1]	63	1			T177	1		T32	3		T123	1
all_values[3]	auto[0]	auto[0]	auto[0]	45	1			T36	1		T176	1		T177	1
all_values[3]	auto[0]	auto[0]	auto[1]	61	1			T36	1		T176	3		T32	5
all_values[3]	auto[0]	auto[1]	auto[0]	30	1			T123	2		T124	1		T283	1
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T36	3		T176	1		T177	3
all_values[3]	auto[1]	auto[0]	auto[1]	75	1			T36	1		T176	2		T32	3
all_values[3]	auto[1]	auto[1]	auto[1]	69	1			T36	5		T176	4		T177	3
all_values[4]	auto[0]	auto[0]	auto[0]	43	1			T177	1		T279	1		T124	4
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T36	4		T176	3		T177	1
all_values[4]	auto[0]	auto[1]	auto[0]	33	1			T177	1		T279	1		T127	3
all_values[4]	auto[0]	auto[1]	auto[1]	69	1			T36	1		T176	3		T177	2
all_values[4]	auto[1]	auto[0]	auto[1]	85	1			T36	4		T176	4		T177	1
all_values[4]	auto[1]	auto[1]	auto[1]	52	1			T36	2		T176	1		T177	1
all_values[5]	auto[0]	auto[0]	auto[0]	30	1			T36	1		T176	1		T177	2
all_values[5]	auto[0]	auto[0]	auto[1]	76	1			T36	2		T176	2		T32	3
all_values[5]	auto[0]	auto[1]	auto[0]	10	1			T282	1		T283	2		T284	1
all_values[5]	auto[0]	auto[1]	auto[1]	90	1			T36	4		T176	3		T177	4
all_values[5]	auto[1]	auto[0]	auto[1]	78	1			T176	3		T177	1		T32	2
all_values[5]	auto[1]	auto[1]	auto[1]	73	1			T36	4		T176	2		T32	2
all_values[6]	auto[0]	auto[0]	auto[0]	30	1			T36	1		T279	4		T123	1
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T36	2		T176	7		T32	1
all_values[6]	auto[0]	auto[1]	auto[0]	20	1			T36	1		T282	1		T280	1
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T36	3		T176	1		T177	4
all_values[6]	auto[1]	auto[0]	auto[1]	87	1			T36	1		T176	3		T177	1
all_values[6]	auto[1]	auto[1]	auto[1]	63	1			T36	3		T177	2		T32	1
all_values[7]	auto[0]	auto[0]	auto[0]	44	1			T36	3		T124	1		T280	2
all_values[7]	auto[0]	auto[0]	auto[1]	60	1			T36	1		T176	2		T32	1
all_values[7]	auto[0]	auto[1]	auto[0]	34	1			T36	3		T282	4		T280	2
all_values[7]	auto[0]	auto[1]	auto[1]	84	1			T36	1		T176	3		T177	2
all_values[7]	auto[1]	auto[0]	auto[1]	85	1			T36	3		T176	5		T177	3
all_values[7]	auto[1]	auto[1]	auto[1]	50	1			T176	1		T177	2		T32	2
all_values[8]	auto[0]	auto[0]	auto[0]	36	1			T176	1		T123	1		T282	1
all_values[8]	auto[0]	auto[0]	auto[1]	69	1			T36	1		T176	3		T177	3
all_values[8]	auto[0]	auto[1]	auto[0]	36	1			T280	2		T285	1		T286	2
all_values[8]	auto[0]	auto[1]	auto[1]	80	1			T36	5		T176	2		T177	2
all_values[8]	auto[1]	auto[0]	auto[1]	75	1			T36	3		T176	2		T177	2
all_values[8]	auto[1]	auto[1]	auto[1]	61	1			T36	2		T176	3		T32	1
all_values[9]	auto[0]	auto[0]	auto[0]	46	1			T177	1		T32	1		T282	1
all_values[9]	auto[0]	auto[0]	auto[1]	76	1			T36	2		T176	7		T32	5
all_values[9]	auto[0]	auto[1]	auto[0]	18	1			T32	1		T123	1		T285	1
all_values[9]	auto[0]	auto[1]	auto[1]	77	1			T36	4		T176	1		T177	3
all_values[9]	auto[1]	auto[0]	auto[1]	74	1			T36	3		T176	1		T177	2
all_values[9]	auto[1]	auto[1]	auto[1]	66	1			T36	2		T176	2		T177	1
all_values[10]	auto[0]	auto[0]	auto[0]	51	1			T176	2		T177	1		T123	2
all_values[10]	auto[0]	auto[0]	auto[1]	76	1			T36	1		T176	4		T177	3
all_values[10]	auto[0]	auto[1]	auto[0]	29	1			T176	2		T279	4		T282	1
all_values[10]	auto[0]	auto[1]	auto[1]	64	1			T36	2		T176	1		T32	1
all_values[10]	auto[1]	auto[0]	auto[1]	76	1			T36	4		T176	2		T177	1
all_values[10]	auto[1]	auto[1]	auto[1]	61	1			T36	4		T177	2		T32	3
all_values[11]	auto[0]	auto[0]	auto[0]	30	1			T36	1		T177	1		T123	1
all_values[11]	auto[0]	auto[0]	auto[1]	84	1			T36	1		T176	5		T177	2
all_values[11]	auto[0]	auto[1]	auto[0]	13	1			T280	1		T285	1		T287	1
all_values[11]	auto[0]	auto[1]	auto[1]	82	1			T36	5		T176	1		T177	1
all_values[11]	auto[1]	auto[0]	auto[1]	83	1			T36	1		T176	5		T177	2
all_values[11]	auto[1]	auto[1]	auto[1]	65	1			T36	3		T177	1		T32	3
all_values[12]	auto[0]	auto[0]	auto[0]	50	1			T176	1		T177	3		T32	1
all_values[12]	auto[0]	auto[0]	auto[1]	70	1			T36	2		T176	4		T177	1
all_values[12]	auto[0]	auto[1]	auto[0]	34	1			T177	2		T32	1		T279	2
all_values[12]	auto[0]	auto[1]	auto[1]	73	1			T36	1		T176	2		T32	5
all_values[12]	auto[1]	auto[0]	auto[1]	76	1			T36	3		T176	3		T177	1
all_values[12]	auto[1]	auto[1]	auto[1]	54	1			T36	5		T176	1		T279	1
all_values[13]	auto[0]	auto[0]	auto[0]	31	1			T176	1		T177	1		T124	1
all_values[13]	auto[0]	auto[0]	auto[1]	80	1			T36	5		T176	4		T177	3
all_values[13]	auto[0]	auto[1]	auto[0]	30	1			T176	1		T282	2		T124	3
all_values[13]	auto[0]	auto[1]	auto[1]	64	1			T36	4		T176	1		T123	3
all_values[13]	auto[1]	auto[0]	auto[1]	89	1			T36	1		T176	2		T177	1
all_values[13]	auto[1]	auto[1]	auto[1]	63	1			T36	1		T176	2		T177	2
all_values[14]	auto[0]	auto[0]	auto[0]	34	1			T124	2		T285	1		T126	2
all_values[14]	auto[0]	auto[0]	auto[1]	76	1			T36	1		T176	5		T177	2
all_values[14]	auto[0]	auto[1]	auto[0]	18	1			T282	2		T280	2		T128	1
all_values[14]	auto[0]	auto[1]	auto[1]	81	1			T36	5		T177	1		T32	3
all_values[14]	auto[1]	auto[0]	auto[1]	87	1			T36	2		T176	6		T177	3
all_values[14]	auto[1]	auto[1]	auto[1]	61	1			T36	3		T177	1		T32	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal