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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.28 97.21 89.46 97.22 72.02 94.26 98.44 90.32


Total test records in report: 1847
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T1764 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2694000371 Aug 11 04:56:17 PM PDT 24 Aug 11 04:56:18 PM PDT 24 162480306 ps
T1765 /workspace/coverage/cover_reg_top/24.i2c_intr_test.3324746959 Aug 11 04:56:42 PM PDT 24 Aug 11 04:56:43 PM PDT 24 37559472 ps
T1766 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.18129165 Aug 11 04:56:33 PM PDT 24 Aug 11 04:56:34 PM PDT 24 160258998 ps
T1767 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1811399425 Aug 11 04:56:35 PM PDT 24 Aug 11 04:56:37 PM PDT 24 84901706 ps
T1768 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2537465547 Aug 11 04:56:17 PM PDT 24 Aug 11 04:56:18 PM PDT 24 25653294 ps
T1769 /workspace/coverage/cover_reg_top/49.i2c_intr_test.853404322 Aug 11 04:56:45 PM PDT 24 Aug 11 04:56:46 PM PDT 24 23478337 ps
T220 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3043654929 Aug 11 04:55:54 PM PDT 24 Aug 11 04:55:55 PM PDT 24 40764943 ps
T1770 /workspace/coverage/cover_reg_top/29.i2c_intr_test.1232085547 Aug 11 04:56:39 PM PDT 24 Aug 11 04:56:40 PM PDT 24 27304806 ps
T1771 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.907797465 Aug 11 04:56:34 PM PDT 24 Aug 11 04:56:35 PM PDT 24 26848592 ps
T1772 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3578519486 Aug 11 04:56:06 PM PDT 24 Aug 11 04:56:08 PM PDT 24 47182838 ps
T1773 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.4016360709 Aug 11 04:56:06 PM PDT 24 Aug 11 04:56:09 PM PDT 24 42339066 ps
T1774 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1348229308 Aug 11 04:56:27 PM PDT 24 Aug 11 04:56:28 PM PDT 24 101364338 ps
T1775 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.233810530 Aug 11 04:55:59 PM PDT 24 Aug 11 04:56:01 PM PDT 24 115766392 ps
T1776 /workspace/coverage/cover_reg_top/4.i2c_intr_test.1375266548 Aug 11 04:56:05 PM PDT 24 Aug 11 04:56:06 PM PDT 24 19640992 ps
T1777 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.156826474 Aug 11 04:56:33 PM PDT 24 Aug 11 04:56:36 PM PDT 24 115923966 ps
T284 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1651774643 Aug 11 04:56:39 PM PDT 24 Aug 11 04:56:40 PM PDT 24 50578217 ps
T1778 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1485726393 Aug 11 04:56:24 PM PDT 24 Aug 11 04:56:26 PM PDT 24 76193379 ps
T210 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4080166911 Aug 11 04:56:30 PM PDT 24 Aug 11 04:56:33 PM PDT 24 136515983 ps
T1779 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.537394955 Aug 11 04:56:35 PM PDT 24 Aug 11 04:56:36 PM PDT 24 123491309 ps
T1780 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.422555169 Aug 11 04:55:54 PM PDT 24 Aug 11 04:55:55 PM PDT 24 34022843 ps
T1781 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3183960029 Aug 11 04:56:28 PM PDT 24 Aug 11 04:56:29 PM PDT 24 86860968 ps
T221 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3152653215 Aug 11 04:56:02 PM PDT 24 Aug 11 04:56:05 PM PDT 24 95256653 ps
T1782 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2634074690 Aug 11 04:56:27 PM PDT 24 Aug 11 04:56:28 PM PDT 24 19667859 ps
T222 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.976160155 Aug 11 04:55:50 PM PDT 24 Aug 11 04:55:50 PM PDT 24 68791239 ps
T1783 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1744349788 Aug 11 04:56:22 PM PDT 24 Aug 11 04:56:23 PM PDT 24 31581590 ps
T1784 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.867721655 Aug 11 04:55:53 PM PDT 24 Aug 11 04:55:55 PM PDT 24 68587230 ps
T1785 /workspace/coverage/cover_reg_top/38.i2c_intr_test.4148672401 Aug 11 04:56:50 PM PDT 24 Aug 11 04:56:51 PM PDT 24 33926083 ps
T1786 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3811500010 Aug 11 04:55:55 PM PDT 24 Aug 11 04:55:57 PM PDT 24 349192988 ps
T1787 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3398100081 Aug 11 04:56:36 PM PDT 24 Aug 11 04:56:37 PM PDT 24 326577116 ps
T1788 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3831703655 Aug 11 04:56:25 PM PDT 24 Aug 11 04:56:26 PM PDT 24 86441784 ps
T1789 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1825754921 Aug 11 04:56:34 PM PDT 24 Aug 11 04:56:35 PM PDT 24 18155604 ps
T1790 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3775227457 Aug 11 04:56:12 PM PDT 24 Aug 11 04:56:15 PM PDT 24 302449019 ps
T1791 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3496610743 Aug 11 04:55:47 PM PDT 24 Aug 11 04:55:48 PM PDT 24 42855652 ps
T208 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3160804996 Aug 11 04:56:06 PM PDT 24 Aug 11 04:56:08 PM PDT 24 422309035 ps
T1792 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1457772464 Aug 11 04:56:00 PM PDT 24 Aug 11 04:56:06 PM PDT 24 698515560 ps
T1793 /workspace/coverage/cover_reg_top/31.i2c_intr_test.877947814 Aug 11 04:56:42 PM PDT 24 Aug 11 04:56:43 PM PDT 24 55181635 ps
T1794 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.289901340 Aug 11 04:56:39 PM PDT 24 Aug 11 04:56:40 PM PDT 24 186146134 ps
T1795 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.822438739 Aug 11 04:55:50 PM PDT 24 Aug 11 04:55:52 PM PDT 24 107297554 ps
T1796 /workspace/coverage/cover_reg_top/16.i2c_intr_test.4162093142 Aug 11 04:56:34 PM PDT 24 Aug 11 04:56:35 PM PDT 24 31676771 ps
T209 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1234827062 Aug 11 04:56:11 PM PDT 24 Aug 11 04:56:12 PM PDT 24 148094778 ps
T223 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1320326900 Aug 11 04:56:33 PM PDT 24 Aug 11 04:56:34 PM PDT 24 18031837 ps
T1797 /workspace/coverage/cover_reg_top/34.i2c_intr_test.2316613968 Aug 11 04:56:38 PM PDT 24 Aug 11 04:56:39 PM PDT 24 33825653 ps
T1798 /workspace/coverage/cover_reg_top/33.i2c_intr_test.3319198217 Aug 11 04:56:42 PM PDT 24 Aug 11 04:56:43 PM PDT 24 16498568 ps
T1799 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1208419351 Aug 11 04:56:45 PM PDT 24 Aug 11 04:56:46 PM PDT 24 43302046 ps
T1800 /workspace/coverage/cover_reg_top/0.i2c_intr_test.2600990384 Aug 11 04:55:47 PM PDT 24 Aug 11 04:55:48 PM PDT 24 59261476 ps
T1801 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.216576167 Aug 11 04:56:05 PM PDT 24 Aug 11 04:56:06 PM PDT 24 21423089 ps
T1802 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2818480375 Aug 11 04:56:23 PM PDT 24 Aug 11 04:56:25 PM PDT 24 105721898 ps
T1803 /workspace/coverage/cover_reg_top/21.i2c_intr_test.4105225717 Aug 11 04:56:39 PM PDT 24 Aug 11 04:56:40 PM PDT 24 15494451 ps
T1804 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1106140677 Aug 11 04:56:27 PM PDT 24 Aug 11 04:56:29 PM PDT 24 96025738 ps
T1805 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3562109921 Aug 11 04:56:47 PM PDT 24 Aug 11 04:56:48 PM PDT 24 53316719 ps
T1806 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2853744593 Aug 11 04:56:27 PM PDT 24 Aug 11 04:56:29 PM PDT 24 81995704 ps
T1807 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1102541123 Aug 11 04:56:46 PM PDT 24 Aug 11 04:56:47 PM PDT 24 34846357 ps
T1808 /workspace/coverage/cover_reg_top/25.i2c_intr_test.968740567 Aug 11 04:56:43 PM PDT 24 Aug 11 04:56:43 PM PDT 24 36848545 ps
T211 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.937039897 Aug 11 04:56:14 PM PDT 24 Aug 11 04:56:16 PM PDT 24 168336070 ps
T1809 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1128223099 Aug 11 04:55:58 PM PDT 24 Aug 11 04:55:59 PM PDT 24 56392826 ps
T1810 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1972403326 Aug 11 04:56:40 PM PDT 24 Aug 11 04:56:41 PM PDT 24 20529858 ps
T1811 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4074024179 Aug 11 04:56:26 PM PDT 24 Aug 11 04:56:27 PM PDT 24 116599084 ps
T1812 /workspace/coverage/cover_reg_top/40.i2c_intr_test.104838126 Aug 11 04:56:50 PM PDT 24 Aug 11 04:56:51 PM PDT 24 90498924 ps
T1813 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.870638859 Aug 11 04:56:34 PM PDT 24 Aug 11 04:56:35 PM PDT 24 159328880 ps
T1814 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.338677720 Aug 11 04:56:28 PM PDT 24 Aug 11 04:56:29 PM PDT 24 36608567 ps
T224 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.628745147 Aug 11 04:56:39 PM PDT 24 Aug 11 04:56:40 PM PDT 24 16445531 ps
T1815 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2912869269 Aug 11 04:55:59 PM PDT 24 Aug 11 04:56:00 PM PDT 24 78676228 ps
T1816 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4207714144 Aug 11 04:56:09 PM PDT 24 Aug 11 04:56:10 PM PDT 24 214425764 ps
T1817 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1798537601 Aug 11 04:56:26 PM PDT 24 Aug 11 04:56:27 PM PDT 24 23253844 ps
T1818 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1772004338 Aug 11 04:55:57 PM PDT 24 Aug 11 04:56:00 PM PDT 24 96951308 ps
T1819 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3039234846 Aug 11 04:56:23 PM PDT 24 Aug 11 04:56:24 PM PDT 24 33502984 ps
T1820 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2255885950 Aug 11 04:56:45 PM PDT 24 Aug 11 04:56:46 PM PDT 24 52729822 ps
T1821 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1046433355 Aug 11 04:56:23 PM PDT 24 Aug 11 04:56:24 PM PDT 24 202365519 ps
T1822 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3074927872 Aug 11 04:56:28 PM PDT 24 Aug 11 04:56:29 PM PDT 24 72309648 ps
T1823 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4198848133 Aug 11 04:56:13 PM PDT 24 Aug 11 04:56:14 PM PDT 24 51632009 ps
T1824 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3970622502 Aug 11 04:56:34 PM PDT 24 Aug 11 04:56:35 PM PDT 24 74579272 ps
T1825 /workspace/coverage/cover_reg_top/26.i2c_intr_test.2577651313 Aug 11 04:56:38 PM PDT 24 Aug 11 04:56:39 PM PDT 24 17209354 ps
T1826 /workspace/coverage/cover_reg_top/44.i2c_intr_test.3757464443 Aug 11 04:56:50 PM PDT 24 Aug 11 04:56:51 PM PDT 24 60690358 ps
T1827 /workspace/coverage/cover_reg_top/11.i2c_intr_test.979894858 Aug 11 04:56:26 PM PDT 24 Aug 11 04:56:27 PM PDT 24 68672478 ps
T1828 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.971749881 Aug 11 04:56:14 PM PDT 24 Aug 11 04:56:17 PM PDT 24 461348909 ps
T1829 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.592123258 Aug 11 04:55:46 PM PDT 24 Aug 11 04:55:49 PM PDT 24 245159274 ps
T1830 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.305305205 Aug 11 04:56:28 PM PDT 24 Aug 11 04:56:30 PM PDT 24 126720902 ps
T225 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3800891470 Aug 11 04:56:22 PM PDT 24 Aug 11 04:56:23 PM PDT 24 54317379 ps
T264 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3011822235 Aug 11 04:56:00 PM PDT 24 Aug 11 04:56:01 PM PDT 24 322854379 ps
T226 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2596987112 Aug 11 04:56:28 PM PDT 24 Aug 11 04:56:29 PM PDT 24 181682114 ps
T1831 /workspace/coverage/cover_reg_top/3.i2c_intr_test.1976844843 Aug 11 04:55:59 PM PDT 24 Aug 11 04:56:00 PM PDT 24 22778271 ps
T1832 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1359725475 Aug 11 04:56:39 PM PDT 24 Aug 11 04:56:40 PM PDT 24 25453220 ps
T1833 /workspace/coverage/cover_reg_top/10.i2c_intr_test.1912761785 Aug 11 04:56:26 PM PDT 24 Aug 11 04:56:27 PM PDT 24 33848762 ps
T1834 /workspace/coverage/cover_reg_top/22.i2c_intr_test.284862020 Aug 11 04:56:43 PM PDT 24 Aug 11 04:56:44 PM PDT 24 14693489 ps
T1835 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1287672942 Aug 11 04:55:47 PM PDT 24 Aug 11 04:55:48 PM PDT 24 100201284 ps
T1836 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3366707033 Aug 11 04:56:27 PM PDT 24 Aug 11 04:56:29 PM PDT 24 43611820 ps
T1837 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1245030462 Aug 11 04:56:35 PM PDT 24 Aug 11 04:56:35 PM PDT 24 25225582 ps
T1838 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3901735765 Aug 11 04:56:28 PM PDT 24 Aug 11 04:56:31 PM PDT 24 234069075 ps
T1839 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4049673355 Aug 11 04:55:53 PM PDT 24 Aug 11 04:55:54 PM PDT 24 27508751 ps
T1840 /workspace/coverage/cover_reg_top/7.i2c_intr_test.3920055804 Aug 11 04:56:14 PM PDT 24 Aug 11 04:56:15 PM PDT 24 26602800 ps
T1841 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.162067269 Aug 11 04:56:23 PM PDT 24 Aug 11 04:56:24 PM PDT 24 270096679 ps
T1842 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.296007397 Aug 11 04:55:53 PM PDT 24 Aug 11 04:55:55 PM PDT 24 65408681 ps
T1843 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2053635972 Aug 11 04:56:28 PM PDT 24 Aug 11 04:56:29 PM PDT 24 31063020 ps
T1844 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.434522848 Aug 11 04:56:17 PM PDT 24 Aug 11 04:56:19 PM PDT 24 60969256 ps
T1845 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1467851879 Aug 11 04:56:33 PM PDT 24 Aug 11 04:56:35 PM PDT 24 114026820 ps
T1846 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1146144539 Aug 11 04:56:27 PM PDT 24 Aug 11 04:56:27 PM PDT 24 36758791 ps
T1847 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2242095381 Aug 11 04:56:24 PM PDT 24 Aug 11 04:56:24 PM PDT 24 43643561 ps

Test location /workspace/coverage/default/48.i2c_host_error_intr.2012926362
Short name T9
Test name
Test status
Simulation time 293237540 ps
CPU time 4.45 seconds
Started Aug 11 05:33:54 PM PDT 24
Finished Aug 11 05:33:58 PM PDT 24
Peak memory 227332 kb
Host smart-83c42b21-a979-4b22-948e-dc6311510b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012926362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2012926362
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.2851172046
Short name T1
Test name
Test status
Simulation time 1003037028 ps
CPU time 3.41 seconds
Started Aug 11 05:29:00 PM PDT 24
Finished Aug 11 05:29:03 PM PDT 24
Peak memory 232468 kb
Host smart-8660f84a-8c5b-41d8-8a56-f5ea07d8375d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851172046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.2851172046
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.1150152725
Short name T36
Test name
Test status
Simulation time 49921484740 ps
CPU time 442.44 seconds
Started Aug 11 05:25:49 PM PDT 24
Finished Aug 11 05:33:12 PM PDT 24
Peak memory 1510752 kb
Host smart-86cd01bb-0d28-4692-874a-ab00b4262582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150152725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.1150152725
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.673965088
Short name T51
Test name
Test status
Simulation time 2666421380 ps
CPU time 12.74 seconds
Started Aug 11 05:25:34 PM PDT 24
Finished Aug 11 05:25:47 PM PDT 24
Peak memory 214288 kb
Host smart-602ffabe-cd01-4b7a-9403-a0361eb9cad1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673965088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.673965088
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.3228283977
Short name T71
Test name
Test status
Simulation time 26831205984 ps
CPU time 162.67 seconds
Started Aug 11 05:29:43 PM PDT 24
Finished Aug 11 05:32:26 PM PDT 24
Peak memory 1734468 kb
Host smart-0905f455-a4a5-4c4a-811b-a0f601a3d9ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228283977 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.3228283977
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2738143122
Short name T98
Test name
Test status
Simulation time 191237769 ps
CPU time 2.38 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 04:55:50 PM PDT 24
Peak memory 204364 kb
Host smart-978321f6-c6fa-4d54-8e60-d2889323cdb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738143122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2738143122
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2611029196
Short name T19
Test name
Test status
Simulation time 505851402 ps
CPU time 20.48 seconds
Started Aug 11 05:28:31 PM PDT 24
Finished Aug 11 05:28:51 PM PDT 24
Peak memory 205496 kb
Host smart-2a78d32e-949d-4f7e-bebd-28f977c4bbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611029196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2611029196
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_target_nack_txstretch.800317155
Short name T3
Test name
Test status
Simulation time 235014760 ps
CPU time 1.34 seconds
Started Aug 11 05:33:13 PM PDT 24
Finished Aug 11 05:33:15 PM PDT 24
Peak memory 222336 kb
Host smart-a6c22747-cddc-4dca-a6b0-df6803a745f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800317155 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_nack_txstretch.800317155
Directory /workspace/43.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/32.i2c_host_override.106092653
Short name T140
Test name
Test status
Simulation time 51631565 ps
CPU time 0.69 seconds
Started Aug 11 05:31:12 PM PDT 24
Finished Aug 11 05:31:13 PM PDT 24
Peak memory 205292 kb
Host smart-b42b6e19-629c-4fd5-8c50-23f22167d5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106092653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.106092653
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull_addr.883659406
Short name T60
Test name
Test status
Simulation time 513906776 ps
CPU time 2.76 seconds
Started Aug 11 05:28:59 PM PDT 24
Finished Aug 11 05:29:02 PM PDT 24
Peak memory 205552 kb
Host smart-a8d3a9bd-059c-4eb1-8743-de6816a612c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883659406 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.i2c_target_nack_acqfull_addr.883659406
Directory /workspace/18.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3101659669
Short name T5
Test name
Test status
Simulation time 6607731537 ps
CPU time 238.26 seconds
Started Aug 11 05:31:40 PM PDT 24
Finished Aug 11 05:35:38 PM PDT 24
Peak memory 782880 kb
Host smart-91de5bd5-f51d-4e96-9096-448c0563cdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101659669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3101659669
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.794722780
Short name T199
Test name
Test status
Simulation time 116212782 ps
CPU time 1.75 seconds
Started Aug 11 04:56:27 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 204476 kb
Host smart-756dcd1d-0f09-4d5a-bdd5-d4ff694b2fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794722780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.794722780
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3669607708
Short name T30
Test name
Test status
Simulation time 449623468 ps
CPU time 1.08 seconds
Started Aug 11 05:32:45 PM PDT 24
Finished Aug 11 05:32:46 PM PDT 24
Peak memory 205324 kb
Host smart-00b469e6-8f0b-445c-b344-0ed17e989595
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669607708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3669607708
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_alert_test.651450657
Short name T366
Test name
Test status
Simulation time 16965391 ps
CPU time 0.62 seconds
Started Aug 11 05:29:07 PM PDT 24
Finished Aug 11 05:29:08 PM PDT 24
Peak memory 204784 kb
Host smart-a0501b91-6094-4096-8780-83cd8f96f91a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651450657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.651450657
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.3841774136
Short name T125
Test name
Test status
Simulation time 16663129125 ps
CPU time 128.6 seconds
Started Aug 11 05:30:33 PM PDT 24
Finished Aug 11 05:32:42 PM PDT 24
Peak memory 541336 kb
Host smart-64949eae-19ee-474a-a94c-135a955e6f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841774136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3841774136
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1709627333
Short name T217
Test name
Test status
Simulation time 20320907 ps
CPU time 0.79 seconds
Started Aug 11 04:56:29 PM PDT 24
Finished Aug 11 04:56:30 PM PDT 24
Peak memory 204316 kb
Host smart-f7f75b25-f9d1-4567-ba04-8ec07ca4e5e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709627333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1709627333
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.4191297087
Short name T276
Test name
Test status
Simulation time 70742943978 ps
CPU time 827.43 seconds
Started Aug 11 05:32:45 PM PDT 24
Finished Aug 11 05:46:32 PM PDT 24
Peak memory 4351816 kb
Host smart-fdc6442c-0ab2-4665-84c6-693fb2942882
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191297087 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.4191297087
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1102529546
Short name T13
Test name
Test status
Simulation time 26588364106 ps
CPU time 101.51 seconds
Started Aug 11 05:33:44 PM PDT 24
Finished Aug 11 05:35:26 PM PDT 24
Peak memory 412128 kb
Host smart-7c39f682-6b71-4b49-bf05-b8e36db03567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102529546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1102529546
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull.2785819913
Short name T53
Test name
Test status
Simulation time 949092268 ps
CPU time 2.75 seconds
Started Aug 11 05:29:49 PM PDT 24
Finished Aug 11 05:29:52 PM PDT 24
Peak memory 213824 kb
Host smart-22aefeaf-adea-44ab-ad14-24f30eb826be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785819913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_nack_acqfull.2785819913
Directory /workspace/23.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.4074551129
Short name T282
Test name
Test status
Simulation time 12797643202 ps
CPU time 299.95 seconds
Started Aug 11 05:30:13 PM PDT 24
Finished Aug 11 05:35:13 PM PDT 24
Peak memory 1485452 kb
Host smart-f6ffecd7-9cb6-4030-b35c-aea6b219318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074551129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.4074551129
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull.1152566539
Short name T68
Test name
Test status
Simulation time 1133630078 ps
CPU time 3.07 seconds
Started Aug 11 05:30:10 PM PDT 24
Finished Aug 11 05:30:13 PM PDT 24
Peak memory 213860 kb
Host smart-4b09247a-d838-4b35-90ba-8afced31fe4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152566539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_nack_acqfull.1152566539
Directory /workspace/25.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.2870468778
Short name T449
Test name
Test status
Simulation time 2051012136 ps
CPU time 5.55 seconds
Started Aug 11 05:25:31 PM PDT 24
Finished Aug 11 05:25:36 PM PDT 24
Peak memory 215504 kb
Host smart-d1564c7b-6e89-4c00-842a-9ad878dff99a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870468778 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.2870468778
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.2299891308
Short name T187
Test name
Test status
Simulation time 68030053 ps
CPU time 0.91 seconds
Started Aug 11 05:25:28 PM PDT 24
Finished Aug 11 05:25:29 PM PDT 24
Peak memory 223920 kb
Host smart-da7db76c-6ff7-4511-958e-36f82b8d2339
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299891308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.2299891308
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3498042787
Short name T76
Test name
Test status
Simulation time 5115382237 ps
CPU time 128.3 seconds
Started Aug 11 05:28:13 PM PDT 24
Finished Aug 11 05:30:21 PM PDT 24
Peak memory 1477684 kb
Host smart-58e99154-312e-426c-a4d3-838479c667ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498042787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3498042787
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.1661865876
Short name T285
Test name
Test status
Simulation time 24622239 ps
CPU time 0.69 seconds
Started Aug 11 04:56:47 PM PDT 24
Finished Aug 11 04:56:48 PM PDT 24
Peak memory 204216 kb
Host smart-45a99450-2fec-4f13-b293-0defc6b2791b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661865876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1661865876
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.1737664570
Short name T244
Test name
Test status
Simulation time 1207604319 ps
CPU time 25.07 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:31:23 PM PDT 24
Peak memory 205532 kb
Host smart-5ead825e-7a78-4fc9-b3b9-213d4ecef4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737664570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1737664570
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.869944641
Short name T170
Test name
Test status
Simulation time 133952301 ps
CPU time 3.53 seconds
Started Aug 11 05:28:14 PM PDT 24
Finished Aug 11 05:28:18 PM PDT 24
Peak memory 224400 kb
Host smart-7631ff6e-9833-4a9f-b901-1003e202bc38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869944641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.
869944641
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.1549505537
Short name T249
Test name
Test status
Simulation time 906920191 ps
CPU time 7.21 seconds
Started Aug 11 05:30:39 PM PDT 24
Finished Aug 11 05:30:46 PM PDT 24
Peak memory 205396 kb
Host smart-fd808f16-db1e-4a59-977d-54fb2050783e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549505537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.1549505537
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.466504027
Short name T1289
Test name
Test status
Simulation time 24843588575 ps
CPU time 20.54 seconds
Started Aug 11 05:26:40 PM PDT 24
Finished Aug 11 05:27:01 PM PDT 24
Peak memory 411416 kb
Host smart-0401a90b-53b6-477f-82a4-f27c1f38598e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466504027 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.466504027
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.2316244416
Short name T82
Test name
Test status
Simulation time 2879973787 ps
CPU time 21.58 seconds
Started Aug 11 05:28:57 PM PDT 24
Finished Aug 11 05:29:19 PM PDT 24
Peak memory 213924 kb
Host smart-0f1779f1-15a6-47fe-862a-440c7d1ae06d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316244416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.2316244416
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3011822235
Short name T264
Test name
Test status
Simulation time 322854379 ps
CPU time 1.19 seconds
Started Aug 11 04:56:00 PM PDT 24
Finished Aug 11 04:56:01 PM PDT 24
Peak memory 204456 kb
Host smart-092d6f1e-9e6b-475d-b117-5db78315a0be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011822235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3011822235
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3371231210
Short name T1747
Test name
Test status
Simulation time 17297477 ps
CPU time 0.73 seconds
Started Aug 11 04:56:46 PM PDT 24
Finished Aug 11 04:56:47 PM PDT 24
Peak memory 204328 kb
Host smart-b84c11cb-ea06-4f77-a3a4-03bfdbd01ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371231210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3371231210
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1690665048
Short name T96
Test name
Test status
Simulation time 143019250 ps
CPU time 2.19 seconds
Started Aug 11 04:56:29 PM PDT 24
Finished Aug 11 04:56:31 PM PDT 24
Peak memory 204352 kb
Host smart-60fe577c-4a0e-4f38-a2dc-72c6764cec90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690665048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1690665048
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.3532361175
Short name T269
Test name
Test status
Simulation time 63352881 ps
CPU time 1.2 seconds
Started Aug 11 05:30:51 PM PDT 24
Finished Aug 11 05:30:53 PM PDT 24
Peak memory 213764 kb
Host smart-acf312d9-41d9-47c3-ace9-fe5339589093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532361175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.3532361175
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2125807201
Short name T105
Test name
Test status
Simulation time 558807175 ps
CPU time 5.15 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 04:55:52 PM PDT 24
Peak memory 204380 kb
Host smart-f424fb0f-bf33-4249-b810-73aebfe6cd62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125807201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2125807201
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1970058734
Short name T288
Test name
Test status
Simulation time 6208920475 ps
CPU time 157.37 seconds
Started Aug 11 05:33:09 PM PDT 24
Finished Aug 11 05:35:46 PM PDT 24
Peak memory 702468 kb
Host smart-7db89e83-44ac-45e0-86cb-a9e9be2580aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970058734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1970058734
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3334815493
Short name T241
Test name
Test status
Simulation time 174034695 ps
CPU time 1.32 seconds
Started Aug 11 05:25:22 PM PDT 24
Finished Aug 11 05:25:24 PM PDT 24
Peak memory 205432 kb
Host smart-1b0ec14b-b6b2-48b9-81dd-b3df77f6e176
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334815493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3334815493
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1805299639
Short name T123
Test name
Test status
Simulation time 110569676107 ps
CPU time 1671.48 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:57:12 PM PDT 24
Peak memory 4709712 kb
Host smart-8ea59d9b-ee80-4101-aaef-d6f61dea46ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805299639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1805299639
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.2096928631
Short name T215
Test name
Test status
Simulation time 83875811271 ps
CPU time 223.71 seconds
Started Aug 11 05:26:24 PM PDT 24
Finished Aug 11 05:30:08 PM PDT 24
Peak memory 1477864 kb
Host smart-6aae7ea2-931d-4a89-8b11-d616c0edc661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096928631 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_stress_all.2096928631
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3160804996
Short name T208
Test name
Test status
Simulation time 422309035 ps
CPU time 2.17 seconds
Started Aug 11 04:56:06 PM PDT 24
Finished Aug 11 04:56:08 PM PDT 24
Peak memory 204616 kb
Host smart-a0692f29-ebe6-4fe1-afa6-0d6728fba127
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160804996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3160804996
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/2.i2c_host_perf.3560516092
Short name T1404
Test name
Test status
Simulation time 12215146347 ps
CPU time 950.46 seconds
Started Aug 11 05:25:48 PM PDT 24
Finished Aug 11 05:41:38 PM PDT 24
Peak memory 1527140 kb
Host smart-36ee69d0-7b40-4bda-aa56-df8a644fb560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560516092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3560516092
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.437934982
Short name T1721
Test name
Test status
Simulation time 843837914 ps
CPU time 35.89 seconds
Started Aug 11 05:25:31 PM PDT 24
Finished Aug 11 05:26:07 PM PDT 24
Peak memory 205528 kb
Host smart-29ead420-597a-4398-a425-e3c6cc3e1a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437934982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.437934982
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1170352023
Short name T164
Test name
Test status
Simulation time 328055485 ps
CPU time 1.71 seconds
Started Aug 11 05:27:36 PM PDT 24
Finished Aug 11 05:27:38 PM PDT 24
Peak memory 205884 kb
Host smart-e293225e-47cf-4e02-865f-3dfb8aff9b80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170352023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1170352023
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.2414110916
Short name T528
Test name
Test status
Simulation time 5135531632 ps
CPU time 51.55 seconds
Started Aug 11 05:28:01 PM PDT 24
Finished Aug 11 05:28:53 PM PDT 24
Peak memory 215484 kb
Host smart-0311c06d-a5d6-43f0-b63a-1fd378ccc498
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414110916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.2414110916
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.3083153611
Short name T331
Test name
Test status
Simulation time 69360022 ps
CPU time 1.69 seconds
Started Aug 11 05:28:08 PM PDT 24
Finished Aug 11 05:28:10 PM PDT 24
Peak memory 205600 kb
Host smart-92540c18-20bb-4d9d-8eed-5dfb428050e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083153611 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.3083153611
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_host_override.155972074
Short name T143
Test name
Test status
Simulation time 44613148 ps
CPU time 0.67 seconds
Started Aug 11 05:28:12 PM PDT 24
Finished Aug 11 05:28:13 PM PDT 24
Peak memory 205176 kb
Host smart-2c9e16ce-8b32-4bc6-badd-ef33cca073c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155972074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.155972074
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.28577737
Short name T295
Test name
Test status
Simulation time 446137950 ps
CPU time 1.47 seconds
Started Aug 11 05:28:44 PM PDT 24
Finished Aug 11 05:28:46 PM PDT 24
Peak memory 205668 kb
Host smart-f14df5a1-d569-4c4b-9af8-b53e3b0c3261
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28577737 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_acq.28577737
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.1807321622
Short name T243
Test name
Test status
Simulation time 447869719 ps
CPU time 17.18 seconds
Started Aug 11 05:33:18 PM PDT 24
Finished Aug 11 05:33:35 PM PDT 24
Peak memory 205532 kb
Host smart-7e9fbde0-d007-41ec-b390-673924ba422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807321622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1807321622
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.2241919024
Short name T24
Test name
Test status
Simulation time 395390469 ps
CPU time 1.54 seconds
Started Aug 11 05:31:32 PM PDT 24
Finished Aug 11 05:31:33 PM PDT 24
Peak memory 213728 kb
Host smart-ee765c6e-85a9-419d-861a-98a5e2ff733a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241919024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2241919024
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1049020571
Short name T206
Test name
Test status
Simulation time 82504802 ps
CPU time 1.58 seconds
Started Aug 11 04:56:23 PM PDT 24
Finished Aug 11 04:56:25 PM PDT 24
Peak memory 204440 kb
Host smart-f58d8509-8bd3-4281-90df-01df82ef7d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049020571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1049020571
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.305305205
Short name T1830
Test name
Test status
Simulation time 126720902 ps
CPU time 2.16 seconds
Started Aug 11 04:56:28 PM PDT 24
Finished Aug 11 04:56:30 PM PDT 24
Peak memory 204428 kb
Host smart-a88f988e-defc-49e6-919a-77b2e17de5ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305305205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.305305205
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.4058274340
Short name T932
Test name
Test status
Simulation time 1370125080 ps
CPU time 2.9 seconds
Started Aug 11 05:25:37 PM PDT 24
Finished Aug 11 05:25:40 PM PDT 24
Peak memory 213828 kb
Host smart-a0ae55d3-6cce-4482-92c8-6be2b0a2cad3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058274340 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.4058274340
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.964269217
Short name T1022
Test name
Test status
Simulation time 149064786 ps
CPU time 1.14 seconds
Started Aug 11 05:27:35 PM PDT 24
Finished Aug 11 05:27:36 PM PDT 24
Peak memory 205464 kb
Host smart-7ee146fc-7923-4ecc-9bf4-8cb059e2dc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964269217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.964269217
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1356058111
Short name T23
Test name
Test status
Simulation time 195333247 ps
CPU time 6.97 seconds
Started Aug 11 05:25:47 PM PDT 24
Finished Aug 11 05:25:54 PM PDT 24
Peak memory 219172 kb
Host smart-dd2657e3-35e0-4510-8237-76bca76b05c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356058111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1356058111
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.822438739
Short name T1795
Test name
Test status
Simulation time 107297554 ps
CPU time 1.22 seconds
Started Aug 11 04:55:50 PM PDT 24
Finished Aug 11 04:55:52 PM PDT 24
Peak memory 204372 kb
Host smart-82e11a2a-b2f6-4bde-9ecc-b333e9a59525
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822438739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.822438739
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2796239516
Short name T1743
Test name
Test status
Simulation time 18893583 ps
CPU time 0.72 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 04:55:48 PM PDT 24
Peak memory 204256 kb
Host smart-e1f0dcca-ff6a-40f5-b442-c195572f23a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796239516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2796239516
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1287672942
Short name T1835
Test name
Test status
Simulation time 100201284 ps
CPU time 1.45 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 04:55:48 PM PDT 24
Peak memory 204540 kb
Host smart-278e12c0-65ed-456a-a40a-b1be87c44345
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287672942 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1287672942
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.976160155
Short name T222
Test name
Test status
Simulation time 68791239 ps
CPU time 0.74 seconds
Started Aug 11 04:55:50 PM PDT 24
Finished Aug 11 04:55:50 PM PDT 24
Peak memory 204280 kb
Host smart-6448c1b7-940f-4cc0-bc19-0a38495d2c57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976160155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.976160155
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.2600990384
Short name T1800
Test name
Test status
Simulation time 59261476 ps
CPU time 0.72 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 04:55:48 PM PDT 24
Peak memory 204240 kb
Host smart-29a4150c-47d7-4dff-9f4e-d77e935fa8ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600990384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2600990384
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1439277935
Short name T233
Test name
Test status
Simulation time 59382110 ps
CPU time 0.96 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 04:55:48 PM PDT 24
Peak memory 204340 kb
Host smart-929b5e0e-d681-416d-9733-2dfafc0f9250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439277935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1439277935
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3496610743
Short name T1791
Test name
Test status
Simulation time 42855652 ps
CPU time 1.41 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 04:55:48 PM PDT 24
Peak memory 204492 kb
Host smart-6aea650b-938b-4d1f-b59a-f4c4443daf8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496610743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3496610743
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3924908405
Short name T104
Test name
Test status
Simulation time 223076831 ps
CPU time 1.24 seconds
Started Aug 11 04:55:53 PM PDT 24
Finished Aug 11 04:55:54 PM PDT 24
Peak memory 204424 kb
Host smart-7119173d-d751-4c69-8ca2-3092db2f7b40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924908405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3924908405
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1567973858
Short name T1759
Test name
Test status
Simulation time 5734640519 ps
CPU time 5.51 seconds
Started Aug 11 04:55:55 PM PDT 24
Finished Aug 11 04:56:01 PM PDT 24
Peak memory 204516 kb
Host smart-d666c917-8f69-4336-86ac-62a7573a2398
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567973858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1567973858
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4049673355
Short name T1839
Test name
Test status
Simulation time 27508751 ps
CPU time 0.79 seconds
Started Aug 11 04:55:53 PM PDT 24
Finished Aug 11 04:55:54 PM PDT 24
Peak memory 204228 kb
Host smart-8645b3f6-f60d-4bcf-b6c4-6738c2517a96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049673355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.4049673355
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3277515243
Short name T201
Test name
Test status
Simulation time 101233536 ps
CPU time 1.39 seconds
Started Aug 11 04:55:58 PM PDT 24
Finished Aug 11 04:56:00 PM PDT 24
Peak memory 212868 kb
Host smart-8470a416-e825-4b65-8fc5-4ac84833fbcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277515243 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3277515243
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3043654929
Short name T220
Test name
Test status
Simulation time 40764943 ps
CPU time 0.77 seconds
Started Aug 11 04:55:54 PM PDT 24
Finished Aug 11 04:55:55 PM PDT 24
Peak memory 204368 kb
Host smart-dabc26a8-71a0-4525-98ae-bc5b9256a96c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043654929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3043654929
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.568338559
Short name T1750
Test name
Test status
Simulation time 48178670 ps
CPU time 0.63 seconds
Started Aug 11 04:55:49 PM PDT 24
Finished Aug 11 04:55:50 PM PDT 24
Peak memory 204184 kb
Host smart-924bc669-f80e-46c2-bb65-a3e6c20d39fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568338559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.568338559
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.422555169
Short name T1780
Test name
Test status
Simulation time 34022843 ps
CPU time 0.95 seconds
Started Aug 11 04:55:54 PM PDT 24
Finished Aug 11 04:55:55 PM PDT 24
Peak memory 204344 kb
Host smart-420d1c71-c3cb-49a7-8958-506e1b6c35b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422555169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.422555169
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.592123258
Short name T1829
Test name
Test status
Simulation time 245159274 ps
CPU time 2.59 seconds
Started Aug 11 04:55:46 PM PDT 24
Finished Aug 11 04:55:49 PM PDT 24
Peak memory 204480 kb
Host smart-3f97d735-5c5e-4abe-80e8-a7f1e531c4c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592123258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.592123258
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.494626475
Short name T212
Test name
Test status
Simulation time 465750978 ps
CPU time 2.05 seconds
Started Aug 11 04:55:48 PM PDT 24
Finished Aug 11 04:55:51 PM PDT 24
Peak memory 204492 kb
Host smart-bb7b155c-be3d-4873-bf0b-ea6ff813173d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494626475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.494626475
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4277792970
Short name T216
Test name
Test status
Simulation time 62319745 ps
CPU time 0.83 seconds
Started Aug 11 04:56:28 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 204388 kb
Host smart-fa64ca3f-7ffe-469c-a889-cb24f5143c25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277792970 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.4277792970
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1348229308
Short name T1774
Test name
Test status
Simulation time 101364338 ps
CPU time 0.7 seconds
Started Aug 11 04:56:27 PM PDT 24
Finished Aug 11 04:56:28 PM PDT 24
Peak memory 204300 kb
Host smart-348ea66d-52fd-42a7-a35c-8763dcfb3819
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348229308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1348229308
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.1912761785
Short name T1833
Test name
Test status
Simulation time 33848762 ps
CPU time 0.72 seconds
Started Aug 11 04:56:26 PM PDT 24
Finished Aug 11 04:56:27 PM PDT 24
Peak memory 204208 kb
Host smart-cd6347cd-b881-48f7-a603-acf835d70cf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912761785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1912761785
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1106140677
Short name T1804
Test name
Test status
Simulation time 96025738 ps
CPU time 1.19 seconds
Started Aug 11 04:56:27 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 204492 kb
Host smart-c2a3d5b8-4498-4874-99c5-8ee5fa8b2e61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106140677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.1106140677
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2818480375
Short name T1802
Test name
Test status
Simulation time 105721898 ps
CPU time 1.39 seconds
Started Aug 11 04:56:23 PM PDT 24
Finished Aug 11 04:56:25 PM PDT 24
Peak memory 204560 kb
Host smart-07957ab6-49a8-4c0f-b12d-d64750a1c7ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818480375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2818480375
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3074927872
Short name T1822
Test name
Test status
Simulation time 72309648 ps
CPU time 0.99 seconds
Started Aug 11 04:56:28 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 204388 kb
Host smart-1a02dbef-c6c0-4c15-bd0c-40587c6fbc31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074927872 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3074927872
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1320326900
Short name T223
Test name
Test status
Simulation time 18031837 ps
CPU time 0.67 seconds
Started Aug 11 04:56:33 PM PDT 24
Finished Aug 11 04:56:34 PM PDT 24
Peak memory 204292 kb
Host smart-2a056e5b-568d-48bc-97e8-d72665c1a588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320326900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1320326900
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.979894858
Short name T1827
Test name
Test status
Simulation time 68672478 ps
CPU time 0.66 seconds
Started Aug 11 04:56:26 PM PDT 24
Finished Aug 11 04:56:27 PM PDT 24
Peak memory 204328 kb
Host smart-232be8a9-01a1-4852-93b2-3dd6d82a50dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979894858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.979894858
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3183960029
Short name T1781
Test name
Test status
Simulation time 86860968 ps
CPU time 1.12 seconds
Started Aug 11 04:56:28 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 204388 kb
Host smart-f3d256f5-93db-474a-9129-47b888fcb956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183960029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.3183960029
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2853744593
Short name T1806
Test name
Test status
Simulation time 81995704 ps
CPU time 2.29 seconds
Started Aug 11 04:56:27 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 204444 kb
Host smart-4483179f-4c15-43ef-af17-86f0b7945fae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853744593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2853744593
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4080166911
Short name T210
Test name
Test status
Simulation time 136515983 ps
CPU time 2.37 seconds
Started Aug 11 04:56:30 PM PDT 24
Finished Aug 11 04:56:33 PM PDT 24
Peak memory 204412 kb
Host smart-911d24c5-7258-4d6c-b463-fa2afc5009f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080166911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.4080166911
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.889408607
Short name T202
Test name
Test status
Simulation time 30662150 ps
CPU time 1.44 seconds
Started Aug 11 04:56:33 PM PDT 24
Finished Aug 11 04:56:34 PM PDT 24
Peak memory 212976 kb
Host smart-333e707b-ec91-4bc9-83d9-e3dbed9e3145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889408607 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.889408607
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2053635972
Short name T1843
Test name
Test status
Simulation time 31063020 ps
CPU time 0.71 seconds
Started Aug 11 04:56:28 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 204256 kb
Host smart-01688528-f3eb-4a9a-aed6-a314234f2260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053635972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2053635972
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.4287843471
Short name T228
Test name
Test status
Simulation time 156500257 ps
CPU time 1.12 seconds
Started Aug 11 04:56:27 PM PDT 24
Finished Aug 11 04:56:28 PM PDT 24
Peak memory 204392 kb
Host smart-d70e5720-cb92-4252-a5a1-de8d780797d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287843471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.4287843471
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.892103064
Short name T197
Test name
Test status
Simulation time 72722051 ps
CPU time 1.06 seconds
Started Aug 11 04:56:35 PM PDT 24
Finished Aug 11 04:56:36 PM PDT 24
Peak memory 204436 kb
Host smart-81c958f4-2dd0-4d43-a485-a177dd5d477d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892103064 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.892103064
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2596987112
Short name T226
Test name
Test status
Simulation time 181682114 ps
CPU time 0.8 seconds
Started Aug 11 04:56:28 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 204276 kb
Host smart-f67b3c60-6e93-4ad7-a0d9-0d5353b910b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596987112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2596987112
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1146144539
Short name T1846
Test name
Test status
Simulation time 36758791 ps
CPU time 0.67 seconds
Started Aug 11 04:56:27 PM PDT 24
Finished Aug 11 04:56:27 PM PDT 24
Peak memory 204260 kb
Host smart-f9e54d85-b505-44a0-aa64-ca85ba45206c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146144539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1146144539
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.338677720
Short name T1814
Test name
Test status
Simulation time 36608567 ps
CPU time 0.89 seconds
Started Aug 11 04:56:28 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 204376 kb
Host smart-f142f3bf-4251-4947-961b-0f88f3d74d70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338677720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou
tstanding.338677720
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3901735765
Short name T1838
Test name
Test status
Simulation time 234069075 ps
CPU time 2.66 seconds
Started Aug 11 04:56:28 PM PDT 24
Finished Aug 11 04:56:31 PM PDT 24
Peak memory 204536 kb
Host smart-5d3144b6-ef42-4759-8de3-5b79b8d47188
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901735765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3901735765
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.249230548
Short name T97
Test name
Test status
Simulation time 75934614 ps
CPU time 1.48 seconds
Started Aug 11 04:56:36 PM PDT 24
Finished Aug 11 04:56:37 PM PDT 24
Peak memory 204364 kb
Host smart-be20178b-9cef-4df2-b6f2-8f58d3d8937f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249230548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.249230548
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4074024179
Short name T1811
Test name
Test status
Simulation time 116599084 ps
CPU time 0.8 seconds
Started Aug 11 04:56:26 PM PDT 24
Finished Aug 11 04:56:27 PM PDT 24
Peak memory 204384 kb
Host smart-fc81ae0e-9c7a-46d6-9297-a1a38131238e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074024179 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.4074024179
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1798537601
Short name T1817
Test name
Test status
Simulation time 23253844 ps
CPU time 0.82 seconds
Started Aug 11 04:56:26 PM PDT 24
Finished Aug 11 04:56:27 PM PDT 24
Peak memory 204324 kb
Host smart-6c7c5055-62ea-4860-b346-de9cb417d012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798537601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1798537601
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.2387950633
Short name T127
Test name
Test status
Simulation time 144791310 ps
CPU time 0.68 seconds
Started Aug 11 04:56:30 PM PDT 24
Finished Aug 11 04:56:31 PM PDT 24
Peak memory 204228 kb
Host smart-d34e8eb4-479a-423a-960f-afee1279e324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387950633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2387950633
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2102880978
Short name T229
Test name
Test status
Simulation time 84186021 ps
CPU time 1.12 seconds
Started Aug 11 04:56:36 PM PDT 24
Finished Aug 11 04:56:37 PM PDT 24
Peak memory 204440 kb
Host smart-64912190-1187-4684-83a5-f04a527674e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102880978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2102880978
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3366707033
Short name T1836
Test name
Test status
Simulation time 43611820 ps
CPU time 2.01 seconds
Started Aug 11 04:56:27 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 204508 kb
Host smart-9d6c1167-1752-41dd-82b8-d71f29b10fa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366707033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3366707033
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1811399425
Short name T1767
Test name
Test status
Simulation time 84901706 ps
CPU time 1.51 seconds
Started Aug 11 04:56:35 PM PDT 24
Finished Aug 11 04:56:37 PM PDT 24
Peak memory 204376 kb
Host smart-72e44b23-31df-4f20-bcd2-6f8fe29c38ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811399425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1811399425
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.907797465
Short name T1771
Test name
Test status
Simulation time 26848592 ps
CPU time 1.08 seconds
Started Aug 11 04:56:34 PM PDT 24
Finished Aug 11 04:56:35 PM PDT 24
Peak memory 204524 kb
Host smart-bb805d2e-2d67-458d-be17-b7b650bc9969
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907797465 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.907797465
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.537394955
Short name T1779
Test name
Test status
Simulation time 123491309 ps
CPU time 0.69 seconds
Started Aug 11 04:56:35 PM PDT 24
Finished Aug 11 04:56:36 PM PDT 24
Peak memory 204284 kb
Host smart-63867faa-2e73-4500-84fb-7f32c4f45b15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537394955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.537394955
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2634074690
Short name T1782
Test name
Test status
Simulation time 19667859 ps
CPU time 0.63 seconds
Started Aug 11 04:56:27 PM PDT 24
Finished Aug 11 04:56:28 PM PDT 24
Peak memory 204232 kb
Host smart-a4f81363-7e4c-4383-9547-598a3e286580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634074690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2634074690
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2039672466
Short name T230
Test name
Test status
Simulation time 50965161 ps
CPU time 1.19 seconds
Started Aug 11 04:56:33 PM PDT 24
Finished Aug 11 04:56:34 PM PDT 24
Peak memory 204420 kb
Host smart-3ac11beb-8209-4c9b-b400-a38a209a7dd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039672466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2039672466
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.291267962
Short name T198
Test name
Test status
Simulation time 186614887 ps
CPU time 1.46 seconds
Started Aug 11 04:56:31 PM PDT 24
Finished Aug 11 04:56:32 PM PDT 24
Peak memory 204464 kb
Host smart-979e89c6-efce-4b4a-8f33-4ce2acc15c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291267962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.291267962
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2247833411
Short name T181
Test name
Test status
Simulation time 37207614 ps
CPU time 1.07 seconds
Started Aug 11 04:56:34 PM PDT 24
Finished Aug 11 04:56:35 PM PDT 24
Peak memory 204340 kb
Host smart-20ee5de3-29fe-4d05-862c-46b1e239750f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247833411 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2247833411
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1825754921
Short name T1789
Test name
Test status
Simulation time 18155604 ps
CPU time 0.7 seconds
Started Aug 11 04:56:34 PM PDT 24
Finished Aug 11 04:56:35 PM PDT 24
Peak memory 204264 kb
Host smart-922e3dd1-0b13-4788-b5ad-5ed02bf7c0a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825754921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1825754921
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.4162093142
Short name T1796
Test name
Test status
Simulation time 31676771 ps
CPU time 0.71 seconds
Started Aug 11 04:56:34 PM PDT 24
Finished Aug 11 04:56:35 PM PDT 24
Peak memory 204212 kb
Host smart-ba223977-d2f4-4a02-943e-5a3ea1784ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162093142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.4162093142
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3398100081
Short name T1787
Test name
Test status
Simulation time 326577116 ps
CPU time 1.1 seconds
Started Aug 11 04:56:36 PM PDT 24
Finished Aug 11 04:56:37 PM PDT 24
Peak memory 204420 kb
Host smart-0ec0c2f2-5c40-4d49-9ea5-1e4733232af4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398100081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3398100081
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.870638859
Short name T1813
Test name
Test status
Simulation time 159328880 ps
CPU time 1.83 seconds
Started Aug 11 04:56:34 PM PDT 24
Finished Aug 11 04:56:35 PM PDT 24
Peak memory 204560 kb
Host smart-9537b285-efd5-41ff-8e23-b62dbb5efb8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870638859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.870638859
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3725769278
Short name T207
Test name
Test status
Simulation time 56156378 ps
CPU time 1.46 seconds
Started Aug 11 04:56:35 PM PDT 24
Finished Aug 11 04:56:36 PM PDT 24
Peak memory 204344 kb
Host smart-28dff567-636f-4327-9f84-31f834c4cdf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725769278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3725769278
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1245030462
Short name T1837
Test name
Test status
Simulation time 25225582 ps
CPU time 0.76 seconds
Started Aug 11 04:56:35 PM PDT 24
Finished Aug 11 04:56:35 PM PDT 24
Peak memory 204344 kb
Host smart-270ae034-786c-4d6a-a289-38d2741beaed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245030462 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1245030462
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3332866622
Short name T102
Test name
Test status
Simulation time 62229928 ps
CPU time 0.69 seconds
Started Aug 11 04:56:36 PM PDT 24
Finished Aug 11 04:56:37 PM PDT 24
Peak memory 204308 kb
Host smart-3e301da9-941e-451f-94fb-12008d0bcbd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332866622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3332866622
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1691297240
Short name T1752
Test name
Test status
Simulation time 17286848 ps
CPU time 0.72 seconds
Started Aug 11 04:56:32 PM PDT 24
Finished Aug 11 04:56:33 PM PDT 24
Peak memory 204160 kb
Host smart-2d6b5b07-ea10-4267-8512-363946b3e1d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691297240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1691297240
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.4137150802
Short name T232
Test name
Test status
Simulation time 22394191 ps
CPU time 0.9 seconds
Started Aug 11 04:56:34 PM PDT 24
Finished Aug 11 04:56:36 PM PDT 24
Peak memory 204308 kb
Host smart-11aeba6a-9ffa-48f0-8711-335f1e85aa6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137150802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.4137150802
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3970622502
Short name T1824
Test name
Test status
Simulation time 74579272 ps
CPU time 1.12 seconds
Started Aug 11 04:56:34 PM PDT 24
Finished Aug 11 04:56:35 PM PDT 24
Peak memory 204544 kb
Host smart-1cd344b2-0054-462a-ad34-4110ec008e02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970622502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3970622502
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3688312530
Short name T101
Test name
Test status
Simulation time 333012427 ps
CPU time 2.12 seconds
Started Aug 11 04:56:34 PM PDT 24
Finished Aug 11 04:56:37 PM PDT 24
Peak memory 204352 kb
Host smart-3f0b7431-d608-467c-b4ee-f93cb636f71c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688312530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3688312530
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.18129165
Short name T1766
Test name
Test status
Simulation time 160258998 ps
CPU time 0.78 seconds
Started Aug 11 04:56:33 PM PDT 24
Finished Aug 11 04:56:34 PM PDT 24
Peak memory 204424 kb
Host smart-2fa53c8c-a515-410f-86c0-1003d1904216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18129165 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.18129165
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2231003675
Short name T227
Test name
Test status
Simulation time 47059565 ps
CPU time 0.71 seconds
Started Aug 11 04:56:33 PM PDT 24
Finished Aug 11 04:56:33 PM PDT 24
Peak memory 204344 kb
Host smart-8b9dcb72-4772-4697-a540-c652c56f7d86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231003675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2231003675
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3268926956
Short name T1762
Test name
Test status
Simulation time 176786078 ps
CPU time 0.7 seconds
Started Aug 11 04:56:38 PM PDT 24
Finished Aug 11 04:56:39 PM PDT 24
Peak memory 204192 kb
Host smart-90a23ee9-a4f2-4495-a442-e94446142236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268926956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3268926956
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2825859429
Short name T1758
Test name
Test status
Simulation time 24392987 ps
CPU time 0.88 seconds
Started Aug 11 04:56:33 PM PDT 24
Finished Aug 11 04:56:34 PM PDT 24
Peak memory 204320 kb
Host smart-4c1e5b34-5ff1-43dc-89ea-2387a1b118bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825859429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2825859429
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.156826474
Short name T1777
Test name
Test status
Simulation time 115923966 ps
CPU time 2.47 seconds
Started Aug 11 04:56:33 PM PDT 24
Finished Aug 11 04:56:36 PM PDT 24
Peak memory 204496 kb
Host smart-fbff4a88-2016-4d98-8640-4d5a327dc768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156826474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.156826474
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1931044716
Short name T204
Test name
Test status
Simulation time 481190932 ps
CPU time 2.17 seconds
Started Aug 11 04:56:34 PM PDT 24
Finished Aug 11 04:56:37 PM PDT 24
Peak memory 204556 kb
Host smart-db686edb-2e3c-48eb-9cd6-b147b87594f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931044716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1931044716
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.1359725475
Short name T1832
Test name
Test status
Simulation time 25453220 ps
CPU time 0.84 seconds
Started Aug 11 04:56:39 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 204704 kb
Host smart-5ebde8cb-ed56-4822-8e9f-be99b404584f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359725475 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.1359725475
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.628745147
Short name T224
Test name
Test status
Simulation time 16445531 ps
CPU time 0.72 seconds
Started Aug 11 04:56:39 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 204292 kb
Host smart-92265d56-3e2b-4fb5-8490-1ea840359162
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628745147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.628745147
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1084917199
Short name T283
Test name
Test status
Simulation time 14523976 ps
CPU time 0.73 seconds
Started Aug 11 04:56:41 PM PDT 24
Finished Aug 11 04:56:41 PM PDT 24
Peak memory 204260 kb
Host smart-f8456e47-e903-4900-be90-8e41f4383b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084917199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1084917199
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.289901340
Short name T1794
Test name
Test status
Simulation time 186146134 ps
CPU time 1.13 seconds
Started Aug 11 04:56:39 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 204436 kb
Host smart-d710a0fc-372f-4911-abe1-d8997ed35c7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289901340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.289901340
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1467851879
Short name T1845
Test name
Test status
Simulation time 114026820 ps
CPU time 1.54 seconds
Started Aug 11 04:56:33 PM PDT 24
Finished Aug 11 04:56:35 PM PDT 24
Peak memory 204576 kb
Host smart-98935f1a-f571-4b0c-919b-6c932e8806ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467851879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1467851879
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1263650137
Short name T205
Test name
Test status
Simulation time 52972961 ps
CPU time 1.44 seconds
Started Aug 11 04:56:41 PM PDT 24
Finished Aug 11 04:56:42 PM PDT 24
Peak memory 204372 kb
Host smart-3bd4287b-86b2-4da4-9a2e-2a7ccbcb1dca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263650137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1263650137
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1772004338
Short name T1818
Test name
Test status
Simulation time 96951308 ps
CPU time 2.09 seconds
Started Aug 11 04:55:57 PM PDT 24
Finished Aug 11 04:56:00 PM PDT 24
Peak memory 204380 kb
Host smart-569445a5-3946-4cab-a7ff-9758e12ad2bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772004338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1772004338
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2047908666
Short name T1754
Test name
Test status
Simulation time 1099607039 ps
CPU time 2.99 seconds
Started Aug 11 04:55:57 PM PDT 24
Finished Aug 11 04:56:00 PM PDT 24
Peak memory 204368 kb
Host smart-02079985-8f52-43c6-9836-a2056fe735f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047908666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2047908666
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2721077523
Short name T218
Test name
Test status
Simulation time 316433742 ps
CPU time 0.79 seconds
Started Aug 11 04:55:55 PM PDT 24
Finished Aug 11 04:55:56 PM PDT 24
Peak memory 204324 kb
Host smart-0bc302ba-ec09-44b7-9ee7-61ff5f1ac612
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721077523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2721077523
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2912869269
Short name T1815
Test name
Test status
Simulation time 78676228 ps
CPU time 0.87 seconds
Started Aug 11 04:55:59 PM PDT 24
Finished Aug 11 04:56:00 PM PDT 24
Peak memory 204352 kb
Host smart-f5b178fa-dfd5-4c29-83fb-72c47cbaead6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912869269 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2912869269
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1128223099
Short name T1809
Test name
Test status
Simulation time 56392826 ps
CPU time 0.76 seconds
Started Aug 11 04:55:58 PM PDT 24
Finished Aug 11 04:55:59 PM PDT 24
Peak memory 204304 kb
Host smart-ade5374d-1ab3-4fa0-80cc-4bdca3e708db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128223099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1128223099
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3043398853
Short name T1761
Test name
Test status
Simulation time 47103644 ps
CPU time 0.67 seconds
Started Aug 11 04:55:54 PM PDT 24
Finished Aug 11 04:55:55 PM PDT 24
Peak memory 204208 kb
Host smart-c75f34c4-672b-4965-8389-c0e355a53d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043398853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3043398853
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.296007397
Short name T1842
Test name
Test status
Simulation time 65408681 ps
CPU time 1.23 seconds
Started Aug 11 04:55:53 PM PDT 24
Finished Aug 11 04:55:55 PM PDT 24
Peak memory 204544 kb
Host smart-b174d43e-0511-4968-88c8-d36cf834c581
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296007397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_out
standing.296007397
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.867721655
Short name T1784
Test name
Test status
Simulation time 68587230 ps
CPU time 2.09 seconds
Started Aug 11 04:55:53 PM PDT 24
Finished Aug 11 04:55:55 PM PDT 24
Peak memory 204528 kb
Host smart-9664ede5-d5da-4b3d-b831-203bcf67a979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867721655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.867721655
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3811500010
Short name T1786
Test name
Test status
Simulation time 349192988 ps
CPU time 2.17 seconds
Started Aug 11 04:55:55 PM PDT 24
Finished Aug 11 04:55:57 PM PDT 24
Peak memory 204504 kb
Host smart-fbf9515f-3601-4428-8050-e052c91eb5d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811500010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3811500010
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3883043433
Short name T126
Test name
Test status
Simulation time 139819677 ps
CPU time 0.7 seconds
Started Aug 11 04:56:40 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 204260 kb
Host smart-2c66c551-d708-4f77-9551-dc172f076b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883043433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3883043433
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.4105225717
Short name T1803
Test name
Test status
Simulation time 15494451 ps
CPU time 0.68 seconds
Started Aug 11 04:56:39 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 204208 kb
Host smart-3183b78e-7f73-4fe1-b805-acbb7916c9e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105225717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4105225717
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.284862020
Short name T1834
Test name
Test status
Simulation time 14693489 ps
CPU time 0.68 seconds
Started Aug 11 04:56:43 PM PDT 24
Finished Aug 11 04:56:44 PM PDT 24
Peak memory 204280 kb
Host smart-78265541-c3cb-4894-b789-85542ad2bf5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284862020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.284862020
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2643469226
Short name T1753
Test name
Test status
Simulation time 105256969 ps
CPU time 0.66 seconds
Started Aug 11 04:56:39 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 204212 kb
Host smart-2b833388-2e98-4bcc-8227-4df7e73311c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643469226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2643469226
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.3324746959
Short name T1765
Test name
Test status
Simulation time 37559472 ps
CPU time 0.66 seconds
Started Aug 11 04:56:42 PM PDT 24
Finished Aug 11 04:56:43 PM PDT 24
Peak memory 204280 kb
Host smart-c6be31c7-1b15-4df8-94e7-d705c341d4cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324746959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3324746959
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.968740567
Short name T1808
Test name
Test status
Simulation time 36848545 ps
CPU time 0.7 seconds
Started Aug 11 04:56:43 PM PDT 24
Finished Aug 11 04:56:43 PM PDT 24
Peak memory 204280 kb
Host smart-744afe0e-347a-4b26-8d1d-4a81f0eed76f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968740567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.968740567
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2577651313
Short name T1825
Test name
Test status
Simulation time 17209354 ps
CPU time 0.72 seconds
Started Aug 11 04:56:38 PM PDT 24
Finished Aug 11 04:56:39 PM PDT 24
Peak memory 204144 kb
Host smart-55895141-3f8d-47f9-822b-9b58b30a18dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577651313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2577651313
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.1188942518
Short name T1748
Test name
Test status
Simulation time 51104269 ps
CPU time 0.71 seconds
Started Aug 11 04:56:41 PM PDT 24
Finished Aug 11 04:56:41 PM PDT 24
Peak memory 204260 kb
Host smart-27341896-d6c9-4b70-b562-dde892b8b9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188942518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1188942518
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3647756178
Short name T281
Test name
Test status
Simulation time 32216609 ps
CPU time 0.63 seconds
Started Aug 11 04:56:38 PM PDT 24
Finished Aug 11 04:56:39 PM PDT 24
Peak memory 204300 kb
Host smart-6e2798da-9c4f-48ed-8b9d-8f50d0b969b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647756178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3647756178
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.1232085547
Short name T1770
Test name
Test status
Simulation time 27304806 ps
CPU time 0.64 seconds
Started Aug 11 04:56:39 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 204296 kb
Host smart-a4218ff1-9f5f-4bb7-a7f1-90b09a5ecb39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232085547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1232085547
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3152653215
Short name T221
Test name
Test status
Simulation time 95256653 ps
CPU time 1.99 seconds
Started Aug 11 04:56:02 PM PDT 24
Finished Aug 11 04:56:05 PM PDT 24
Peak memory 204380 kb
Host smart-41b860f7-dbc9-4ad5-8334-dc57c7c418d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152653215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3152653215
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1457772464
Short name T1792
Test name
Test status
Simulation time 698515560 ps
CPU time 5.39 seconds
Started Aug 11 04:56:00 PM PDT 24
Finished Aug 11 04:56:06 PM PDT 24
Peak memory 204412 kb
Host smart-19b50fc9-fafa-4cbd-a3ad-179d268cd49b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457772464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1457772464
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3471358983
Short name T100
Test name
Test status
Simulation time 56036143 ps
CPU time 0.68 seconds
Started Aug 11 04:55:59 PM PDT 24
Finished Aug 11 04:56:00 PM PDT 24
Peak memory 204308 kb
Host smart-6e460fdd-cb98-4467-9d4f-4248fd72d713
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471358983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3471358983
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.233810530
Short name T1775
Test name
Test status
Simulation time 115766392 ps
CPU time 1.06 seconds
Started Aug 11 04:55:59 PM PDT 24
Finished Aug 11 04:56:01 PM PDT 24
Peak memory 204324 kb
Host smart-1a350646-e0b8-4d3c-b619-8cd3657c3f9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233810530 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.233810530
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2714295410
Short name T231
Test name
Test status
Simulation time 50069209 ps
CPU time 0.75 seconds
Started Aug 11 04:56:00 PM PDT 24
Finished Aug 11 04:56:01 PM PDT 24
Peak memory 204256 kb
Host smart-d19ef4fe-785b-4ca1-8c44-7b946d2728cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714295410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2714295410
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.1976844843
Short name T1831
Test name
Test status
Simulation time 22778271 ps
CPU time 0.68 seconds
Started Aug 11 04:55:59 PM PDT 24
Finished Aug 11 04:56:00 PM PDT 24
Peak memory 204560 kb
Host smart-d4c60e62-f402-488e-bc4f-ea79efa2cdf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976844843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1976844843
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1040749076
Short name T200
Test name
Test status
Simulation time 200528361 ps
CPU time 1.1 seconds
Started Aug 11 04:55:55 PM PDT 24
Finished Aug 11 04:55:56 PM PDT 24
Peak memory 204456 kb
Host smart-4513cb82-0494-4e8e-bb43-675ba57b0358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040749076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1040749076
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1612026811
Short name T122
Test name
Test status
Simulation time 1168509698 ps
CPU time 1.54 seconds
Started Aug 11 04:56:00 PM PDT 24
Finished Aug 11 04:56:02 PM PDT 24
Peak memory 204424 kb
Host smart-8a5462aa-e045-4e19-ab0c-35b5a27353d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612026811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1612026811
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3014741590
Short name T1749
Test name
Test status
Simulation time 24415332 ps
CPU time 0.68 seconds
Started Aug 11 04:56:39 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 204216 kb
Host smart-3f077185-324d-4dd7-b981-40780d6e5962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014741590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3014741590
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.877947814
Short name T1793
Test name
Test status
Simulation time 55181635 ps
CPU time 0.71 seconds
Started Aug 11 04:56:42 PM PDT 24
Finished Aug 11 04:56:43 PM PDT 24
Peak memory 204220 kb
Host smart-3cf6932e-9551-407c-88e5-7f9446da81f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877947814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.877947814
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.364833357
Short name T1746
Test name
Test status
Simulation time 37316223 ps
CPU time 0.7 seconds
Started Aug 11 04:56:43 PM PDT 24
Finished Aug 11 04:56:44 PM PDT 24
Peak memory 204216 kb
Host smart-65a83346-99dc-461d-b05c-ffa6e4a29eae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364833357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.364833357
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.3319198217
Short name T1798
Test name
Test status
Simulation time 16498568 ps
CPU time 0.69 seconds
Started Aug 11 04:56:42 PM PDT 24
Finished Aug 11 04:56:43 PM PDT 24
Peak memory 204220 kb
Host smart-829868bd-78c9-4a16-8dd8-6160c3ef92a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319198217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3319198217
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2316613968
Short name T1797
Test name
Test status
Simulation time 33825653 ps
CPU time 0.7 seconds
Started Aug 11 04:56:38 PM PDT 24
Finished Aug 11 04:56:39 PM PDT 24
Peak memory 204248 kb
Host smart-4b1f09d0-7464-40b1-b19a-c34c69f9e293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316613968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2316613968
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.844748847
Short name T286
Test name
Test status
Simulation time 40363712 ps
CPU time 0.68 seconds
Started Aug 11 04:56:39 PM PDT 24
Finished Aug 11 04:56:39 PM PDT 24
Peak memory 204256 kb
Host smart-7afa145b-6e05-4cfc-8ffc-0eebdaf39aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844748847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.844748847
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1651774643
Short name T284
Test name
Test status
Simulation time 50578217 ps
CPU time 0.72 seconds
Started Aug 11 04:56:39 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 204232 kb
Host smart-469c67b6-f442-436f-80df-5a3e5fa191bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651774643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1651774643
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1972403326
Short name T1810
Test name
Test status
Simulation time 20529858 ps
CPU time 0.71 seconds
Started Aug 11 04:56:40 PM PDT 24
Finished Aug 11 04:56:41 PM PDT 24
Peak memory 204372 kb
Host smart-438f2ddf-6f71-4928-b89c-280fbd85b28a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972403326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1972403326
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.4148672401
Short name T1785
Test name
Test status
Simulation time 33926083 ps
CPU time 0.7 seconds
Started Aug 11 04:56:50 PM PDT 24
Finished Aug 11 04:56:51 PM PDT 24
Peak memory 204244 kb
Host smart-80bac331-6df9-488e-8f84-0a2ba080abc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148672401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.4148672401
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1208419351
Short name T1799
Test name
Test status
Simulation time 43302046 ps
CPU time 0.71 seconds
Started Aug 11 04:56:45 PM PDT 24
Finished Aug 11 04:56:46 PM PDT 24
Peak memory 204204 kb
Host smart-a8e9ff87-ab6e-4960-b2db-a98ffce9d586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208419351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1208419351
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1115409103
Short name T1745
Test name
Test status
Simulation time 31577145 ps
CPU time 1.21 seconds
Started Aug 11 04:56:06 PM PDT 24
Finished Aug 11 04:56:08 PM PDT 24
Peak memory 204416 kb
Host smart-dd32ce69-70b6-495c-b38d-c8efe20f4cbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115409103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1115409103
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2337929146
Short name T103
Test name
Test status
Simulation time 269613247 ps
CPU time 2.97 seconds
Started Aug 11 04:56:06 PM PDT 24
Finished Aug 11 04:56:09 PM PDT 24
Peak memory 204408 kb
Host smart-e73a17c5-cda8-4da2-8132-53811bd14491
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337929146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2337929146
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1300873509
Short name T1760
Test name
Test status
Simulation time 29312983 ps
CPU time 0.72 seconds
Started Aug 11 04:56:06 PM PDT 24
Finished Aug 11 04:56:07 PM PDT 24
Peak memory 204352 kb
Host smart-a3c96afa-c47d-4dfb-bea6-ffbe9433424d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300873509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1300873509
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4207714144
Short name T1816
Test name
Test status
Simulation time 214425764 ps
CPU time 0.98 seconds
Started Aug 11 04:56:09 PM PDT 24
Finished Aug 11 04:56:10 PM PDT 24
Peak memory 204320 kb
Host smart-8869bc87-ca66-47c1-919f-661ea2840075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207714144 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.4207714144
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3189400753
Short name T99
Test name
Test status
Simulation time 30009845 ps
CPU time 0.78 seconds
Started Aug 11 04:56:06 PM PDT 24
Finished Aug 11 04:56:07 PM PDT 24
Peak memory 204340 kb
Host smart-7111a46b-af67-4822-b4ac-ea3904aeeae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189400753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3189400753
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1375266548
Short name T1776
Test name
Test status
Simulation time 19640992 ps
CPU time 0.67 seconds
Started Aug 11 04:56:05 PM PDT 24
Finished Aug 11 04:56:06 PM PDT 24
Peak memory 204268 kb
Host smart-161712c7-070d-4efb-aa55-2c97e7f9b8be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375266548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1375266548
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2376197153
Short name T213
Test name
Test status
Simulation time 88817083 ps
CPU time 1.13 seconds
Started Aug 11 04:56:14 PM PDT 24
Finished Aug 11 04:56:15 PM PDT 24
Peak memory 204516 kb
Host smart-0431f4f5-1669-4440-ab60-c3b04943142a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376197153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2376197153
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.971749881
Short name T1828
Test name
Test status
Simulation time 461348909 ps
CPU time 2.69 seconds
Started Aug 11 04:56:14 PM PDT 24
Finished Aug 11 04:56:17 PM PDT 24
Peak memory 204576 kb
Host smart-e5225231-ab82-4045-b831-9915bf9fd2a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971749881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.971749881
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.937039897
Short name T211
Test name
Test status
Simulation time 168336070 ps
CPU time 1.39 seconds
Started Aug 11 04:56:14 PM PDT 24
Finished Aug 11 04:56:16 PM PDT 24
Peak memory 204496 kb
Host smart-7b258f44-9d8f-4160-887b-d62dc70b50c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937039897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.937039897
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.104838126
Short name T1812
Test name
Test status
Simulation time 90498924 ps
CPU time 0.67 seconds
Started Aug 11 04:56:50 PM PDT 24
Finished Aug 11 04:56:51 PM PDT 24
Peak memory 204244 kb
Host smart-37b7ac3c-85a7-4c18-94a1-77c9e3e50f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104838126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.104838126
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.499203015
Short name T287
Test name
Test status
Simulation time 46582182 ps
CPU time 0.68 seconds
Started Aug 11 04:56:47 PM PDT 24
Finished Aug 11 04:56:48 PM PDT 24
Peak memory 204280 kb
Host smart-cf6c34ca-cd67-4f02-84ab-c013c4d41e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499203015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.499203015
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1102541123
Short name T1807
Test name
Test status
Simulation time 34846357 ps
CPU time 0.72 seconds
Started Aug 11 04:56:46 PM PDT 24
Finished Aug 11 04:56:47 PM PDT 24
Peak memory 204328 kb
Host smart-3dffed11-a90d-45ec-aaf9-7ab6285d9b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102541123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1102541123
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3757464443
Short name T1826
Test name
Test status
Simulation time 60690358 ps
CPU time 0.7 seconds
Started Aug 11 04:56:50 PM PDT 24
Finished Aug 11 04:56:51 PM PDT 24
Peak memory 204248 kb
Host smart-66b1ccf1-0b96-453e-8bad-66fa581c4a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757464443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3757464443
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.3918878046
Short name T128
Test name
Test status
Simulation time 39460544 ps
CPU time 0.65 seconds
Started Aug 11 04:56:51 PM PDT 24
Finished Aug 11 04:56:52 PM PDT 24
Peak memory 204236 kb
Host smart-50f6f00d-244d-486a-a155-a7f3d2f2bdad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918878046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3918878046
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2255885950
Short name T1820
Test name
Test status
Simulation time 52729822 ps
CPU time 0.68 seconds
Started Aug 11 04:56:45 PM PDT 24
Finished Aug 11 04:56:46 PM PDT 24
Peak memory 204252 kb
Host smart-7d080543-e3f6-4127-a024-272c89f01238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255885950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2255885950
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3562109921
Short name T1805
Test name
Test status
Simulation time 53316719 ps
CPU time 0.72 seconds
Started Aug 11 04:56:47 PM PDT 24
Finished Aug 11 04:56:48 PM PDT 24
Peak memory 204208 kb
Host smart-a4924ec8-8387-4e52-9f5f-c79281dbd2d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562109921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3562109921
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.853404322
Short name T1769
Test name
Test status
Simulation time 23478337 ps
CPU time 0.68 seconds
Started Aug 11 04:56:45 PM PDT 24
Finished Aug 11 04:56:46 PM PDT 24
Peak memory 204260 kb
Host smart-aa4a10dc-6526-479b-8541-32c7e143f4ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853404322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.853404322
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4025712258
Short name T1756
Test name
Test status
Simulation time 59220132 ps
CPU time 0.82 seconds
Started Aug 11 04:56:13 PM PDT 24
Finished Aug 11 04:56:14 PM PDT 24
Peak memory 204400 kb
Host smart-be33ba2a-472b-4f18-a96a-f398477ac470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025712258 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.4025712258
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.216576167
Short name T1801
Test name
Test status
Simulation time 21423089 ps
CPU time 0.75 seconds
Started Aug 11 04:56:05 PM PDT 24
Finished Aug 11 04:56:06 PM PDT 24
Peak memory 204384 kb
Host smart-e65bc3b7-f2ff-4ca2-a514-bb5cf4b8fa17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216576167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.216576167
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.4249408995
Short name T1751
Test name
Test status
Simulation time 32631954 ps
CPU time 0.67 seconds
Started Aug 11 04:56:06 PM PDT 24
Finished Aug 11 04:56:07 PM PDT 24
Peak memory 204256 kb
Host smart-1229430c-81cd-42ea-9cca-b1e747d7d7c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249408995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.4249408995
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3578519486
Short name T1772
Test name
Test status
Simulation time 47182838 ps
CPU time 1.18 seconds
Started Aug 11 04:56:06 PM PDT 24
Finished Aug 11 04:56:08 PM PDT 24
Peak memory 204384 kb
Host smart-2825dffa-96e7-467b-96a8-c3dc6eae09b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578519486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3578519486
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.4016360709
Short name T1773
Test name
Test status
Simulation time 42339066 ps
CPU time 2.02 seconds
Started Aug 11 04:56:06 PM PDT 24
Finished Aug 11 04:56:09 PM PDT 24
Peak memory 212720 kb
Host smart-e90c3b52-21e5-4e10-a732-8f3977d6e910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016360709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.4016360709
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3717419312
Short name T1757
Test name
Test status
Simulation time 52112665 ps
CPU time 0.88 seconds
Started Aug 11 04:56:12 PM PDT 24
Finished Aug 11 04:56:13 PM PDT 24
Peak memory 204440 kb
Host smart-2508cc2a-93e3-4877-94ed-71bca4c3d2f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717419312 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3717419312
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4198848133
Short name T1823
Test name
Test status
Simulation time 51632009 ps
CPU time 0.77 seconds
Started Aug 11 04:56:13 PM PDT 24
Finished Aug 11 04:56:14 PM PDT 24
Peak memory 204276 kb
Host smart-676991cd-f5b6-4595-82e9-70c188b000cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198848133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.4198848133
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2537465547
Short name T1768
Test name
Test status
Simulation time 25653294 ps
CPU time 0.69 seconds
Started Aug 11 04:56:17 PM PDT 24
Finished Aug 11 04:56:18 PM PDT 24
Peak memory 204296 kb
Host smart-a641691f-859b-45cb-b7ca-cb54224266bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537465547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2537465547
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2694000371
Short name T1764
Test name
Test status
Simulation time 162480306 ps
CPU time 1.1 seconds
Started Aug 11 04:56:17 PM PDT 24
Finished Aug 11 04:56:18 PM PDT 24
Peak memory 204504 kb
Host smart-a2e4579d-4925-4504-b349-51f5c44a7f47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694000371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2694000371
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3775227457
Short name T1790
Test name
Test status
Simulation time 302449019 ps
CPU time 3.03 seconds
Started Aug 11 04:56:12 PM PDT 24
Finished Aug 11 04:56:15 PM PDT 24
Peak memory 204496 kb
Host smart-7142088c-ccae-489f-a978-9732c87b043b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775227457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3775227457
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2383935584
Short name T180
Test name
Test status
Simulation time 322524711 ps
CPU time 2.13 seconds
Started Aug 11 04:56:17 PM PDT 24
Finished Aug 11 04:56:19 PM PDT 24
Peak memory 204512 kb
Host smart-3e121ec3-ff13-47b3-9e86-5e3e35404b28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383935584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2383935584
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3831703655
Short name T1788
Test name
Test status
Simulation time 86441784 ps
CPU time 0.87 seconds
Started Aug 11 04:56:25 PM PDT 24
Finished Aug 11 04:56:26 PM PDT 24
Peak memory 204396 kb
Host smart-4e20d7ca-49b9-4221-bfec-16e6ce7daeb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831703655 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3831703655
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3800891470
Short name T225
Test name
Test status
Simulation time 54317379 ps
CPU time 0.71 seconds
Started Aug 11 04:56:22 PM PDT 24
Finished Aug 11 04:56:23 PM PDT 24
Peak memory 204428 kb
Host smart-5c77a7fa-521f-4d4f-a4af-120a47fcadd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800891470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3800891470
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.3920055804
Short name T1840
Test name
Test status
Simulation time 26602800 ps
CPU time 0.72 seconds
Started Aug 11 04:56:14 PM PDT 24
Finished Aug 11 04:56:15 PM PDT 24
Peak memory 204232 kb
Host smart-408ec283-5074-471f-bc71-60024066a4a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920055804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3920055804
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.434522848
Short name T1844
Test name
Test status
Simulation time 60969256 ps
CPU time 1.37 seconds
Started Aug 11 04:56:17 PM PDT 24
Finished Aug 11 04:56:19 PM PDT 24
Peak memory 204500 kb
Host smart-c97a691d-c1cd-474b-a53b-4b879a12b4b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434522848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.434522848
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1234827062
Short name T209
Test name
Test status
Simulation time 148094778 ps
CPU time 1.44 seconds
Started Aug 11 04:56:11 PM PDT 24
Finished Aug 11 04:56:12 PM PDT 24
Peak memory 204388 kb
Host smart-50163e42-d6e9-495f-b0e6-f2a8244a95c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234827062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1234827062
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3039234846
Short name T1819
Test name
Test status
Simulation time 33502984 ps
CPU time 1.47 seconds
Started Aug 11 04:56:23 PM PDT 24
Finished Aug 11 04:56:24 PM PDT 24
Peak memory 212636 kb
Host smart-203b8e64-7928-4cbc-8341-db5fa123e7c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039234846 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3039234846
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2242095381
Short name T1847
Test name
Test status
Simulation time 43643561 ps
CPU time 0.73 seconds
Started Aug 11 04:56:24 PM PDT 24
Finished Aug 11 04:56:24 PM PDT 24
Peak memory 204288 kb
Host smart-8b1d71db-1a35-4ae6-ae31-28ddada014fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242095381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2242095381
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.2227897477
Short name T1744
Test name
Test status
Simulation time 17825502 ps
CPU time 0.66 seconds
Started Aug 11 04:56:22 PM PDT 24
Finished Aug 11 04:56:23 PM PDT 24
Peak memory 204276 kb
Host smart-ff0cdbad-bccf-4aab-b35c-9c715ff80b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227897477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2227897477
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1046433355
Short name T1821
Test name
Test status
Simulation time 202365519 ps
CPU time 1.24 seconds
Started Aug 11 04:56:23 PM PDT 24
Finished Aug 11 04:56:24 PM PDT 24
Peak memory 204424 kb
Host smart-acc41bd9-2167-4730-9bf4-eab441b7849f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046433355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1046433355
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2575664174
Short name T203
Test name
Test status
Simulation time 156940391 ps
CPU time 1.69 seconds
Started Aug 11 04:56:23 PM PDT 24
Finished Aug 11 04:56:25 PM PDT 24
Peak memory 204816 kb
Host smart-289bd457-be06-4efb-9b77-d60c00b6ad82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575664174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2575664174
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2912709487
Short name T121
Test name
Test status
Simulation time 318802414 ps
CPU time 1.54 seconds
Started Aug 11 04:56:22 PM PDT 24
Finished Aug 11 04:56:24 PM PDT 24
Peak memory 204424 kb
Host smart-2897f790-e966-4ce9-88d7-59d8c26910fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912709487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2912709487
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1744349788
Short name T1783
Test name
Test status
Simulation time 31581590 ps
CPU time 1.41 seconds
Started Aug 11 04:56:22 PM PDT 24
Finished Aug 11 04:56:23 PM PDT 24
Peak memory 204484 kb
Host smart-f621b20e-198a-4cd1-8b90-821d8d28a959
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744349788 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1744349788
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2084381867
Short name T219
Test name
Test status
Simulation time 26038462 ps
CPU time 0.82 seconds
Started Aug 11 04:56:24 PM PDT 24
Finished Aug 11 04:56:25 PM PDT 24
Peak memory 204348 kb
Host smart-1e2ae5af-b7ce-4e58-b32c-48b3e078438d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084381867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2084381867
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3889709501
Short name T1755
Test name
Test status
Simulation time 49119617 ps
CPU time 0.64 seconds
Started Aug 11 04:56:22 PM PDT 24
Finished Aug 11 04:56:22 PM PDT 24
Peak memory 204200 kb
Host smart-e44b95db-383e-4765-9d88-b08a975abe76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889709501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3889709501
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2358085394
Short name T1763
Test name
Test status
Simulation time 31761077 ps
CPU time 0.9 seconds
Started Aug 11 04:56:22 PM PDT 24
Finished Aug 11 04:56:23 PM PDT 24
Peak memory 204320 kb
Host smart-1929a3fc-8fa7-4820-9134-5bf045d57e1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358085394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2358085394
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1485726393
Short name T1778
Test name
Test status
Simulation time 76193379 ps
CPU time 1.97 seconds
Started Aug 11 04:56:24 PM PDT 24
Finished Aug 11 04:56:26 PM PDT 24
Peak memory 204388 kb
Host smart-16553512-a0c9-452c-8aec-bf061d842cc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485726393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1485726393
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.162067269
Short name T1841
Test name
Test status
Simulation time 270096679 ps
CPU time 1.53 seconds
Started Aug 11 04:56:23 PM PDT 24
Finished Aug 11 04:56:24 PM PDT 24
Peak memory 204780 kb
Host smart-05bc1c35-8550-4273-8385-29edfa1d8a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162067269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.162067269
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1538777118
Short name T756
Test name
Test status
Simulation time 29068011 ps
CPU time 0.63 seconds
Started Aug 11 05:25:29 PM PDT 24
Finished Aug 11 05:25:30 PM PDT 24
Peak memory 204712 kb
Host smart-6e72e2c7-4304-4f3d-9983-28825a0d5bef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538777118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1538777118
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2436609878
Short name T1198
Test name
Test status
Simulation time 151378359 ps
CPU time 1.73 seconds
Started Aug 11 05:25:26 PM PDT 24
Finished Aug 11 05:25:28 PM PDT 24
Peak memory 213744 kb
Host smart-8677d8b1-3b5f-47ff-a94d-a612ca12289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436609878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2436609878
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3800694407
Short name T773
Test name
Test status
Simulation time 734842380 ps
CPU time 19.29 seconds
Started Aug 11 05:25:21 PM PDT 24
Finished Aug 11 05:25:41 PM PDT 24
Peak memory 286096 kb
Host smart-44961fa8-53eb-4b97-a7f1-69df14feee93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800694407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3800694407
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.825349140
Short name T390
Test name
Test status
Simulation time 2306953344 ps
CPU time 127.59 seconds
Started Aug 11 05:25:23 PM PDT 24
Finished Aug 11 05:27:31 PM PDT 24
Peak memory 505716 kb
Host smart-f8ede92e-885b-404e-9ec7-b9699accd689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825349140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.825349140
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2715972237
Short name T1654
Test name
Test status
Simulation time 13071128019 ps
CPU time 81.68 seconds
Started Aug 11 05:25:24 PM PDT 24
Finished Aug 11 05:26:45 PM PDT 24
Peak memory 826076 kb
Host smart-b6a5aa2a-24f0-4c28-a696-cd6d98bd527a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715972237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2715972237
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1975065250
Short name T1386
Test name
Test status
Simulation time 369196179 ps
CPU time 4.67 seconds
Started Aug 11 05:25:24 PM PDT 24
Finished Aug 11 05:25:28 PM PDT 24
Peak memory 237664 kb
Host smart-f9aaa346-7f8c-41bd-b0da-83a27fbfae03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975065250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1975065250
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2102738434
Short name T1205
Test name
Test status
Simulation time 77384685430 ps
CPU time 142.3 seconds
Started Aug 11 05:25:23 PM PDT 24
Finished Aug 11 05:27:46 PM PDT 24
Peak memory 1518700 kb
Host smart-ae2e5b93-1571-42d6-a069-4ddd7258af4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102738434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2102738434
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_override.3294724264
Short name T1341
Test name
Test status
Simulation time 22012679 ps
CPU time 0.67 seconds
Started Aug 11 05:25:22 PM PDT 24
Finished Aug 11 05:25:22 PM PDT 24
Peak memory 205196 kb
Host smart-e6add695-0b15-46d7-a619-3dd727b8d134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294724264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3294724264
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.2946850961
Short name T608
Test name
Test status
Simulation time 3326109605 ps
CPU time 17.7 seconds
Started Aug 11 05:25:22 PM PDT 24
Finished Aug 11 05:25:40 PM PDT 24
Peak memory 405708 kb
Host smart-5ee62e74-00c0-40f1-bc79-0bfca9ec9c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946850961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.2946850961
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.3281433994
Short name T1535
Test name
Test status
Simulation time 190823074 ps
CPU time 1.47 seconds
Started Aug 11 05:25:26 PM PDT 24
Finished Aug 11 05:25:28 PM PDT 24
Peak memory 224288 kb
Host smart-5adb90ba-3df8-417f-a4a1-f9853361de89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281433994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.3281433994
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3967648807
Short name T1417
Test name
Test status
Simulation time 1676615149 ps
CPU time 84.95 seconds
Started Aug 11 05:25:22 PM PDT 24
Finished Aug 11 05:26:47 PM PDT 24
Peak memory 406648 kb
Host smart-c1b1bc3b-4ee2-415a-b2eb-6293df19993b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967648807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3967648807
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.917454401
Short name T1419
Test name
Test status
Simulation time 1023474146 ps
CPU time 16.58 seconds
Started Aug 11 05:25:25 PM PDT 24
Finished Aug 11 05:25:42 PM PDT 24
Peak memory 229912 kb
Host smart-5dad79b9-e800-4a2c-aea0-6b28782a9d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917454401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.917454401
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.1291709446
Short name T168
Test name
Test status
Simulation time 169924599 ps
CPU time 1.01 seconds
Started Aug 11 05:25:29 PM PDT 24
Finished Aug 11 05:25:30 PM PDT 24
Peak memory 205644 kb
Host smart-145f953f-7633-48e3-9b09-d92c52114316
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291709446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.1291709446
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3243676765
Short name T165
Test name
Test status
Simulation time 2693827380 ps
CPU time 1.86 seconds
Started Aug 11 05:25:28 PM PDT 24
Finished Aug 11 05:25:30 PM PDT 24
Peak memory 213968 kb
Host smart-1f2653af-c4f4-4f21-baad-a29b9bde8ed7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243676765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3243676765
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.2711260951
Short name T277
Test name
Test status
Simulation time 1925156689 ps
CPU time 2.9 seconds
Started Aug 11 05:25:27 PM PDT 24
Finished Aug 11 05:25:30 PM PDT 24
Peak memory 205472 kb
Host smart-8aca7f84-db5b-41f8-924d-94e1b75ea453
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711260951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.2711260951
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.2862400244
Short name T639
Test name
Test status
Simulation time 579459498 ps
CPU time 1.62 seconds
Started Aug 11 05:25:27 PM PDT 24
Finished Aug 11 05:25:29 PM PDT 24
Peak memory 205400 kb
Host smart-f0519ae6-e28f-4d29-9bb7-74c790fdbd98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862400244 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.2862400244
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.1319383106
Short name T52
Test name
Test status
Simulation time 2288808626 ps
CPU time 11.24 seconds
Started Aug 11 05:25:24 PM PDT 24
Finished Aug 11 05:25:35 PM PDT 24
Peak memory 214264 kb
Host smart-7862b85d-d8ef-4d9d-b2ac-f28d6e472dcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319383106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1319383106
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.330152034
Short name T601
Test name
Test status
Simulation time 698436181 ps
CPU time 4.84 seconds
Started Aug 11 05:25:24 PM PDT 24
Finished Aug 11 05:25:29 PM PDT 24
Peak memory 213888 kb
Host smart-a3d4ccb8-ad5a-44c6-af2f-c061e7a82099
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330152034 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.330152034
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.603337395
Short name T446
Test name
Test status
Simulation time 12449684126 ps
CPU time 213.15 seconds
Started Aug 11 05:25:21 PM PDT 24
Finished Aug 11 05:28:55 PM PDT 24
Peak memory 3020656 kb
Host smart-9484a626-ce23-4ee4-8cb8-630764c754ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603337395 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.603337395
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull.1874612497
Short name T1629
Test name
Test status
Simulation time 2368191101 ps
CPU time 2.97 seconds
Started Aug 11 05:25:34 PM PDT 24
Finished Aug 11 05:25:37 PM PDT 24
Peak memory 213964 kb
Host smart-1f1fa132-67d3-4da7-a482-7f4b40662b5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874612497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_nack_acqfull.1874612497
Directory /workspace/0.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/0.i2c_target_nack_acqfull_addr.3028188368
Short name T460
Test name
Test status
Simulation time 889420919 ps
CPU time 2.38 seconds
Started Aug 11 05:25:31 PM PDT 24
Finished Aug 11 05:25:34 PM PDT 24
Peak memory 205720 kb
Host smart-5b598158-14d1-4793-86a2-b0c820f10b30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028188368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.3028188368
Directory /workspace/0.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/0.i2c_target_nack_txstretch.1777451862
Short name T1233
Test name
Test status
Simulation time 130218726 ps
CPU time 1.37 seconds
Started Aug 11 05:25:29 PM PDT 24
Finished Aug 11 05:25:30 PM PDT 24
Peak memory 222328 kb
Host smart-d4d29c9e-f8dc-4593-ba28-e13bc402856a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777451862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_nack_txstretch.1777451862
Directory /workspace/0.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/0.i2c_target_perf.600108000
Short name T540
Test name
Test status
Simulation time 602326700 ps
CPU time 4.68 seconds
Started Aug 11 05:25:30 PM PDT 24
Finished Aug 11 05:25:35 PM PDT 24
Peak memory 213840 kb
Host smart-b0a35ae1-f1a6-4481-9349-c4d5fab7515f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600108000 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.i2c_target_perf.600108000
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smbus_maxlen.499913519
Short name T861
Test name
Test status
Simulation time 937414128 ps
CPU time 2.26 seconds
Started Aug 11 05:25:27 PM PDT 24
Finished Aug 11 05:25:30 PM PDT 24
Peak memory 205456 kb
Host smart-2d8ba5f9-a8cb-432f-a078-f5f90a42aba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499913519 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_smbus_maxlen.499913519
Directory /workspace/0.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.4105885585
Short name T150
Test name
Test status
Simulation time 838765222 ps
CPU time 7.31 seconds
Started Aug 11 05:25:23 PM PDT 24
Finished Aug 11 05:25:30 PM PDT 24
Peak memory 213832 kb
Host smart-d461443c-a811-4e9c-b4cb-11d5708ead94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105885585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.4105885585
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.850169193
Short name T1452
Test name
Test status
Simulation time 15622782630 ps
CPU time 257.6 seconds
Started Aug 11 05:25:30 PM PDT 24
Finished Aug 11 05:29:48 PM PDT 24
Peak memory 2909424 kb
Host smart-b8df143f-fba5-4da2-bb20-cc8c4e93031f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850169193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_stress_all.850169193
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3573486635
Short name T1185
Test name
Test status
Simulation time 591341395 ps
CPU time 26.53 seconds
Started Aug 11 05:25:24 PM PDT 24
Finished Aug 11 05:25:50 PM PDT 24
Peak memory 213820 kb
Host smart-73c86037-cd06-4f06-9dfa-47630dd754c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573486635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3573486635
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1660531972
Short name T1502
Test name
Test status
Simulation time 10889828548 ps
CPU time 21.96 seconds
Started Aug 11 05:25:22 PM PDT 24
Finished Aug 11 05:25:44 PM PDT 24
Peak memory 205760 kb
Host smart-59f5dbdb-1ad5-4cfb-aa6b-e0410a55b7d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660531972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1660531972
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3886149828
Short name T1313
Test name
Test status
Simulation time 4817291303 ps
CPU time 156.9 seconds
Started Aug 11 05:25:21 PM PDT 24
Finished Aug 11 05:27:58 PM PDT 24
Peak memory 1291908 kb
Host smart-f393d983-9b27-4632-953e-ddcb5a9203d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886149828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3886149828
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.4231130450
Short name T862
Test name
Test status
Simulation time 5019332586 ps
CPU time 6.59 seconds
Started Aug 11 05:25:25 PM PDT 24
Finished Aug 11 05:25:32 PM PDT 24
Peak memory 220468 kb
Host smart-7c552455-20fa-43ed-82d4-ff5bdc8695c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231130450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.4231130450
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.3531239257
Short name T914
Test name
Test status
Simulation time 288453710 ps
CPU time 4.45 seconds
Started Aug 11 05:25:29 PM PDT 24
Finished Aug 11 05:25:34 PM PDT 24
Peak memory 205608 kb
Host smart-a2cbe593-6cce-44cc-b0de-9fa6b29f0200
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531239257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.3531239257
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.3970651410
Short name T696
Test name
Test status
Simulation time 17861548 ps
CPU time 0.67 seconds
Started Aug 11 05:25:42 PM PDT 24
Finished Aug 11 05:25:43 PM PDT 24
Peak memory 204852 kb
Host smart-da641e4d-328d-400e-a4ab-21aec2abfc65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970651410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3970651410
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.387481166
Short name T903
Test name
Test status
Simulation time 1042038351 ps
CPU time 3.39 seconds
Started Aug 11 05:25:34 PM PDT 24
Finished Aug 11 05:25:38 PM PDT 24
Peak memory 230044 kb
Host smart-64850d67-be0d-4dc6-89ac-5260e82875b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387481166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.387481166
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.610363465
Short name T426
Test name
Test status
Simulation time 279427114 ps
CPU time 4.7 seconds
Started Aug 11 05:25:36 PM PDT 24
Finished Aug 11 05:25:41 PM PDT 24
Peak memory 242140 kb
Host smart-0ea50885-06bd-40b6-bcdd-dda59d78ec16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610363465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.610363465
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1641556455
Short name T946
Test name
Test status
Simulation time 8871135302 ps
CPU time 119.41 seconds
Started Aug 11 05:25:34 PM PDT 24
Finished Aug 11 05:27:33 PM PDT 24
Peak memory 213848 kb
Host smart-b9bd69b4-b7ec-488e-b1ab-b91dccea2f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641556455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1641556455
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3604871442
Short name T501
Test name
Test status
Simulation time 14722860937 ps
CPU time 187.25 seconds
Started Aug 11 05:25:30 PM PDT 24
Finished Aug 11 05:28:37 PM PDT 24
Peak memory 707368 kb
Host smart-b7db5a58-6202-46e5-bb67-9d53abc078c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604871442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3604871442
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3914347155
Short name T1581
Test name
Test status
Simulation time 306683732 ps
CPU time 1.04 seconds
Started Aug 11 05:25:35 PM PDT 24
Finished Aug 11 05:25:37 PM PDT 24
Peak memory 205216 kb
Host smart-4d503960-54f1-420d-9eac-f425fd74fd82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914347155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3914347155
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2617033182
Short name T675
Test name
Test status
Simulation time 2053823648 ps
CPU time 3.83 seconds
Started Aug 11 05:25:39 PM PDT 24
Finished Aug 11 05:25:43 PM PDT 24
Peak memory 205500 kb
Host smart-7e5f8e42-e576-49f2-8210-c621f04c583d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617033182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2617033182
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3509264605
Short name T1604
Test name
Test status
Simulation time 17394254922 ps
CPU time 300.01 seconds
Started Aug 11 05:25:30 PM PDT 24
Finished Aug 11 05:30:31 PM PDT 24
Peak memory 1216396 kb
Host smart-7d2db11d-f6a2-4362-8ade-fbf507c9fbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509264605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3509264605
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1941082341
Short name T258
Test name
Test status
Simulation time 679509339 ps
CPU time 20.08 seconds
Started Aug 11 05:25:33 PM PDT 24
Finished Aug 11 05:25:54 PM PDT 24
Peak memory 205380 kb
Host smart-8e892588-b5fb-4e5e-853d-fcf84966c362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941082341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1941082341
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_override.2247235518
Short name T1549
Test name
Test status
Simulation time 19332612 ps
CPU time 0.67 seconds
Started Aug 11 05:25:33 PM PDT 24
Finished Aug 11 05:25:33 PM PDT 24
Peak memory 205204 kb
Host smart-8d64cef2-1e00-4269-9e69-b21dd906539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247235518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2247235518
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1231291062
Short name T154
Test name
Test status
Simulation time 7763738486 ps
CPU time 27.9 seconds
Started Aug 11 05:25:35 PM PDT 24
Finished Aug 11 05:26:03 PM PDT 24
Peak memory 231656 kb
Host smart-a1269b04-87a4-4203-b913-b6289ef6dec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231291062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1231291062
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.4254265069
Short name T234
Test name
Test status
Simulation time 2312489335 ps
CPU time 65.03 seconds
Started Aug 11 05:25:37 PM PDT 24
Finished Aug 11 05:26:42 PM PDT 24
Peak memory 205564 kb
Host smart-649b3b16-eefe-4ab0-afc8-2955a5960f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254265069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.4254265069
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3420149859
Short name T1340
Test name
Test status
Simulation time 4501007577 ps
CPU time 20.76 seconds
Started Aug 11 05:25:27 PM PDT 24
Finished Aug 11 05:25:48 PM PDT 24
Peak memory 286844 kb
Host smart-4a1c0867-9c31-4b52-93ce-1464044944f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420149859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3420149859
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1946206180
Short name T688
Test name
Test status
Simulation time 742737494 ps
CPU time 13.93 seconds
Started Aug 11 05:25:35 PM PDT 24
Finished Aug 11 05:25:49 PM PDT 24
Peak memory 216168 kb
Host smart-a0aab096-bb0f-4c7c-8888-5396fdbc297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946206180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1946206180
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2377267638
Short name T185
Test name
Test status
Simulation time 59710791 ps
CPU time 0.96 seconds
Started Aug 11 05:25:45 PM PDT 24
Finished Aug 11 05:25:46 PM PDT 24
Peak memory 223948 kb
Host smart-75d46e6c-d04f-428a-8b46-91326fccd366
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377267638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2377267638
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.436030127
Short name T841
Test name
Test status
Simulation time 601212039 ps
CPU time 3.52 seconds
Started Aug 11 05:25:34 PM PDT 24
Finished Aug 11 05:25:38 PM PDT 24
Peak memory 217672 kb
Host smart-4aa81a5d-ffec-4b11-8395-01485266640d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436030127 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.436030127
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2687953839
Short name T1713
Test name
Test status
Simulation time 452055817 ps
CPU time 1.12 seconds
Started Aug 11 05:25:35 PM PDT 24
Finished Aug 11 05:25:36 PM PDT 24
Peak memory 205648 kb
Host smart-92f932a1-97bb-4a0b-83c1-8652a2a6e447
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687953839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2687953839
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1288879255
Short name T873
Test name
Test status
Simulation time 165408151 ps
CPU time 1.14 seconds
Started Aug 11 05:25:38 PM PDT 24
Finished Aug 11 05:25:39 PM PDT 24
Peak memory 213528 kb
Host smart-f74cab81-5d10-4f1b-9b7a-0fcd90721e2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288879255 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1288879255
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.505472396
Short name T824
Test name
Test status
Simulation time 957057868 ps
CPU time 2.11 seconds
Started Aug 11 05:25:36 PM PDT 24
Finished Aug 11 05:25:38 PM PDT 24
Peak memory 205548 kb
Host smart-17a29ed5-ace5-492c-80bf-69869538b1ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505472396 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.505472396
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.3670182310
Short name T980
Test name
Test status
Simulation time 171654118 ps
CPU time 1.16 seconds
Started Aug 11 05:25:41 PM PDT 24
Finished Aug 11 05:25:43 PM PDT 24
Peak memory 205336 kb
Host smart-e6c7ba73-6ccf-4a05-a099-30ec8f5d5f35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670182310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.3670182310
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3467139567
Short name T577
Test name
Test status
Simulation time 1789309054 ps
CPU time 9.9 seconds
Started Aug 11 05:25:37 PM PDT 24
Finished Aug 11 05:25:47 PM PDT 24
Peak memory 213852 kb
Host smart-87be4400-eef0-4b6a-9558-297b633a552b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467139567 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3467139567
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3134994969
Short name T1239
Test name
Test status
Simulation time 25078456886 ps
CPU time 39.89 seconds
Started Aug 11 05:25:34 PM PDT 24
Finished Aug 11 05:26:14 PM PDT 24
Peak memory 941216 kb
Host smart-3e3bcfe0-39c8-4be4-8daf-7e7bdedb65a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134994969 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3134994969
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull.2254427678
Short name T1208
Test name
Test status
Simulation time 610052179 ps
CPU time 2.94 seconds
Started Aug 11 05:25:41 PM PDT 24
Finished Aug 11 05:25:45 PM PDT 24
Peak memory 213708 kb
Host smart-bcc193ee-5dc9-4437-acbb-694b7691388c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254427678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_nack_acqfull.2254427678
Directory /workspace/1.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/1.i2c_target_nack_acqfull_addr.1015018344
Short name T1476
Test name
Test status
Simulation time 498911999 ps
CPU time 2.55 seconds
Started Aug 11 05:25:41 PM PDT 24
Finished Aug 11 05:25:44 PM PDT 24
Peak memory 205800 kb
Host smart-7c1f7bc9-5830-4427-90ca-b9589a4a25ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015018344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.1015018344
Directory /workspace/1.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/1.i2c_target_nack_txstretch.4254385771
Short name T1066
Test name
Test status
Simulation time 145133598 ps
CPU time 1.45 seconds
Started Aug 11 05:25:43 PM PDT 24
Finished Aug 11 05:25:44 PM PDT 24
Peak memory 222448 kb
Host smart-5f0bf85f-0916-45d0-89a2-436a8fe8a7a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254385771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_nack_txstretch.4254385771
Directory /workspace/1.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/1.i2c_target_perf.1195034203
Short name T1449
Test name
Test status
Simulation time 816919913 ps
CPU time 6.32 seconds
Started Aug 11 05:25:35 PM PDT 24
Finished Aug 11 05:25:41 PM PDT 24
Peak memory 213804 kb
Host smart-d08d6ce0-a2a8-4216-8382-7a86c0dc4864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195034203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.1195034203
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smbus_maxlen.2356224645
Short name T879
Test name
Test status
Simulation time 2961580952 ps
CPU time 2.44 seconds
Started Aug 11 05:25:42 PM PDT 24
Finished Aug 11 05:25:45 PM PDT 24
Peak memory 205484 kb
Host smart-153f29d3-a2ed-47f7-8d58-2b874d1ba57d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356224645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_smbus_maxlen.2356224645
Directory /workspace/1.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3750816545
Short name T622
Test name
Test status
Simulation time 1087673552 ps
CPU time 32.4 seconds
Started Aug 11 05:25:34 PM PDT 24
Finished Aug 11 05:26:06 PM PDT 24
Peak memory 213912 kb
Host smart-9e7e6fcb-9897-4980-8d72-a180ad66000d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750816545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3750816545
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.1646449660
Short name T1231
Test name
Test status
Simulation time 25074575511 ps
CPU time 38.1 seconds
Started Aug 11 05:25:35 PM PDT 24
Finished Aug 11 05:26:13 PM PDT 24
Peak memory 336472 kb
Host smart-66548220-53fa-4020-ba06-a7c7108f9279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646449660 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.1646449660
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.4017971840
Short name T885
Test name
Test status
Simulation time 6219460707 ps
CPU time 24.93 seconds
Started Aug 11 05:25:36 PM PDT 24
Finished Aug 11 05:26:01 PM PDT 24
Peak memory 237872 kb
Host smart-61a55e72-e109-4854-afd0-5ec49857e876
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017971840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.4017971840
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.1214977900
Short name T1280
Test name
Test status
Simulation time 23402313940 ps
CPU time 5.44 seconds
Started Aug 11 05:25:36 PM PDT 24
Finished Aug 11 05:25:41 PM PDT 24
Peak memory 213940 kb
Host smart-d5baf4d2-1807-47f3-a71d-b6488efa5d63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214977900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.1214977900
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1706763009
Short name T1537
Test name
Test status
Simulation time 1593796519 ps
CPU time 4.27 seconds
Started Aug 11 05:25:38 PM PDT 24
Finished Aug 11 05:25:42 PM PDT 24
Peak memory 213748 kb
Host smart-eebb6fa7-e191-4038-9b19-299b723c368b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706763009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1706763009
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1001413995
Short name T1509
Test name
Test status
Simulation time 1501115962 ps
CPU time 7.29 seconds
Started Aug 11 05:25:36 PM PDT 24
Finished Aug 11 05:25:44 PM PDT 24
Peak memory 217892 kb
Host smart-5fba0775-5c82-4744-9a33-0e06dce0e91d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001413995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1001413995
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.202121260
Short name T748
Test name
Test status
Simulation time 301581268 ps
CPU time 4.51 seconds
Started Aug 11 05:25:41 PM PDT 24
Finished Aug 11 05:25:46 PM PDT 24
Peak memory 213736 kb
Host smart-ffc0dc20-b61a-4fdd-8cec-ea31dbf94c6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202121260 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.202121260
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3673606227
Short name T710
Test name
Test status
Simulation time 20188392 ps
CPU time 0.64 seconds
Started Aug 11 05:27:31 PM PDT 24
Finished Aug 11 05:27:32 PM PDT 24
Peak memory 204724 kb
Host smart-af0267da-de5f-48a1-99e8-bb3569e3c199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673606227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3673606227
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3203173295
Short name T509
Test name
Test status
Simulation time 153102096 ps
CPU time 2.83 seconds
Started Aug 11 05:27:23 PM PDT 24
Finished Aug 11 05:27:26 PM PDT 24
Peak memory 229876 kb
Host smart-c91e4622-87ac-450b-9fdc-ad05cd748473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203173295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3203173295
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1131146101
Short name T656
Test name
Test status
Simulation time 1820012674 ps
CPU time 10.11 seconds
Started Aug 11 05:27:22 PM PDT 24
Finished Aug 11 05:27:32 PM PDT 24
Peak memory 310312 kb
Host smart-379714f1-6804-4c10-a111-9f3772188459
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131146101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1131146101
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1330785194
Short name T1486
Test name
Test status
Simulation time 1995272006 ps
CPU time 116.19 seconds
Started Aug 11 05:27:22 PM PDT 24
Finished Aug 11 05:29:18 PM PDT 24
Peak memory 519760 kb
Host smart-088cc25e-05aa-4326-bcc4-63c50b0cf4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330785194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1330785194
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.3833021670
Short name T1643
Test name
Test status
Simulation time 6178347063 ps
CPU time 188.34 seconds
Started Aug 11 05:27:21 PM PDT 24
Finished Aug 11 05:30:30 PM PDT 24
Peak memory 808452 kb
Host smart-b0ea92a6-1563-4775-bab1-f5bf60c2f184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833021670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3833021670
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.91064899
Short name T239
Test name
Test status
Simulation time 436519389 ps
CPU time 1.16 seconds
Started Aug 11 05:27:23 PM PDT 24
Finished Aug 11 05:27:24 PM PDT 24
Peak memory 205284 kb
Host smart-40e9ef46-89d6-40be-8ba0-e97ef3ca497a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91064899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt
.91064899
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1007317030
Short name T40
Test name
Test status
Simulation time 1210534964 ps
CPU time 9.86 seconds
Started Aug 11 05:27:22 PM PDT 24
Finished Aug 11 05:27:32 PM PDT 24
Peak memory 237396 kb
Host smart-7181c0cd-424b-4439-94c0-4dc4e4fd311a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007317030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1007317030
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.611729475
Short name T112
Test name
Test status
Simulation time 8557876530 ps
CPU time 52.62 seconds
Started Aug 11 05:27:22 PM PDT 24
Finished Aug 11 05:28:15 PM PDT 24
Peak memory 655980 kb
Host smart-d73aef72-33b6-4d3e-92f2-4d857068b111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611729475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.611729475
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.830747945
Short name T254
Test name
Test status
Simulation time 469813782 ps
CPU time 6.97 seconds
Started Aug 11 05:27:30 PM PDT 24
Finished Aug 11 05:27:37 PM PDT 24
Peak memory 205544 kb
Host smart-ecda64de-cb4e-404e-bfb9-705f1694bc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830747945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.830747945
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_override.2897434971
Short name T921
Test name
Test status
Simulation time 39138246 ps
CPU time 0.64 seconds
Started Aug 11 05:27:23 PM PDT 24
Finished Aug 11 05:27:24 PM PDT 24
Peak memory 205468 kb
Host smart-09f6065f-a1f3-4bf5-a155-a188219c2e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897434971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2897434971
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.3626486702
Short name T1455
Test name
Test status
Simulation time 3644243011 ps
CPU time 6.98 seconds
Started Aug 11 05:27:26 PM PDT 24
Finished Aug 11 05:27:33 PM PDT 24
Peak memory 224084 kb
Host smart-846f1008-3d84-4e4a-a671-73e4a2bc0b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626486702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3626486702
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.1126937284
Short name T530
Test name
Test status
Simulation time 2786517852 ps
CPU time 13.79 seconds
Started Aug 11 05:27:23 PM PDT 24
Finished Aug 11 05:27:37 PM PDT 24
Peak memory 317104 kb
Host smart-c0c06bcc-63c1-4d48-86bc-6e23b2f5c1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126937284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.1126937284
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3210325144
Short name T1498
Test name
Test status
Simulation time 1794655321 ps
CPU time 92.48 seconds
Started Aug 11 05:27:22 PM PDT 24
Finished Aug 11 05:28:55 PM PDT 24
Peak memory 401580 kb
Host smart-9e8bd88c-498e-42f1-bd83-d9d5af46e431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210325144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3210325144
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2155834913
Short name T350
Test name
Test status
Simulation time 2542496615 ps
CPU time 28.99 seconds
Started Aug 11 05:27:24 PM PDT 24
Finished Aug 11 05:27:53 PM PDT 24
Peak memory 213864 kb
Host smart-0a9cc229-6151-41f7-b557-8508908d5dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155834913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2155834913
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1836381359
Short name T1587
Test name
Test status
Simulation time 2911896851 ps
CPU time 3.63 seconds
Started Aug 11 05:27:30 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 222032 kb
Host smart-b2da2788-b96c-4a73-b8ff-8f599ca9fb3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836381359 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1836381359
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.765991089
Short name T391
Test name
Test status
Simulation time 1205386050 ps
CPU time 1.35 seconds
Started Aug 11 05:27:31 PM PDT 24
Finished Aug 11 05:27:32 PM PDT 24
Peak memory 213736 kb
Host smart-dee0b1cb-431e-4acb-a268-2a13c7ee00cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765991089 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_acq.765991089
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1764148170
Short name T868
Test name
Test status
Simulation time 210705162 ps
CPU time 1.48 seconds
Started Aug 11 05:27:29 PM PDT 24
Finished Aug 11 05:27:31 PM PDT 24
Peak memory 213620 kb
Host smart-4fb8bbf5-55d0-4dd4-bcd2-98b961fad6d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764148170 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1764148170
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.3453235882
Short name T1443
Test name
Test status
Simulation time 995623766 ps
CPU time 2.53 seconds
Started Aug 11 05:27:31 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 205560 kb
Host smart-d3bf0808-97bd-4a7d-b321-56faad809270
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453235882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.3453235882
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.957740929
Short name T729
Test name
Test status
Simulation time 409921499 ps
CPU time 1.1 seconds
Started Aug 11 05:27:32 PM PDT 24
Finished Aug 11 05:27:33 PM PDT 24
Peak memory 205464 kb
Host smart-172469ee-ab08-40e8-95ed-9bf36b9d2bd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957740929 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.957740929
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1352756212
Short name T645
Test name
Test status
Simulation time 358132020 ps
CPU time 1.43 seconds
Started Aug 11 05:27:30 PM PDT 24
Finished Aug 11 05:27:32 PM PDT 24
Peak memory 205608 kb
Host smart-4875d170-a7c1-439c-bb1e-1f8ec0ee7262
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352756212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1352756212
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2776214264
Short name T874
Test name
Test status
Simulation time 4028213441 ps
CPU time 5.44 seconds
Started Aug 11 05:27:23 PM PDT 24
Finished Aug 11 05:27:28 PM PDT 24
Peak memory 221880 kb
Host smart-3ca4bf07-64ef-4f14-a1cf-1ffbd15b1a4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776214264 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2776214264
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.2643108494
Short name T1439
Test name
Test status
Simulation time 15280499352 ps
CPU time 334.84 seconds
Started Aug 11 05:27:20 PM PDT 24
Finished Aug 11 05:32:55 PM PDT 24
Peak memory 3757496 kb
Host smart-81758809-3d6a-42a3-b9ad-3f11467229b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643108494 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.2643108494
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull.2123742571
Short name T1118
Test name
Test status
Simulation time 451425350 ps
CPU time 2.65 seconds
Started Aug 11 05:27:31 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 213728 kb
Host smart-316b0a2a-b681-4e37-af5e-3b18693cf9fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123742571 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_nack_acqfull.2123742571
Directory /workspace/10.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/10.i2c_target_nack_acqfull_addr.832299758
Short name T614
Test name
Test status
Simulation time 2222683227 ps
CPU time 2.99 seconds
Started Aug 11 05:27:29 PM PDT 24
Finished Aug 11 05:27:32 PM PDT 24
Peak memory 205812 kb
Host smart-85c08af2-dc8c-4f4f-a532-aad3384dc54b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832299758 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.832299758
Directory /workspace/10.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/10.i2c_target_nack_txstretch.397963812
Short name T1652
Test name
Test status
Simulation time 270997538 ps
CPU time 1.39 seconds
Started Aug 11 05:27:31 PM PDT 24
Finished Aug 11 05:27:32 PM PDT 24
Peak memory 222392 kb
Host smart-e2482d16-e5f1-4d23-8120-aecb7b157b1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397963812 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_nack_txstretch.397963812
Directory /workspace/10.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/10.i2c_target_perf.382746714
Short name T1612
Test name
Test status
Simulation time 457113696 ps
CPU time 3.68 seconds
Started Aug 11 05:27:31 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 213904 kb
Host smart-cab760e6-fd26-4d4f-b2b2-ae8bd828c6f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382746714 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.i2c_target_perf.382746714
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smbus_maxlen.2498749463
Short name T1471
Test name
Test status
Simulation time 1623501975 ps
CPU time 2.08 seconds
Started Aug 11 05:27:29 PM PDT 24
Finished Aug 11 05:27:32 PM PDT 24
Peak memory 205368 kb
Host smart-cebb4894-a899-4aed-83ac-2aedd42f3994
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498749463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_smbus_maxlen.2498749463
Directory /workspace/10.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.4153458294
Short name T966
Test name
Test status
Simulation time 929002098 ps
CPU time 14.13 seconds
Started Aug 11 05:27:21 PM PDT 24
Finished Aug 11 05:27:35 PM PDT 24
Peak memory 222032 kb
Host smart-69364c86-a0ba-4bc1-aa28-84ad7cd03be4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153458294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.4153458294
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.2416576448
Short name T1150
Test name
Test status
Simulation time 40867747390 ps
CPU time 1360.74 seconds
Started Aug 11 05:27:28 PM PDT 24
Finished Aug 11 05:50:09 PM PDT 24
Peak memory 6913892 kb
Host smart-ef32cb6f-6e12-4cf2-9d81-c5b25236af65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416576448 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.2416576448
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.1146194659
Short name T1570
Test name
Test status
Simulation time 4240638779 ps
CPU time 8.25 seconds
Started Aug 11 05:27:24 PM PDT 24
Finished Aug 11 05:27:32 PM PDT 24
Peak memory 205820 kb
Host smart-90d87bd3-6c1b-4d53-9dd8-30949abcd96c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146194659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.1146194659
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.219656672
Short name T1068
Test name
Test status
Simulation time 22029022606 ps
CPU time 52.53 seconds
Started Aug 11 05:27:23 PM PDT 24
Finished Aug 11 05:28:15 PM PDT 24
Peak memory 486032 kb
Host smart-cc626176-c79c-4e4b-8405-e8ecd69bdd20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219656672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_wr.219656672
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1113507668
Short name T1525
Test name
Test status
Simulation time 2623617794 ps
CPU time 6.26 seconds
Started Aug 11 05:27:23 PM PDT 24
Finished Aug 11 05:27:29 PM PDT 24
Peak memory 213936 kb
Host smart-b5f448c1-5bee-407f-88d7-0e5a115edce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113507668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1113507668
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3256322084
Short name T1216
Test name
Test status
Simulation time 4697862812 ps
CPU time 6.82 seconds
Started Aug 11 05:27:24 PM PDT 24
Finished Aug 11 05:27:31 PM PDT 24
Peak memory 219696 kb
Host smart-b00de670-05e1-4422-965b-d4369ac24a96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256322084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3256322084
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3561358071
Short name T434
Test name
Test status
Simulation time 27418302 ps
CPU time 0.69 seconds
Started Aug 11 05:27:42 PM PDT 24
Finished Aug 11 05:27:42 PM PDT 24
Peak memory 204752 kb
Host smart-fcaee6ae-26e5-428d-98f6-fd79997533c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561358071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3561358071
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2250986433
Short name T825
Test name
Test status
Simulation time 140062073 ps
CPU time 1.27 seconds
Started Aug 11 05:27:40 PM PDT 24
Finished Aug 11 05:27:42 PM PDT 24
Peak memory 213760 kb
Host smart-3c128664-d44b-4742-be90-6c54f9239575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250986433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2250986433
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.3620898700
Short name T330
Test name
Test status
Simulation time 342302121 ps
CPU time 17.92 seconds
Started Aug 11 05:27:31 PM PDT 24
Finished Aug 11 05:27:49 PM PDT 24
Peak memory 277148 kb
Host smart-8899e6ca-e5ae-4219-ad4c-b5243ed5b4b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620898700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.3620898700
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.2230686616
Short name T22
Test name
Test status
Simulation time 12491305395 ps
CPU time 61.48 seconds
Started Aug 11 05:27:40 PM PDT 24
Finished Aug 11 05:28:41 PM PDT 24
Peak memory 213856 kb
Host smart-76443674-af4c-45ad-8fdc-0267935dd7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230686616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2230686616
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3351461846
Short name T95
Test name
Test status
Simulation time 4787880188 ps
CPU time 84.9 seconds
Started Aug 11 05:27:30 PM PDT 24
Finished Aug 11 05:28:55 PM PDT 24
Peak memory 711908 kb
Host smart-f84fc690-8b7a-4460-8faf-f8e826d26719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351461846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3351461846
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2562888116
Short name T1288
Test name
Test status
Simulation time 572706175 ps
CPU time 1.1 seconds
Started Aug 11 05:27:28 PM PDT 24
Finished Aug 11 05:27:29 PM PDT 24
Peak memory 205244 kb
Host smart-6b962f41-6a51-4ce0-bb0b-40b0279646c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562888116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2562888116
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3130787942
Short name T1596
Test name
Test status
Simulation time 367614323 ps
CPU time 4.66 seconds
Started Aug 11 05:27:32 PM PDT 24
Finished Aug 11 05:27:37 PM PDT 24
Peak memory 205584 kb
Host smart-32d4db50-aec1-4158-9faa-69b856edbe5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130787942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3130787942
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1280346857
Short name T790
Test name
Test status
Simulation time 3147714956 ps
CPU time 77.54 seconds
Started Aug 11 05:27:30 PM PDT 24
Finished Aug 11 05:28:48 PM PDT 24
Peak memory 959676 kb
Host smart-c20505fd-fc46-4569-aab2-8ab19f2337ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280346857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1280346857
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.2096185919
Short name T683
Test name
Test status
Simulation time 469269730 ps
CPU time 19 seconds
Started Aug 11 05:27:40 PM PDT 24
Finished Aug 11 05:27:59 PM PDT 24
Peak memory 205536 kb
Host smart-b6b1149c-9348-4a59-9e23-04d6061c5244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096185919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2096185919
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_override.2891523066
Short name T653
Test name
Test status
Simulation time 50170213 ps
CPU time 0.63 seconds
Started Aug 11 05:27:30 PM PDT 24
Finished Aug 11 05:27:30 PM PDT 24
Peak memory 205200 kb
Host smart-994075c1-1671-499e-ac3b-9d083c14cb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891523066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2891523066
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.773252641
Short name T1468
Test name
Test status
Simulation time 27724893842 ps
CPU time 97.83 seconds
Started Aug 11 05:27:37 PM PDT 24
Finished Aug 11 05:29:15 PM PDT 24
Peak memory 213812 kb
Host smart-a3ce5cd5-51ad-4d9d-a759-0ef53283c818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773252641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.773252641
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.1253136021
Short name T923
Test name
Test status
Simulation time 6038964477 ps
CPU time 52.72 seconds
Started Aug 11 05:27:37 PM PDT 24
Finished Aug 11 05:28:30 PM PDT 24
Peak memory 205564 kb
Host smart-a1037012-014d-4932-aa95-3ef22395f474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253136021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.1253136021
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3851133328
Short name T881
Test name
Test status
Simulation time 12998649931 ps
CPU time 25.24 seconds
Started Aug 11 05:27:30 PM PDT 24
Finished Aug 11 05:27:56 PM PDT 24
Peak memory 321020 kb
Host smart-da26b890-f4d6-4cf7-842e-81af79fd4f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851133328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3851133328
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1109787276
Short name T511
Test name
Test status
Simulation time 1541015490 ps
CPU time 14.71 seconds
Started Aug 11 05:27:37 PM PDT 24
Finished Aug 11 05:27:52 PM PDT 24
Peak memory 221096 kb
Host smart-66a259d1-de99-4944-a520-fec7e586d759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109787276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1109787276
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.628921117
Short name T728
Test name
Test status
Simulation time 1174162468 ps
CPU time 5.47 seconds
Started Aug 11 05:27:36 PM PDT 24
Finished Aug 11 05:27:42 PM PDT 24
Peak memory 213836 kb
Host smart-547096f8-d00f-4516-8ed1-1e61d424a195
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628921117 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.628921117
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2208382069
Short name T1383
Test name
Test status
Simulation time 586223479 ps
CPU time 1.14 seconds
Started Aug 11 05:27:37 PM PDT 24
Finished Aug 11 05:27:38 PM PDT 24
Peak memory 204616 kb
Host smart-a0e452c5-c64b-4c81-be30-2f678a07d68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208382069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2208382069
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.2776627921
Short name T1020
Test name
Test status
Simulation time 2225661190 ps
CPU time 2.24 seconds
Started Aug 11 05:27:37 PM PDT 24
Finished Aug 11 05:27:39 PM PDT 24
Peak memory 205716 kb
Host smart-44b9bd77-d18c-4ca9-911f-bf6efcbfe9eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776627921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.2776627921
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.259092050
Short name T575
Test name
Test status
Simulation time 759771488 ps
CPU time 1.6 seconds
Started Aug 11 05:27:38 PM PDT 24
Finished Aug 11 05:27:40 PM PDT 24
Peak memory 205388 kb
Host smart-83b4a221-67f4-4fe7-911a-14f551474bd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259092050 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.259092050
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.2138408483
Short name T1553
Test name
Test status
Simulation time 424213676 ps
CPU time 1.67 seconds
Started Aug 11 05:27:35 PM PDT 24
Finished Aug 11 05:27:37 PM PDT 24
Peak memory 215868 kb
Host smart-43d82dfd-fb33-40be-95e5-29f1fda836dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138408483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.2138408483
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2676480162
Short name T1101
Test name
Test status
Simulation time 765087033 ps
CPU time 5.38 seconds
Started Aug 11 05:27:39 PM PDT 24
Finished Aug 11 05:27:44 PM PDT 24
Peak memory 213980 kb
Host smart-da411a19-7520-4ff6-9abb-9e87c080d67c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676480162 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2676480162
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.2477184505
Short name T1071
Test name
Test status
Simulation time 23466847309 ps
CPU time 630.6 seconds
Started Aug 11 05:27:35 PM PDT 24
Finished Aug 11 05:38:06 PM PDT 24
Peak memory 5702032 kb
Host smart-44c7b4ef-508e-452d-87b8-9489a13559cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477184505 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.2477184505
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull.883971934
Short name T1591
Test name
Test status
Simulation time 1018872216 ps
CPU time 2.89 seconds
Started Aug 11 05:27:43 PM PDT 24
Finished Aug 11 05:27:46 PM PDT 24
Peak memory 213864 kb
Host smart-8a01523c-e703-4677-8e0e-72ce69fbb9c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883971934 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_nack_acqfull.883971934
Directory /workspace/11.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/11.i2c_target_nack_acqfull_addr.733879680
Short name T1602
Test name
Test status
Simulation time 451636903 ps
CPU time 2.88 seconds
Started Aug 11 05:27:43 PM PDT 24
Finished Aug 11 05:27:46 PM PDT 24
Peak memory 205588 kb
Host smart-1034a86b-ef17-47a6-af63-a919521cd474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733879680 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 11.i2c_target_nack_acqfull_addr.733879680
Directory /workspace/11.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/11.i2c_target_perf.764760769
Short name T1511
Test name
Test status
Simulation time 2236977993 ps
CPU time 3.91 seconds
Started Aug 11 05:27:35 PM PDT 24
Finished Aug 11 05:27:40 PM PDT 24
Peak memory 214136 kb
Host smart-1de57a38-2c61-4286-8562-307d2e35fbc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764760769 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_perf.764760769
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smbus_maxlen.154652042
Short name T1507
Test name
Test status
Simulation time 2463539691 ps
CPU time 1.94 seconds
Started Aug 11 05:27:37 PM PDT 24
Finished Aug 11 05:27:39 PM PDT 24
Peak memory 205576 kb
Host smart-fbe39574-09f3-4702-8c50-ebdf0bddde09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154652042 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_smbus_maxlen.154652042
Directory /workspace/11.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.1980581429
Short name T1206
Test name
Test status
Simulation time 12954226511 ps
CPU time 31.34 seconds
Started Aug 11 05:27:37 PM PDT 24
Finished Aug 11 05:28:09 PM PDT 24
Peak memory 218628 kb
Host smart-4d5ba6bd-ea8c-4b65-96d3-84e5c67f338e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980581429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.1980581429
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.817112748
Short name T1176
Test name
Test status
Simulation time 31004557852 ps
CPU time 166.51 seconds
Started Aug 11 05:27:34 PM PDT 24
Finished Aug 11 05:30:21 PM PDT 24
Peak memory 862528 kb
Host smart-db74523a-becd-465f-8b4f-553cc7a6fecb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817112748 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_target_stress_all.817112748
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1424679815
Short name T1501
Test name
Test status
Simulation time 307232881 ps
CPU time 13.74 seconds
Started Aug 11 05:27:37 PM PDT 24
Finished Aug 11 05:27:51 PM PDT 24
Peak memory 205648 kb
Host smart-16084183-8c9b-4dee-ba89-e4e23cdb9ccb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424679815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1424679815
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.2701560661
Short name T512
Test name
Test status
Simulation time 59186210766 ps
CPU time 192.39 seconds
Started Aug 11 05:27:36 PM PDT 24
Finished Aug 11 05:30:49 PM PDT 24
Peak memory 2048800 kb
Host smart-9ee778fa-6056-4642-a72c-1e58f586fd5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701560661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.2701560661
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.2857753471
Short name T322
Test name
Test status
Simulation time 291134402 ps
CPU time 1.03 seconds
Started Aug 11 05:27:36 PM PDT 24
Finished Aug 11 05:27:38 PM PDT 24
Peak memory 205444 kb
Host smart-e5251458-d630-4531-8b1e-b39fa95b602c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857753471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.2857753471
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.2695313333
Short name T1685
Test name
Test status
Simulation time 6043132482 ps
CPU time 7.63 seconds
Started Aug 11 05:27:37 PM PDT 24
Finished Aug 11 05:27:45 PM PDT 24
Peak memory 213920 kb
Host smart-6d176a25-90d2-43da-8d80-2ad74dc701c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695313333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.2695313333
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.3072063756
Short name T721
Test name
Test status
Simulation time 130096171 ps
CPU time 1.59 seconds
Started Aug 11 05:27:35 PM PDT 24
Finished Aug 11 05:27:37 PM PDT 24
Peak memory 214808 kb
Host smart-ddc1417f-ef6c-4e00-bb26-73512c2edd08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072063756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.3072063756
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.1855181
Short name T638
Test name
Test status
Simulation time 30666770 ps
CPU time 0.67 seconds
Started Aug 11 05:27:54 PM PDT 24
Finished Aug 11 05:27:55 PM PDT 24
Peak memory 204796 kb
Host smart-e9284e07-766d-4f3e-b9b4-15a122db124c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.1855181
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.1758523200
Short name T1499
Test name
Test status
Simulation time 117130962 ps
CPU time 5.17 seconds
Started Aug 11 05:27:42 PM PDT 24
Finished Aug 11 05:27:47 PM PDT 24
Peak memory 227920 kb
Host smart-276156a4-9618-434a-82e4-1c949f056ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758523200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.1758523200
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.4038691489
Short name T303
Test name
Test status
Simulation time 1651441921 ps
CPU time 20.96 seconds
Started Aug 11 05:27:43 PM PDT 24
Finished Aug 11 05:28:04 PM PDT 24
Peak memory 288064 kb
Host smart-4277e1ad-1dd3-47a5-a039-9a109eeef121
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038691489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.4038691489
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2057255226
Short name T1637
Test name
Test status
Simulation time 3950804192 ps
CPU time 175.06 seconds
Started Aug 11 05:27:42 PM PDT 24
Finished Aug 11 05:30:38 PM PDT 24
Peak memory 542972 kb
Host smart-9d06b315-14fa-463f-a808-deed0267d927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057255226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2057255226
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2894552357
Short name T669
Test name
Test status
Simulation time 10172228249 ps
CPU time 76.88 seconds
Started Aug 11 05:27:42 PM PDT 24
Finished Aug 11 05:28:59 PM PDT 24
Peak memory 786680 kb
Host smart-68673784-7d32-4e07-b6f5-9cf8cec73eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894552357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2894552357
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.1704654502
Short name T1251
Test name
Test status
Simulation time 420088041 ps
CPU time 1.2 seconds
Started Aug 11 05:27:43 PM PDT 24
Finished Aug 11 05:27:44 PM PDT 24
Peak memory 205516 kb
Host smart-7dd8cf1e-c170-4f44-a533-deec5f9f0222
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704654502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.1704654502
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1238644240
Short name T810
Test name
Test status
Simulation time 164153338 ps
CPU time 4.18 seconds
Started Aug 11 05:27:41 PM PDT 24
Finished Aug 11 05:27:45 PM PDT 24
Peak memory 230892 kb
Host smart-1e0b7fe4-d759-4b83-8fcc-f59b5a21ce57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238644240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1238644240
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.271391500
Short name T1437
Test name
Test status
Simulation time 11707202748 ps
CPU time 175.74 seconds
Started Aug 11 05:27:44 PM PDT 24
Finished Aug 11 05:30:40 PM PDT 24
Peak memory 842556 kb
Host smart-e4b90754-170c-40cb-9e3a-83b8c01e57c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271391500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.271391500
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.406636227
Short name T1538
Test name
Test status
Simulation time 350906405 ps
CPU time 5.61 seconds
Started Aug 11 05:27:49 PM PDT 24
Finished Aug 11 05:27:54 PM PDT 24
Peak memory 205480 kb
Host smart-96fdde88-1a58-4f3c-ae3b-e785ca2f5882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406636227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.406636227
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.3162121413
Short name T1077
Test name
Test status
Simulation time 86703913 ps
CPU time 1.45 seconds
Started Aug 11 05:27:59 PM PDT 24
Finished Aug 11 05:28:01 PM PDT 24
Peak memory 218544 kb
Host smart-cf771a0a-caee-4b45-b696-4fd79204896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162121413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3162121413
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.1969527238
Short name T1580
Test name
Test status
Simulation time 25254732 ps
CPU time 0.67 seconds
Started Aug 11 05:27:42 PM PDT 24
Finished Aug 11 05:27:43 PM PDT 24
Peak memory 205168 kb
Host smart-262c261e-0730-4e6f-8445-064e97ab4e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969527238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1969527238
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.4117557624
Short name T514
Test name
Test status
Simulation time 3053076128 ps
CPU time 32.42 seconds
Started Aug 11 05:27:41 PM PDT 24
Finished Aug 11 05:28:13 PM PDT 24
Peak memory 205832 kb
Host smart-28ae279c-9578-4370-b5a0-26e39321ae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117557624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.4117557624
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.316792570
Short name T372
Test name
Test status
Simulation time 240901468 ps
CPU time 2.21 seconds
Started Aug 11 05:27:42 PM PDT 24
Finished Aug 11 05:27:44 PM PDT 24
Peak memory 225952 kb
Host smart-dcf9910a-a62a-41f2-9ae8-031b7432b436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316792570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.316792570
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.4233869674
Short name T302
Test name
Test status
Simulation time 8935532890 ps
CPU time 32.45 seconds
Started Aug 11 05:27:43 PM PDT 24
Finished Aug 11 05:28:15 PM PDT 24
Peak memory 359420 kb
Host smart-a5b63860-d52c-48a1-ac6e-a85c76338d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233869674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.4233869674
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3056865438
Short name T416
Test name
Test status
Simulation time 1312186640 ps
CPU time 14.59 seconds
Started Aug 11 05:27:42 PM PDT 24
Finished Aug 11 05:27:57 PM PDT 24
Peak memory 218132 kb
Host smart-1ad30fed-be41-4fc7-9a22-92f5803e186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056865438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3056865438
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1051842839
Short name T1161
Test name
Test status
Simulation time 1300998095 ps
CPU time 4.72 seconds
Started Aug 11 05:27:49 PM PDT 24
Finished Aug 11 05:27:53 PM PDT 24
Peak memory 214020 kb
Host smart-46e78ada-ab8f-4303-a4e3-0b5254ef7131
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051842839 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1051842839
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.549441004
Short name T194
Test name
Test status
Simulation time 307821591 ps
CPU time 1.31 seconds
Started Aug 11 05:27:47 PM PDT 24
Finished Aug 11 05:27:49 PM PDT 24
Peak memory 205612 kb
Host smart-faad191e-ec9f-415b-b341-16e3483edeb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549441004 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.549441004
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.4196207910
Short name T491
Test name
Test status
Simulation time 163372486 ps
CPU time 0.83 seconds
Started Aug 11 05:27:51 PM PDT 24
Finished Aug 11 05:27:52 PM PDT 24
Peak memory 205320 kb
Host smart-3287c6ad-8c9b-4c69-8c34-42666b9d2644
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196207910 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.4196207910
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.1546732168
Short name T1307
Test name
Test status
Simulation time 581676395 ps
CPU time 3.26 seconds
Started Aug 11 05:27:47 PM PDT 24
Finished Aug 11 05:27:50 PM PDT 24
Peak memory 205668 kb
Host smart-f30a1d32-836c-4750-b52c-331d63776459
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546732168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.1546732168
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.3947175092
Short name T1636
Test name
Test status
Simulation time 429064661 ps
CPU time 1.08 seconds
Started Aug 11 05:27:48 PM PDT 24
Finished Aug 11 05:27:49 PM PDT 24
Peak memory 205400 kb
Host smart-94f7bbea-ea4d-47f7-a17b-45605808e654
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947175092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.3947175092
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3657709482
Short name T1430
Test name
Test status
Simulation time 2484706212 ps
CPU time 8.32 seconds
Started Aug 11 05:27:48 PM PDT 24
Finished Aug 11 05:27:56 PM PDT 24
Peak memory 222084 kb
Host smart-2d1e653c-ccd7-486f-814b-93d8431cbcc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657709482 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3657709482
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3259366745
Short name T519
Test name
Test status
Simulation time 10789699246 ps
CPU time 177.75 seconds
Started Aug 11 05:27:51 PM PDT 24
Finished Aug 11 05:30:49 PM PDT 24
Peak memory 2686860 kb
Host smart-600f0359-402a-4a23-9f1c-eeff325bc9c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259366745 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3259366745
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull.3082647394
Short name T459
Test name
Test status
Simulation time 2389714268 ps
CPU time 3.22 seconds
Started Aug 11 05:27:54 PM PDT 24
Finished Aug 11 05:27:57 PM PDT 24
Peak memory 214016 kb
Host smart-550b3696-758a-414a-916c-6a2c34004bfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082647394 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_nack_acqfull.3082647394
Directory /workspace/12.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/12.i2c_target_nack_acqfull_addr.3766361975
Short name T1278
Test name
Test status
Simulation time 960260610 ps
CPU time 2.91 seconds
Started Aug 11 05:27:54 PM PDT 24
Finished Aug 11 05:27:57 PM PDT 24
Peak memory 205572 kb
Host smart-981ca73f-4853-4cc8-992b-7226b391c79a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766361975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.3766361975
Directory /workspace/12.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/12.i2c_target_nack_txstretch.1917759507
Short name T47
Test name
Test status
Simulation time 140509114 ps
CPU time 1.38 seconds
Started Aug 11 05:27:56 PM PDT 24
Finished Aug 11 05:27:58 PM PDT 24
Peak memory 222252 kb
Host smart-10b8a64c-bf7a-42c5-ae77-33927318b3dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917759507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_nack_txstretch.1917759507
Directory /workspace/12.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/12.i2c_target_perf.3516607930
Short name T87
Test name
Test status
Simulation time 867066324 ps
CPU time 6.27 seconds
Started Aug 11 05:27:50 PM PDT 24
Finished Aug 11 05:27:56 PM PDT 24
Peak memory 230232 kb
Host smart-934aad00-f68c-4d44-b3d0-964dd4d9facb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516607930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.3516607930
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smbus_maxlen.3394413346
Short name T813
Test name
Test status
Simulation time 2018644431 ps
CPU time 2.36 seconds
Started Aug 11 05:27:56 PM PDT 24
Finished Aug 11 05:27:58 PM PDT 24
Peak memory 205472 kb
Host smart-dfd951d5-6781-4367-a489-556ecb3167cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394413346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_smbus_maxlen.3394413346
Directory /workspace/12.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.131495453
Short name T463
Test name
Test status
Simulation time 667018171 ps
CPU time 10.73 seconds
Started Aug 11 05:27:41 PM PDT 24
Finished Aug 11 05:27:52 PM PDT 24
Peak memory 213952 kb
Host smart-ad17ba2f-6a9d-4fe9-8214-f12a3241e3dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131495453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.131495453
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.2239693637
Short name T1031
Test name
Test status
Simulation time 50473281445 ps
CPU time 675.65 seconds
Started Aug 11 05:27:48 PM PDT 24
Finished Aug 11 05:39:04 PM PDT 24
Peak memory 3098508 kb
Host smart-8679dd74-0772-435e-9b47-25793a696240
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239693637 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.2239693637
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1754130288
Short name T987
Test name
Test status
Simulation time 5155343494 ps
CPU time 21.06 seconds
Started Aug 11 05:27:47 PM PDT 24
Finished Aug 11 05:28:08 PM PDT 24
Peak memory 230256 kb
Host smart-c9ac2e17-b92a-469a-9f8a-8c560bc33f99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754130288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1754130288
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2086445789
Short name T1688
Test name
Test status
Simulation time 49022978141 ps
CPU time 1219.16 seconds
Started Aug 11 05:27:48 PM PDT 24
Finished Aug 11 05:48:07 PM PDT 24
Peak memory 7488104 kb
Host smart-ff4fb14d-2831-44d3-acbd-0f333589c515
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086445789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2086445789
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.2215069372
Short name T732
Test name
Test status
Simulation time 4787573397 ps
CPU time 7.45 seconds
Started Aug 11 05:27:47 PM PDT 24
Finished Aug 11 05:27:55 PM PDT 24
Peak memory 268648 kb
Host smart-04636c71-b517-4085-9b22-5f817dc2a613
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215069372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.2215069372
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3728731482
Short name T1367
Test name
Test status
Simulation time 2702509374 ps
CPU time 7.41 seconds
Started Aug 11 05:27:47 PM PDT 24
Finished Aug 11 05:27:54 PM PDT 24
Peak memory 222096 kb
Host smart-422a98cd-41dd-488f-94c7-cf3720980458
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728731482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3728731482
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.2376326058
Short name T1416
Test name
Test status
Simulation time 102919089 ps
CPU time 1.52 seconds
Started Aug 11 05:27:49 PM PDT 24
Finished Aug 11 05:27:51 PM PDT 24
Peak memory 205592 kb
Host smart-ad170541-4191-4221-a666-eff438a0d7b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376326058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.2376326058
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3472879710
Short name T856
Test name
Test status
Simulation time 38628356 ps
CPU time 0.64 seconds
Started Aug 11 05:28:04 PM PDT 24
Finished Aug 11 05:28:04 PM PDT 24
Peak memory 204736 kb
Host smart-1dfc08ed-1d69-4e4f-81bb-29b0d449eb75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472879710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3472879710
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.1632131477
Short name T479
Test name
Test status
Simulation time 114531031 ps
CPU time 1.59 seconds
Started Aug 11 05:28:01 PM PDT 24
Finished Aug 11 05:28:03 PM PDT 24
Peak memory 213724 kb
Host smart-fbbf54d2-06af-4a54-aca1-98e0da75b7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632131477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1632131477
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1755127593
Short name T963
Test name
Test status
Simulation time 423538164 ps
CPU time 4.07 seconds
Started Aug 11 05:27:54 PM PDT 24
Finished Aug 11 05:27:58 PM PDT 24
Peak memory 249404 kb
Host smart-027f4248-337e-403b-bb3a-2aa35b507379
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755127593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1755127593
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.3603489724
Short name T452
Test name
Test status
Simulation time 3436223121 ps
CPU time 142.33 seconds
Started Aug 11 05:27:54 PM PDT 24
Finished Aug 11 05:30:16 PM PDT 24
Peak memory 468028 kb
Host smart-d6bc8b31-0f1c-42bb-a483-3fd2b92af9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603489724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.3603489724
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3817031910
Short name T1728
Test name
Test status
Simulation time 18084497448 ps
CPU time 93.87 seconds
Started Aug 11 05:27:53 PM PDT 24
Finished Aug 11 05:29:27 PM PDT 24
Peak memory 837648 kb
Host smart-5ed3d6dd-8729-4f65-b59c-9b0c920a4874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817031910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3817031910
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1026237247
Short name T803
Test name
Test status
Simulation time 122955406 ps
CPU time 1.04 seconds
Started Aug 11 05:27:54 PM PDT 24
Finished Aug 11 05:27:55 PM PDT 24
Peak memory 205260 kb
Host smart-2f872aa0-3454-4711-82f1-84824537d70b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026237247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1026237247
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.4116548960
Short name T925
Test name
Test status
Simulation time 206726977 ps
CPU time 10.49 seconds
Started Aug 11 05:27:53 PM PDT 24
Finished Aug 11 05:28:04 PM PDT 24
Peak memory 205504 kb
Host smart-9e639bd4-8a21-4938-9116-1f50160847ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116548960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.4116548960
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3706421291
Short name T1059
Test name
Test status
Simulation time 5539858830 ps
CPU time 177.58 seconds
Started Aug 11 05:27:56 PM PDT 24
Finished Aug 11 05:30:53 PM PDT 24
Peak memory 1546984 kb
Host smart-3269f100-d4e2-4654-ae48-cbec8057e9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706421291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3706421291
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.838139078
Short name T1738
Test name
Test status
Simulation time 2619521379 ps
CPU time 6.83 seconds
Started Aug 11 05:27:59 PM PDT 24
Finished Aug 11 05:28:05 PM PDT 24
Peak memory 204596 kb
Host smart-1f6ec79a-ae79-4c2a-b969-8aeb6bb5dbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838139078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.838139078
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_override.2318438373
Short name T1010
Test name
Test status
Simulation time 47308414 ps
CPU time 0.69 seconds
Started Aug 11 05:27:54 PM PDT 24
Finished Aug 11 05:27:55 PM PDT 24
Peak memory 205200 kb
Host smart-4c0871a0-99f6-4140-aa46-48bd1269d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318438373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2318438373
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1101151519
Short name T1094
Test name
Test status
Simulation time 27085455101 ps
CPU time 63.44 seconds
Started Aug 11 05:27:54 PM PDT 24
Finished Aug 11 05:28:57 PM PDT 24
Peak memory 213776 kb
Host smart-cf75372a-bd6e-4173-a115-6f0307a718d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101151519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1101151519
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.1828682133
Short name T1624
Test name
Test status
Simulation time 392565046 ps
CPU time 4.7 seconds
Started Aug 11 05:27:56 PM PDT 24
Finished Aug 11 05:28:01 PM PDT 24
Peak memory 221808 kb
Host smart-0241d083-4596-477c-9703-d30372e7d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828682133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.1828682133
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3071275120
Short name T1550
Test name
Test status
Simulation time 1984337415 ps
CPU time 92.02 seconds
Started Aug 11 05:27:54 PM PDT 24
Finished Aug 11 05:29:26 PM PDT 24
Peak memory 439812 kb
Host smart-2e612d95-fb05-4552-9312-ca9d21c79649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071275120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3071275120
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.524650750
Short name T1170
Test name
Test status
Simulation time 39435470304 ps
CPU time 2991.5 seconds
Started Aug 11 05:28:01 PM PDT 24
Finished Aug 11 06:17:53 PM PDT 24
Peak memory 5382136 kb
Host smart-f8ab0da4-a963-4a52-a7b9-8da86f530d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524650750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.524650750
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3702556361
Short name T373
Test name
Test status
Simulation time 2189238270 ps
CPU time 9.4 seconds
Started Aug 11 05:27:54 PM PDT 24
Finished Aug 11 05:28:04 PM PDT 24
Peak memory 213796 kb
Host smart-a18da1e1-17a3-48e8-a994-0833f55cecee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702556361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3702556361
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3731703299
Short name T1320
Test name
Test status
Simulation time 464128660 ps
CPU time 2.74 seconds
Started Aug 11 05:28:00 PM PDT 24
Finished Aug 11 05:28:03 PM PDT 24
Peak memory 222000 kb
Host smart-b35206ed-5e57-4b75-a317-1d2589abdc74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731703299 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3731703299
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.683302929
Short name T80
Test name
Test status
Simulation time 505473136 ps
CPU time 1.13 seconds
Started Aug 11 05:28:01 PM PDT 24
Finished Aug 11 05:28:03 PM PDT 24
Peak memory 205384 kb
Host smart-16596d22-676b-4bc8-b6d6-bb9c2beed2b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683302929 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.683302929
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1790936356
Short name T118
Test name
Test status
Simulation time 2975680476 ps
CPU time 1.31 seconds
Started Aug 11 05:28:01 PM PDT 24
Finished Aug 11 05:28:02 PM PDT 24
Peak memory 205880 kb
Host smart-61b2fc75-6370-4fad-a964-bf711066ac19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790936356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1790936356
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.2225109344
Short name T1617
Test name
Test status
Simulation time 318452434 ps
CPU time 2.06 seconds
Started Aug 11 05:28:00 PM PDT 24
Finished Aug 11 05:28:02 PM PDT 24
Peak memory 205636 kb
Host smart-7e54f48e-4096-4ca3-90f7-8f3a69fab62b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225109344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.2225109344
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.801982848
Short name T1642
Test name
Test status
Simulation time 582049824 ps
CPU time 1.39 seconds
Started Aug 11 05:28:01 PM PDT 24
Finished Aug 11 05:28:02 PM PDT 24
Peak memory 205456 kb
Host smart-c46cb408-f0b1-4e3c-9eac-ad20f9553b3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801982848 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.801982848
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.846024287
Short name T461
Test name
Test status
Simulation time 4902455755 ps
CPU time 6.69 seconds
Started Aug 11 05:28:02 PM PDT 24
Finished Aug 11 05:28:09 PM PDT 24
Peak memory 213976 kb
Host smart-414e74a0-27c9-4910-9626-24807a85a119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846024287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.846024287
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.1173045458
Short name T173
Test name
Test status
Simulation time 12468530270 ps
CPU time 78.66 seconds
Started Aug 11 05:28:00 PM PDT 24
Finished Aug 11 05:29:19 PM PDT 24
Peak memory 1405128 kb
Host smart-192b823f-3304-428c-9a81-c1febabb2821
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173045458 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1173045458
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull.3306051787
Short name T913
Test name
Test status
Simulation time 6366594528 ps
CPU time 2.77 seconds
Started Aug 11 05:28:07 PM PDT 24
Finished Aug 11 05:28:10 PM PDT 24
Peak memory 213828 kb
Host smart-5a5198f3-d72a-4b71-b678-3ae8534f7a0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306051787 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_nack_acqfull.3306051787
Directory /workspace/13.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/13.i2c_target_nack_acqfull_addr.3516685926
Short name T161
Test name
Test status
Simulation time 1055179582 ps
CPU time 2.44 seconds
Started Aug 11 05:28:12 PM PDT 24
Finished Aug 11 05:28:14 PM PDT 24
Peak memory 205632 kb
Host smart-8554d63d-5f19-496c-b725-b5a13d5b1492
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516685926 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_target_nack_acqfull_addr.3516685926
Directory /workspace/13.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/13.i2c_target_perf.4280196329
Short name T1544
Test name
Test status
Simulation time 1034171041 ps
CPU time 4.63 seconds
Started Aug 11 05:28:01 PM PDT 24
Finished Aug 11 05:28:06 PM PDT 24
Peak memory 221964 kb
Host smart-c50e8929-ba7a-4f8a-a7ec-2561c533f7a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280196329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.4280196329
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smbus_maxlen.2611099737
Short name T905
Test name
Test status
Simulation time 981373228 ps
CPU time 2.33 seconds
Started Aug 11 05:28:06 PM PDT 24
Finished Aug 11 05:28:08 PM PDT 24
Peak memory 205364 kb
Host smart-48843200-e491-4029-9ba8-1815d4a14f7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611099737 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_smbus_maxlen.2611099737
Directory /workspace/13.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2041320146
Short name T271
Test name
Test status
Simulation time 1666726194 ps
CPU time 7.75 seconds
Started Aug 11 05:27:59 PM PDT 24
Finished Aug 11 05:28:07 PM PDT 24
Peak memory 214196 kb
Host smart-f5f2b34d-4577-4881-8729-6f1f9aaa9197
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041320146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2041320146
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.851451243
Short name T290
Test name
Test status
Simulation time 14769675989 ps
CPU time 64.83 seconds
Started Aug 11 05:28:00 PM PDT 24
Finished Aug 11 05:29:05 PM PDT 24
Peak memory 321948 kb
Host smart-9cfb4b69-56ad-42eb-8053-a86ee63d1789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851451243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.i2c_target_stress_all.851451243
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2126097417
Short name T1047
Test name
Test status
Simulation time 67871345525 ps
CPU time 339.34 seconds
Started Aug 11 05:28:00 PM PDT 24
Finished Aug 11 05:33:40 PM PDT 24
Peak memory 2938196 kb
Host smart-57cc70fa-ffce-400e-a742-bb386a1133f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126097417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2126097417
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.134815907
Short name T1105
Test name
Test status
Simulation time 1267003650 ps
CPU time 7.1 seconds
Started Aug 11 05:28:01 PM PDT 24
Finished Aug 11 05:28:09 PM PDT 24
Peak memory 230260 kb
Host smart-e0fc251e-d3ca-465d-a079-1d9ea5c69d17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134815907 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.134815907
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.4096187615
Short name T1394
Test name
Test status
Simulation time 18221160 ps
CPU time 0.63 seconds
Started Aug 11 05:28:13 PM PDT 24
Finished Aug 11 05:28:14 PM PDT 24
Peak memory 204908 kb
Host smart-5233003c-b61c-47f7-92ad-04905f0397ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096187615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.4096187615
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.970069222
Short name T193
Test name
Test status
Simulation time 880337198 ps
CPU time 3.76 seconds
Started Aug 11 05:28:08 PM PDT 24
Finished Aug 11 05:28:11 PM PDT 24
Peak memory 213752 kb
Host smart-22fd69f1-43b5-443c-84ac-83d81dd1a1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970069222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.970069222
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3770189570
Short name T421
Test name
Test status
Simulation time 633420788 ps
CPU time 7.32 seconds
Started Aug 11 05:28:05 PM PDT 24
Finished Aug 11 05:28:13 PM PDT 24
Peak memory 270284 kb
Host smart-f01e5a62-230a-4bd5-a372-e4a5337e4c31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770189570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.3770189570
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3273953933
Short name T155
Test name
Test status
Simulation time 8107488456 ps
CPU time 55.19 seconds
Started Aug 11 05:28:08 PM PDT 24
Finished Aug 11 05:29:03 PM PDT 24
Peak memory 294864 kb
Host smart-e805f4a6-974e-401d-a69d-2a69891483ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273953933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3273953933
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.2294458144
Short name T1380
Test name
Test status
Simulation time 2163530054 ps
CPU time 155.01 seconds
Started Aug 11 05:28:08 PM PDT 24
Finished Aug 11 05:30:43 PM PDT 24
Peak memory 720472 kb
Host smart-04e95a66-ce7d-409c-a423-134ca2f21f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294458144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.2294458144
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2837229630
Short name T31
Test name
Test status
Simulation time 562752697 ps
CPU time 1.12 seconds
Started Aug 11 05:28:04 PM PDT 24
Finished Aug 11 05:28:05 PM PDT 24
Peak memory 205512 kb
Host smart-2101fe1b-8453-4671-9705-c915a2fc0c62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837229630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2837229630
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.551647573
Short name T1202
Test name
Test status
Simulation time 163423910 ps
CPU time 9.78 seconds
Started Aug 11 05:28:04 PM PDT 24
Finished Aug 11 05:28:14 PM PDT 24
Peak memory 236520 kb
Host smart-33ba36a0-8e92-4ca7-8d3d-6dd34cdd5749
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551647573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.
551647573
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1412655487
Short name T1110
Test name
Test status
Simulation time 2807986030 ps
CPU time 50.42 seconds
Started Aug 11 05:28:07 PM PDT 24
Finished Aug 11 05:28:58 PM PDT 24
Peak memory 713948 kb
Host smart-d5626524-451b-4ff6-9afb-e66955899827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412655487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1412655487
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.1397147468
Short name T246
Test name
Test status
Simulation time 664562282 ps
CPU time 10.32 seconds
Started Aug 11 05:28:14 PM PDT 24
Finished Aug 11 05:28:25 PM PDT 24
Peak memory 205508 kb
Host smart-b3f16fe4-e2a4-4a2b-b7f7-77519caabd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397147468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.1397147468
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.4270330813
Short name T12
Test name
Test status
Simulation time 334932772 ps
CPU time 2.49 seconds
Started Aug 11 05:28:17 PM PDT 24
Finished Aug 11 05:28:20 PM PDT 24
Peak memory 213700 kb
Host smart-8b6d40ed-b08a-4d16-818f-fe584e0975ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270330813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.4270330813
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.186044392
Short name T1343
Test name
Test status
Simulation time 18555282 ps
CPU time 0.66 seconds
Started Aug 11 05:28:07 PM PDT 24
Finished Aug 11 05:28:08 PM PDT 24
Peak memory 205280 kb
Host smart-dfab19e8-4be1-46ff-b471-d782a82af46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186044392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.186044392
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1528376424
Short name T1189
Test name
Test status
Simulation time 2965305897 ps
CPU time 170.55 seconds
Started Aug 11 05:28:08 PM PDT 24
Finished Aug 11 05:30:59 PM PDT 24
Peak memory 790728 kb
Host smart-6678eea4-b6f7-40d8-ba04-42f0f541614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528376424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1528376424
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.1141597995
Short name T15
Test name
Test status
Simulation time 5898312703 ps
CPU time 495.19 seconds
Started Aug 11 05:28:11 PM PDT 24
Finished Aug 11 05:36:26 PM PDT 24
Peak memory 1545016 kb
Host smart-f75bbbea-bf0a-4da4-b442-60f4134a4ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141597995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.1141597995
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3477450677
Short name T893
Test name
Test status
Simulation time 6620573499 ps
CPU time 33.47 seconds
Started Aug 11 05:28:08 PM PDT 24
Finished Aug 11 05:28:41 PM PDT 24
Peak memory 420880 kb
Host smart-77f38abf-e0c5-4c90-b08a-6d7cb7c2771f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477450677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3477450677
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2706763380
Short name T2
Test name
Test status
Simulation time 2704831134 ps
CPU time 30.75 seconds
Started Aug 11 05:28:05 PM PDT 24
Finished Aug 11 05:28:35 PM PDT 24
Peak memory 213748 kb
Host smart-e9db4c3d-2b48-4f92-877a-989ea01987cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706763380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2706763380
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.983282989
Short name T1407
Test name
Test status
Simulation time 1055167422 ps
CPU time 6.04 seconds
Started Aug 11 05:28:11 PM PDT 24
Finished Aug 11 05:28:17 PM PDT 24
Peak memory 213720 kb
Host smart-b4457fb1-49f1-48bd-a0d0-5ea567864441
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983282989 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.983282989
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2410515473
Short name T1458
Test name
Test status
Simulation time 188473241 ps
CPU time 1.3 seconds
Started Aug 11 05:28:07 PM PDT 24
Finished Aug 11 05:28:08 PM PDT 24
Peak memory 205888 kb
Host smart-55c8f58e-39d8-4a98-870d-1ee9bbd19a4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410515473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2410515473
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.304711327
Short name T940
Test name
Test status
Simulation time 251396204 ps
CPU time 1.58 seconds
Started Aug 11 05:28:14 PM PDT 24
Finished Aug 11 05:28:15 PM PDT 24
Peak memory 205608 kb
Host smart-b8421c84-fe18-4025-a7a1-a108e27ac505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304711327 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_tx.304711327
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.1346841048
Short name T802
Test name
Test status
Simulation time 3910414955 ps
CPU time 2.81 seconds
Started Aug 11 05:28:13 PM PDT 24
Finished Aug 11 05:28:16 PM PDT 24
Peak memory 213836 kb
Host smart-13d0e586-2199-4027-a8bf-14e190cc1095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346841048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.1346841048
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.3918514633
Short name T686
Test name
Test status
Simulation time 215688092 ps
CPU time 1.12 seconds
Started Aug 11 05:28:11 PM PDT 24
Finished Aug 11 05:28:12 PM PDT 24
Peak memory 205468 kb
Host smart-df213e7f-5f9b-4e5f-b05c-417db0e1c6b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918514633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.3918514633
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.739828235
Short name T1013
Test name
Test status
Simulation time 858724766 ps
CPU time 5.16 seconds
Started Aug 11 05:28:07 PM PDT 24
Finished Aug 11 05:28:13 PM PDT 24
Peak memory 221984 kb
Host smart-61a79e7d-44ab-42d6-97cc-7449d7661d93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739828235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.739828235
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2134069809
Short name T305
Test name
Test status
Simulation time 3926832787 ps
CPU time 1.81 seconds
Started Aug 11 05:28:07 PM PDT 24
Finished Aug 11 05:28:09 PM PDT 24
Peak memory 205688 kb
Host smart-2c7eeff6-4632-457e-b569-67b853dac671
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134069809 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2134069809
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull.1777775846
Short name T1572
Test name
Test status
Simulation time 563022055 ps
CPU time 2.98 seconds
Started Aug 11 05:28:14 PM PDT 24
Finished Aug 11 05:28:17 PM PDT 24
Peak memory 214056 kb
Host smart-ec52772a-466c-40d2-a36c-1d82b4bd95ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777775846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_nack_acqfull.1777775846
Directory /workspace/14.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/14.i2c_target_nack_acqfull_addr.3908011157
Short name T578
Test name
Test status
Simulation time 517989181 ps
CPU time 2.62 seconds
Started Aug 11 05:28:12 PM PDT 24
Finished Aug 11 05:28:15 PM PDT 24
Peak memory 206180 kb
Host smart-674865be-026a-4187-a3f6-ffc3fa61407d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908011157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_nack_acqfull_addr.3908011157
Directory /workspace/14.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/14.i2c_target_nack_txstretch.765464029
Short name T652
Test name
Test status
Simulation time 164479599 ps
CPU time 1.55 seconds
Started Aug 11 05:28:14 PM PDT 24
Finished Aug 11 05:28:15 PM PDT 24
Peak memory 222244 kb
Host smart-77acc7a8-74cc-48bc-a689-c07db97b6418
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765464029 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_nack_txstretch.765464029
Directory /workspace/14.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/14.i2c_target_perf.3169061203
Short name T1360
Test name
Test status
Simulation time 3283563848 ps
CPU time 3.86 seconds
Started Aug 11 05:28:13 PM PDT 24
Finished Aug 11 05:28:17 PM PDT 24
Peak memory 221388 kb
Host smart-b8a2e4ff-8e76-49bb-bbeb-a01ce652e042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169061203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.3169061203
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smbus_maxlen.1079945991
Short name T937
Test name
Test status
Simulation time 2430247234 ps
CPU time 2.35 seconds
Started Aug 11 05:28:14 PM PDT 24
Finished Aug 11 05:28:17 PM PDT 24
Peak memory 205820 kb
Host smart-4601d1ce-4755-4a59-b20b-fe1e8d5b8ecf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079945991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_smbus_maxlen.1079945991
Directory /workspace/14.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3889711017
Short name T1435
Test name
Test status
Simulation time 902151894 ps
CPU time 13.45 seconds
Started Aug 11 05:28:08 PM PDT 24
Finished Aug 11 05:28:22 PM PDT 24
Peak memory 216912 kb
Host smart-f1867553-56ce-4993-a544-d5035adfe63b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889711017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3889711017
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.2236360558
Short name T1484
Test name
Test status
Simulation time 39593201035 ps
CPU time 47.44 seconds
Started Aug 11 05:28:15 PM PDT 24
Finished Aug 11 05:29:02 PM PDT 24
Peak memory 303704 kb
Host smart-ddf362f8-8cba-43bd-852b-dbc301b90066
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236360558 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_stress_all.2236360558
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1144394534
Short name T493
Test name
Test status
Simulation time 3036456127 ps
CPU time 21.9 seconds
Started Aug 11 05:28:06 PM PDT 24
Finished Aug 11 05:28:28 PM PDT 24
Peak memory 222132 kb
Host smart-da4bfa5e-4310-4ded-90f8-e30974117875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144394534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1144394534
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.2917350431
Short name T399
Test name
Test status
Simulation time 37588126701 ps
CPU time 72.96 seconds
Started Aug 11 05:28:07 PM PDT 24
Finished Aug 11 05:29:21 PM PDT 24
Peak memory 1249948 kb
Host smart-67d88b9e-a92f-483d-916c-6a2577795ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917350431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.2917350431
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1936345050
Short name T1086
Test name
Test status
Simulation time 5995818528 ps
CPU time 96.63 seconds
Started Aug 11 05:28:07 PM PDT 24
Finished Aug 11 05:29:44 PM PDT 24
Peak memory 1181284 kb
Host smart-16ee2bd0-b402-4070-906c-c5e0dc32075a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936345050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1936345050
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.3791777828
Short name T468
Test name
Test status
Simulation time 4906424104 ps
CPU time 7.33 seconds
Started Aug 11 05:28:05 PM PDT 24
Finished Aug 11 05:28:13 PM PDT 24
Peak memory 213900 kb
Host smart-9850af5b-c51a-4dc8-96d8-7f04a07c6f20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791777828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.3791777828
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.843130492
Short name T1246
Test name
Test status
Simulation time 133886994 ps
CPU time 1.95 seconds
Started Aug 11 05:28:12 PM PDT 24
Finished Aug 11 05:28:14 PM PDT 24
Peak memory 205708 kb
Host smart-4d993b0b-3c5d-48dc-a46e-0683e445abdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843130492 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.843130492
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.105891978
Short name T1646
Test name
Test status
Simulation time 18531123 ps
CPU time 0.66 seconds
Started Aug 11 05:28:24 PM PDT 24
Finished Aug 11 05:28:25 PM PDT 24
Peak memory 204736 kb
Host smart-62b38cd0-732c-46dd-a2db-38bd74a5cfa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105891978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.105891978
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.588716287
Short name T692
Test name
Test status
Simulation time 165863255 ps
CPU time 1.68 seconds
Started Aug 11 05:28:14 PM PDT 24
Finished Aug 11 05:28:16 PM PDT 24
Peak memory 213724 kb
Host smart-1b5a4d7d-e0b9-40f3-8e8c-7dee6ff1c097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588716287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.588716287
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.1961502242
Short name T1147
Test name
Test status
Simulation time 1944987183 ps
CPU time 18.67 seconds
Started Aug 11 05:28:11 PM PDT 24
Finished Aug 11 05:28:30 PM PDT 24
Peak memory 284020 kb
Host smart-243fb947-bfa8-4603-a8e0-02913ad89020
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961502242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.1961502242
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.2181583254
Short name T157
Test name
Test status
Simulation time 10449447676 ps
CPU time 68.5 seconds
Started Aug 11 05:28:12 PM PDT 24
Finished Aug 11 05:29:20 PM PDT 24
Peak memory 398460 kb
Host smart-4ffa36fb-7e4e-4a5d-99e2-527b2e1576af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181583254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.2181583254
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3575905357
Short name T703
Test name
Test status
Simulation time 4299085637 ps
CPU time 144.34 seconds
Started Aug 11 05:28:13 PM PDT 24
Finished Aug 11 05:30:38 PM PDT 24
Peak memory 678648 kb
Host smart-501686c1-fc2f-40e6-b91d-4f108dd9dc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575905357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3575905357
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.4272719368
Short name T546
Test name
Test status
Simulation time 91856465 ps
CPU time 0.93 seconds
Started Aug 11 05:28:16 PM PDT 24
Finished Aug 11 05:28:17 PM PDT 24
Peak memory 205268 kb
Host smart-8d103df2-67b8-476c-94a6-1ee8e8c82780
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272719368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.4272719368
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.834032327
Short name T1663
Test name
Test status
Simulation time 519298501 ps
CPU time 7.76 seconds
Started Aug 11 05:28:24 PM PDT 24
Finished Aug 11 05:28:32 PM PDT 24
Peak memory 205524 kb
Host smart-c8c6979a-21dc-445c-bb3a-eb10b4154b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834032327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.834032327
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3784128123
Short name T524
Test name
Test status
Simulation time 653900076 ps
CPU time 8.38 seconds
Started Aug 11 05:28:14 PM PDT 24
Finished Aug 11 05:28:22 PM PDT 24
Peak memory 229396 kb
Host smart-b10d217b-3b0b-4d50-8821-175c35a194af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784128123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3784128123
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.1491392395
Short name T1262
Test name
Test status
Simulation time 67019535 ps
CPU time 1.08 seconds
Started Aug 11 05:28:13 PM PDT 24
Finished Aug 11 05:28:14 PM PDT 24
Peak memory 223068 kb
Host smart-8ccabdf8-21ca-486b-bfd6-7ff58f4313b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491392395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.1491392395
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.526540507
Short name T1286
Test name
Test status
Simulation time 43145318142 ps
CPU time 31.23 seconds
Started Aug 11 05:28:14 PM PDT 24
Finished Aug 11 05:28:46 PM PDT 24
Peak memory 359980 kb
Host smart-e87fe24a-8c47-4dd7-9c05-4848e0e2c440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526540507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.526540507
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.4122738769
Short name T280
Test name
Test status
Simulation time 38164400730 ps
CPU time 822.64 seconds
Started Aug 11 05:28:13 PM PDT 24
Finished Aug 11 05:41:56 PM PDT 24
Peak memory 1698400 kb
Host smart-075ae409-8a41-4118-9901-41aa775e336b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122738769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.4122738769
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.315698594
Short name T717
Test name
Test status
Simulation time 2658878223 ps
CPU time 32.21 seconds
Started Aug 11 05:28:12 PM PDT 24
Finished Aug 11 05:28:45 PM PDT 24
Peak memory 213720 kb
Host smart-fec1c938-15bc-4249-bc02-4531396384db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315698594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.315698594
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.187167949
Short name T1710
Test name
Test status
Simulation time 2980080858 ps
CPU time 7.46 seconds
Started Aug 11 05:28:18 PM PDT 24
Finished Aug 11 05:28:25 PM PDT 24
Peak memory 214624 kb
Host smart-ee1aedde-c5d0-4e32-bb1b-720a9eb9d0c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187167949 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.187167949
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3637190598
Short name T345
Test name
Test status
Simulation time 397038167 ps
CPU time 1.37 seconds
Started Aug 11 05:28:24 PM PDT 24
Finished Aug 11 05:28:25 PM PDT 24
Peak memory 205708 kb
Host smart-1036d342-ef24-45bf-bd4c-c2c3984afbeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637190598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3637190598
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.825549909
Short name T89
Test name
Test status
Simulation time 162577745 ps
CPU time 1.06 seconds
Started Aug 11 05:28:19 PM PDT 24
Finished Aug 11 05:28:20 PM PDT 24
Peak memory 205560 kb
Host smart-9ba62a65-8310-4997-8888-e16bc40e4f9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825549909 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.825549909
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.1035632088
Short name T1240
Test name
Test status
Simulation time 1017291703 ps
CPU time 2.69 seconds
Started Aug 11 05:28:17 PM PDT 24
Finished Aug 11 05:28:20 PM PDT 24
Peak memory 205720 kb
Host smart-6db47d89-0a88-45f6-9aad-ba8f22cdfe49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035632088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.1035632088
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.298888722
Short name T899
Test name
Test status
Simulation time 234237428 ps
CPU time 1.07 seconds
Started Aug 11 05:28:20 PM PDT 24
Finished Aug 11 05:28:21 PM PDT 24
Peak memory 205300 kb
Host smart-be4d4538-d9bc-44b2-a745-a6f41e15d0bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298888722 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.298888722
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2693217371
Short name T599
Test name
Test status
Simulation time 290035168 ps
CPU time 2.32 seconds
Started Aug 11 05:28:18 PM PDT 24
Finished Aug 11 05:28:21 PM PDT 24
Peak memory 213796 kb
Host smart-87ef24c6-d2e0-4624-b0fa-3a725c5cebce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693217371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2693217371
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1231243054
Short name T988
Test name
Test status
Simulation time 492384554 ps
CPU time 3.26 seconds
Started Aug 11 05:28:13 PM PDT 24
Finished Aug 11 05:28:17 PM PDT 24
Peak memory 213816 kb
Host smart-48944e5d-a912-44b0-822b-d67d88ae4edf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231243054 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1231243054
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.2129833473
Short name T611
Test name
Test status
Simulation time 8263350130 ps
CPU time 11.83 seconds
Started Aug 11 05:28:19 PM PDT 24
Finished Aug 11 05:28:31 PM PDT 24
Peak memory 270076 kb
Host smart-f7c15509-1833-4285-bb62-0411eeb7a4dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129833473 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2129833473
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull.3674035194
Short name T1012
Test name
Test status
Simulation time 2662611895 ps
CPU time 2.73 seconds
Started Aug 11 05:28:21 PM PDT 24
Finished Aug 11 05:28:24 PM PDT 24
Peak memory 213928 kb
Host smart-fda2f53c-2107-44ed-8018-86ab45c9f4f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674035194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_nack_acqfull.3674035194
Directory /workspace/15.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/15.i2c_target_nack_acqfull_addr.868232468
Short name T1301
Test name
Test status
Simulation time 413951207 ps
CPU time 2.21 seconds
Started Aug 11 05:28:26 PM PDT 24
Finished Aug 11 05:28:28 PM PDT 24
Peak memory 205540 kb
Host smart-a71dff9e-ff39-4db2-b1ba-e2035ad3a7b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868232468 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.868232468
Directory /workspace/15.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/15.i2c_target_nack_txstretch.3942171216
Short name T673
Test name
Test status
Simulation time 961508427 ps
CPU time 1.53 seconds
Started Aug 11 05:28:26 PM PDT 24
Finished Aug 11 05:28:28 PM PDT 24
Peak memory 222556 kb
Host smart-6c4f2edf-a240-47fb-9ad0-37a2fdec6e64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942171216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_nack_txstretch.3942171216
Directory /workspace/15.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/15.i2c_target_perf.4015475110
Short name T402
Test name
Test status
Simulation time 2335931399 ps
CPU time 4.6 seconds
Started Aug 11 05:28:19 PM PDT 24
Finished Aug 11 05:28:23 PM PDT 24
Peak memory 222168 kb
Host smart-8e17da6f-80bb-4675-947c-f7e757fc153b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015475110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.4015475110
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smbus_maxlen.3623058371
Short name T1084
Test name
Test status
Simulation time 1531725802 ps
CPU time 1.93 seconds
Started Aug 11 05:28:21 PM PDT 24
Finished Aug 11 05:28:23 PM PDT 24
Peak memory 205444 kb
Host smart-a782b6d0-380e-436b-9175-5baa430c0ba4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623058371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_smbus_maxlen.3623058371
Directory /workspace/15.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1431279672
Short name T806
Test name
Test status
Simulation time 830260843 ps
CPU time 10.64 seconds
Started Aug 11 05:28:12 PM PDT 24
Finished Aug 11 05:28:22 PM PDT 24
Peak memory 213856 kb
Host smart-a1410f2d-51e1-4c89-ad21-af8783b1e0e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431279672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1431279672
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.3939366579
Short name T134
Test name
Test status
Simulation time 25924815187 ps
CPU time 608.47 seconds
Started Aug 11 05:28:18 PM PDT 24
Finished Aug 11 05:38:27 PM PDT 24
Peak memory 2987772 kb
Host smart-c1601b8a-f7e4-42c4-94a7-3283f6e0fb41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939366579 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.3939366579
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3602948155
Short name T695
Test name
Test status
Simulation time 3226343057 ps
CPU time 6.96 seconds
Started Aug 11 05:28:11 PM PDT 24
Finished Aug 11 05:28:18 PM PDT 24
Peak memory 205760 kb
Host smart-a17bb264-f813-42ed-835c-4d54cb2f7d41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602948155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3602948155
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.2571124315
Short name T413
Test name
Test status
Simulation time 43158279257 ps
CPU time 898.4 seconds
Started Aug 11 05:28:12 PM PDT 24
Finished Aug 11 05:43:11 PM PDT 24
Peak memory 5924512 kb
Host smart-0440e83e-46d4-4587-8c36-c0c6d7073932
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571124315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.2571124315
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2059661743
Short name T1555
Test name
Test status
Simulation time 2238658825 ps
CPU time 8.66 seconds
Started Aug 11 05:28:12 PM PDT 24
Finished Aug 11 05:28:21 PM PDT 24
Peak memory 314072 kb
Host smart-a36849d6-42e7-4fc1-bcb0-e1ebdf60aa3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059661743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2059661743
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3672655153
Short name T1273
Test name
Test status
Simulation time 1804170550 ps
CPU time 6.87 seconds
Started Aug 11 05:28:20 PM PDT 24
Finished Aug 11 05:28:27 PM PDT 24
Peak memory 220744 kb
Host smart-1cc33b8d-556e-46fc-b434-98b55e1761d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672655153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3672655153
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2218111658
Short name T1625
Test name
Test status
Simulation time 16938007 ps
CPU time 0.63 seconds
Started Aug 11 05:28:31 PM PDT 24
Finished Aug 11 05:28:32 PM PDT 24
Peak memory 204684 kb
Host smart-96f71c57-894a-4efa-95a7-900d26604d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218111658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2218111658
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.3043929426
Short name T997
Test name
Test status
Simulation time 792305629 ps
CPU time 8.28 seconds
Started Aug 11 05:28:27 PM PDT 24
Finished Aug 11 05:28:36 PM PDT 24
Peak memory 263768 kb
Host smart-74432c9a-aa01-41f4-a7c7-d14d963f635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043929426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3043929426
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3312455721
Short name T689
Test name
Test status
Simulation time 2056110197 ps
CPU time 10.44 seconds
Started Aug 11 05:28:25 PM PDT 24
Finished Aug 11 05:28:35 PM PDT 24
Peak memory 296168 kb
Host smart-b5a4dd0e-77b7-4ccc-bcd4-54a9b54c0dd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312455721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.3312455721
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2188161355
Short name T1200
Test name
Test status
Simulation time 2853665767 ps
CPU time 178.61 seconds
Started Aug 11 05:28:27 PM PDT 24
Finished Aug 11 05:31:26 PM PDT 24
Peak memory 461376 kb
Host smart-e0bd9ddc-3e3c-41a3-90a4-b47208f1e84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188161355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2188161355
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2712163314
Short name T1156
Test name
Test status
Simulation time 9166844713 ps
CPU time 83.38 seconds
Started Aug 11 05:28:25 PM PDT 24
Finished Aug 11 05:29:48 PM PDT 24
Peak memory 780544 kb
Host smart-fa9e1a57-ae4d-449f-ae13-252afda315ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712163314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2712163314
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.240951432
Short name T1072
Test name
Test status
Simulation time 125750120 ps
CPU time 1.15 seconds
Started Aug 11 05:28:24 PM PDT 24
Finished Aug 11 05:28:25 PM PDT 24
Peak memory 205252 kb
Host smart-5d1d06a9-5bad-4de2-a6fa-09c3e31278fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240951432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.240951432
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3632005371
Short name T412
Test name
Test status
Simulation time 599196921 ps
CPU time 3.51 seconds
Started Aug 11 05:28:24 PM PDT 24
Finished Aug 11 05:28:28 PM PDT 24
Peak memory 205508 kb
Host smart-0f0b5f29-a61b-430b-a910-4f25ec9720b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632005371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3632005371
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3746355137
Short name T1679
Test name
Test status
Simulation time 26216376368 ps
CPU time 148.63 seconds
Started Aug 11 05:28:23 PM PDT 24
Finished Aug 11 05:30:52 PM PDT 24
Peak memory 1611108 kb
Host smart-25cf62e4-344f-4840-b2d4-5b68cbb1acda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746355137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3746355137
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.2454534144
Short name T11
Test name
Test status
Simulation time 404009510 ps
CPU time 1.88 seconds
Started Aug 11 05:28:31 PM PDT 24
Finished Aug 11 05:28:33 PM PDT 24
Peak memory 221840 kb
Host smart-ef801cec-5a7b-40b1-af77-a697761b8939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454534144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.2454534144
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.2614948207
Short name T1075
Test name
Test status
Simulation time 18606415 ps
CPU time 0.7 seconds
Started Aug 11 05:28:25 PM PDT 24
Finished Aug 11 05:28:26 PM PDT 24
Peak memory 205180 kb
Host smart-8093ece9-6df8-4bdb-b025-406e9781db2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614948207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2614948207
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.1782273227
Short name T752
Test name
Test status
Simulation time 446626592 ps
CPU time 4.63 seconds
Started Aug 11 05:28:25 PM PDT 24
Finished Aug 11 05:28:29 PM PDT 24
Peak memory 229924 kb
Host smart-d53e4ea7-aead-4183-8a44-afd4c43ec1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782273227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1782273227
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.258761812
Short name T819
Test name
Test status
Simulation time 2779752214 ps
CPU time 33.2 seconds
Started Aug 11 05:28:25 PM PDT 24
Finished Aug 11 05:28:58 PM PDT 24
Peak memory 365520 kb
Host smart-7d603fbf-dd39-4f48-8cf9-74af564a2aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258761812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.258761812
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2761501605
Short name T28
Test name
Test status
Simulation time 1432435489 ps
CPU time 66.4 seconds
Started Aug 11 05:28:25 PM PDT 24
Finished Aug 11 05:29:32 PM PDT 24
Peak memory 366120 kb
Host smart-154f5bd7-827b-47c1-b761-981de5539fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761501605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2761501605
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.1571753948
Short name T1018
Test name
Test status
Simulation time 569531433 ps
CPU time 8.34 seconds
Started Aug 11 05:28:24 PM PDT 24
Finished Aug 11 05:28:33 PM PDT 24
Peak memory 213648 kb
Host smart-a9b06712-ca68-47ad-84fc-93243cdd8d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571753948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1571753948
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1931080772
Short name T63
Test name
Test status
Simulation time 1360613199 ps
CPU time 3.42 seconds
Started Aug 11 05:28:31 PM PDT 24
Finished Aug 11 05:28:35 PM PDT 24
Peak memory 217656 kb
Host smart-6d07605c-8ab1-47f3-baa2-6e4b03070382
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931080772 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1931080772
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2817084120
Short name T936
Test name
Test status
Simulation time 1788199709 ps
CPU time 1.49 seconds
Started Aug 11 05:28:33 PM PDT 24
Finished Aug 11 05:28:34 PM PDT 24
Peak memory 205404 kb
Host smart-e4cab511-41e7-415e-be42-adff3b9a796e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817084120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.2817084120
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.3111583091
Short name T1242
Test name
Test status
Simulation time 381371075 ps
CPU time 1.46 seconds
Started Aug 11 05:28:34 PM PDT 24
Finished Aug 11 05:28:36 PM PDT 24
Peak memory 205616 kb
Host smart-7e092d5d-b822-41ff-a197-7ed1f39cf3c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111583091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.3111583091
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.3484997852
Short name T1681
Test name
Test status
Simulation time 1252329647 ps
CPU time 3 seconds
Started Aug 11 05:28:32 PM PDT 24
Finished Aug 11 05:28:35 PM PDT 24
Peak memory 205548 kb
Host smart-4cf81b7a-ecbc-4548-9817-fa1d72dc2396
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484997852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.3484997852
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.1602954165
Short name T438
Test name
Test status
Simulation time 158724290 ps
CPU time 1.52 seconds
Started Aug 11 05:28:34 PM PDT 24
Finished Aug 11 05:28:36 PM PDT 24
Peak memory 205444 kb
Host smart-de3cc055-4100-49fe-af25-39fe1c8e09f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602954165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.1602954165
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.4069947689
Short name T1295
Test name
Test status
Simulation time 2133729646 ps
CPU time 2.82 seconds
Started Aug 11 05:28:31 PM PDT 24
Finished Aug 11 05:28:34 PM PDT 24
Peak memory 213804 kb
Host smart-e51e129f-6f4b-4bf9-9f2a-b9e753c947e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069947689 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.4069947689
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.786264971
Short name T304
Test name
Test status
Simulation time 17195309016 ps
CPU time 7.29 seconds
Started Aug 11 05:28:34 PM PDT 24
Finished Aug 11 05:28:41 PM PDT 24
Peak memory 213968 kb
Host smart-da43c4a8-8473-420b-99b0-1f020a5e4719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786264971 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.786264971
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3303088796
Short name T518
Test name
Test status
Simulation time 9359590692 ps
CPU time 84.57 seconds
Started Aug 11 05:28:32 PM PDT 24
Finished Aug 11 05:29:57 PM PDT 24
Peak memory 1775908 kb
Host smart-b4a5b16f-ad4e-44a6-838e-ce681ebe605c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303088796 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3303088796
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull.598243419
Short name T623
Test name
Test status
Simulation time 578263172 ps
CPU time 3.27 seconds
Started Aug 11 05:28:30 PM PDT 24
Finished Aug 11 05:28:34 PM PDT 24
Peak memory 213748 kb
Host smart-33e73138-785c-4f8f-ba07-ef95054d6018
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598243419 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_nack_acqfull.598243419
Directory /workspace/16.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/16.i2c_target_nack_acqfull_addr.4030088102
Short name T1454
Test name
Test status
Simulation time 1897271270 ps
CPU time 2.61 seconds
Started Aug 11 05:28:32 PM PDT 24
Finished Aug 11 05:28:35 PM PDT 24
Peak memory 205516 kb
Host smart-19a709c7-f357-4b93-a04f-4fa63172bf31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030088102 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_nack_acqfull_addr.4030088102
Directory /workspace/16.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.413577579
Short name T1375
Test name
Test status
Simulation time 7154583576 ps
CPU time 3.13 seconds
Started Aug 11 05:28:30 PM PDT 24
Finished Aug 11 05:28:33 PM PDT 24
Peak memory 215088 kb
Host smart-d6d5f0df-2107-4aad-a19e-b083ca45c743
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413577579 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_perf.413577579
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smbus_maxlen.1271619938
Short name T315
Test name
Test status
Simulation time 1838651290 ps
CPU time 2.26 seconds
Started Aug 11 05:28:29 PM PDT 24
Finished Aug 11 05:28:31 PM PDT 24
Peak memory 205468 kb
Host smart-f4beddab-e414-4a1c-9ffb-d0dff1b8d3a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271619938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_smbus_maxlen.1271619938
Directory /workspace/16.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2289964371
Short name T1194
Test name
Test status
Simulation time 1005910239 ps
CPU time 13.24 seconds
Started Aug 11 05:28:27 PM PDT 24
Finished Aug 11 05:28:40 PM PDT 24
Peak memory 213764 kb
Host smart-4875f734-5c4c-45cc-86ac-11cb0474350c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289964371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2289964371
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.1749642057
Short name T685
Test name
Test status
Simulation time 36908361859 ps
CPU time 1062.83 seconds
Started Aug 11 05:28:31 PM PDT 24
Finished Aug 11 05:46:14 PM PDT 24
Peak memory 4660204 kb
Host smart-7ef96f8c-22e1-44cf-b1f5-e4e2d517285e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749642057 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.1749642057
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.1191390168
Short name T714
Test name
Test status
Simulation time 707486531 ps
CPU time 29.22 seconds
Started Aug 11 05:28:31 PM PDT 24
Finished Aug 11 05:29:00 PM PDT 24
Peak memory 213808 kb
Host smart-447958c4-5883-451a-9263-d989782da1d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191390168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.1191390168
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.3150282446
Short name T431
Test name
Test status
Simulation time 14442068973 ps
CPU time 26.27 seconds
Started Aug 11 05:28:30 PM PDT 24
Finished Aug 11 05:28:56 PM PDT 24
Peak memory 205680 kb
Host smart-871adddf-47c8-41b4-982d-52502f8980af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150282446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.3150282446
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.805123587
Short name T531
Test name
Test status
Simulation time 295055704 ps
CPU time 1.5 seconds
Started Aug 11 05:28:31 PM PDT 24
Finished Aug 11 05:28:32 PM PDT 24
Peak memory 205672 kb
Host smart-1444dba3-efb8-4e56-a8e8-6f0f33e57abe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805123587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stretch.805123587
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2687378411
Short name T312
Test name
Test status
Simulation time 1133279765 ps
CPU time 6.94 seconds
Started Aug 11 05:28:32 PM PDT 24
Finished Aug 11 05:28:39 PM PDT 24
Peak memory 221900 kb
Host smart-792cc415-fac5-47fc-b10b-54359003bed6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687378411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2687378411
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.1728668485
Short name T1414
Test name
Test status
Simulation time 566852507 ps
CPU time 8.35 seconds
Started Aug 11 05:28:30 PM PDT 24
Finished Aug 11 05:28:39 PM PDT 24
Peak memory 213792 kb
Host smart-2b30d230-414f-4d4b-996a-5f9701fc7e69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728668485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.1728668485
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.948333179
Short name T628
Test name
Test status
Simulation time 35704581 ps
CPU time 0.64 seconds
Started Aug 11 05:28:46 PM PDT 24
Finished Aug 11 05:28:47 PM PDT 24
Peak memory 204744 kb
Host smart-6ea6a613-6972-4c56-9910-51b253ad5fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948333179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.948333179
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2747533977
Short name T723
Test name
Test status
Simulation time 91486121 ps
CPU time 1.94 seconds
Started Aug 11 05:28:35 PM PDT 24
Finished Aug 11 05:28:37 PM PDT 24
Peak memory 213708 kb
Host smart-b6397788-4a0c-480c-b79c-96191b6dd35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747533977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2747533977
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1636973186
Short name T1098
Test name
Test status
Simulation time 585352511 ps
CPU time 4.48 seconds
Started Aug 11 05:28:35 PM PDT 24
Finished Aug 11 05:28:40 PM PDT 24
Peak memory 243272 kb
Host smart-82359341-8e61-4c2f-9859-8b8158a6cd4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636973186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1636973186
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3243670062
Short name T1087
Test name
Test status
Simulation time 16944731605 ps
CPU time 98.09 seconds
Started Aug 11 05:28:36 PM PDT 24
Finished Aug 11 05:30:14 PM PDT 24
Peak memory 547588 kb
Host smart-d65b0f71-b33a-4249-a2b2-94e6346b66ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243670062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3243670062
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2784125371
Short name T1275
Test name
Test status
Simulation time 3054515806 ps
CPU time 98.56 seconds
Started Aug 11 05:28:36 PM PDT 24
Finished Aug 11 05:30:15 PM PDT 24
Peak memory 527236 kb
Host smart-9632d973-2c26-4ec9-8d1f-d936b2f64da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784125371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2784125371
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.104986619
Short name T532
Test name
Test status
Simulation time 126849516 ps
CPU time 1.16 seconds
Started Aug 11 05:28:35 PM PDT 24
Finished Aug 11 05:28:36 PM PDT 24
Peak memory 205296 kb
Host smart-95af8a90-dbe9-4ac9-adb0-bcca6b439da4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104986619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.104986619
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.649492084
Short name T943
Test name
Test status
Simulation time 155672328 ps
CPU time 4.23 seconds
Started Aug 11 05:28:41 PM PDT 24
Finished Aug 11 05:28:45 PM PDT 24
Peak memory 232080 kb
Host smart-91c026ea-6a29-48ad-aff0-c7d92a757b90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649492084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.
649492084
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2922540861
Short name T766
Test name
Test status
Simulation time 10067230508 ps
CPU time 373.69 seconds
Started Aug 11 05:28:36 PM PDT 24
Finished Aug 11 05:34:50 PM PDT 24
Peak memory 1455720 kb
Host smart-27671c7f-c439-4d8a-bb3c-9f3cdcd0c5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922540861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2922540861
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1267937147
Short name T1702
Test name
Test status
Simulation time 3056718710 ps
CPU time 15.93 seconds
Started Aug 11 05:28:44 PM PDT 24
Finished Aug 11 05:29:00 PM PDT 24
Peak memory 205636 kb
Host smart-85a3f897-8331-4665-bc2e-421a2086f173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267937147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1267937147
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_override.2164649871
Short name T1700
Test name
Test status
Simulation time 48570764 ps
CPU time 0.67 seconds
Started Aug 11 05:28:33 PM PDT 24
Finished Aug 11 05:28:34 PM PDT 24
Peak memory 205188 kb
Host smart-cc2ddf87-2a72-48b2-8cdd-936e880e707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164649871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2164649871
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.1825071362
Short name T967
Test name
Test status
Simulation time 234783035 ps
CPU time 2.98 seconds
Started Aug 11 05:28:36 PM PDT 24
Finished Aug 11 05:28:40 PM PDT 24
Peak memory 222996 kb
Host smart-ba1430d8-f4e2-441c-ae9f-be48deebc7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825071362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.1825071362
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.987901931
Short name T469
Test name
Test status
Simulation time 7563586101 ps
CPU time 35.01 seconds
Started Aug 11 05:28:30 PM PDT 24
Finished Aug 11 05:29:05 PM PDT 24
Peak memory 428112 kb
Host smart-98d0ec9c-1f41-42c0-aaeb-86dadd5862f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987901931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.987901931
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1416795508
Short name T1413
Test name
Test status
Simulation time 382450233 ps
CPU time 17.29 seconds
Started Aug 11 05:28:40 PM PDT 24
Finished Aug 11 05:28:58 PM PDT 24
Peak memory 213680 kb
Host smart-12d07cf8-c5d4-4b92-a175-2880a4f7ab33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416795508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1416795508
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1945595654
Short name T1707
Test name
Test status
Simulation time 2397573784 ps
CPU time 5.46 seconds
Started Aug 11 05:28:44 PM PDT 24
Finished Aug 11 05:28:49 PM PDT 24
Peak memory 217432 kb
Host smart-3aea0d0b-14f1-42a2-aa68-1db2540252fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945595654 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1945595654
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.4042118891
Short name T1577
Test name
Test status
Simulation time 385226238 ps
CPU time 1.49 seconds
Started Aug 11 05:28:43 PM PDT 24
Finished Aug 11 05:28:44 PM PDT 24
Peak memory 205632 kb
Host smart-f1311970-d248-47a1-854e-0c033bfb02c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042118891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.4042118891
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.2969696846
Short name T1092
Test name
Test status
Simulation time 455722578 ps
CPU time 2.42 seconds
Started Aug 11 05:28:44 PM PDT 24
Finished Aug 11 05:28:46 PM PDT 24
Peak memory 205576 kb
Host smart-0591ca0c-391a-4ddb-8e61-9df5636e5047
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969696846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.2969696846
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.2401341519
Short name T991
Test name
Test status
Simulation time 483920018 ps
CPU time 1.13 seconds
Started Aug 11 05:28:44 PM PDT 24
Finished Aug 11 05:28:45 PM PDT 24
Peak memory 205416 kb
Host smart-26ff3ffd-8d01-4bb9-8edb-a0d04eb65de5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401341519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.2401341519
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.2972127989
Short name T864
Test name
Test status
Simulation time 625998320 ps
CPU time 3.96 seconds
Started Aug 11 05:28:42 PM PDT 24
Finished Aug 11 05:28:46 PM PDT 24
Peak memory 221804 kb
Host smart-e4d19399-b893-45a2-94b2-afe788e3789d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972127989 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.2972127989
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.4096056567
Short name T338
Test name
Test status
Simulation time 6391927062 ps
CPU time 10.75 seconds
Started Aug 11 05:28:41 PM PDT 24
Finished Aug 11 05:28:52 PM PDT 24
Peak memory 479288 kb
Host smart-ac3a3119-2b98-42bb-b018-8b070a4aa059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096056567 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.4096056567
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull.1377636992
Short name T160
Test name
Test status
Simulation time 1111333580 ps
CPU time 2.97 seconds
Started Aug 11 05:28:43 PM PDT 24
Finished Aug 11 05:28:46 PM PDT 24
Peak memory 213836 kb
Host smart-ffbdc5b5-0801-4cbc-b7d0-8fa496419b69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377636992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_nack_acqfull.1377636992
Directory /workspace/17.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/17.i2c_target_nack_acqfull_addr.3745011711
Short name T1686
Test name
Test status
Simulation time 2592107299 ps
CPU time 2.61 seconds
Started Aug 11 05:28:44 PM PDT 24
Finished Aug 11 05:28:47 PM PDT 24
Peak memory 205736 kb
Host smart-4dad85d7-26b3-48ef-914a-738aa69869c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745011711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_nack_acqfull_addr.3745011711
Directory /workspace/17.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/17.i2c_target_nack_txstretch.945616143
Short name T957
Test name
Test status
Simulation time 288420848 ps
CPU time 1.36 seconds
Started Aug 11 05:28:42 PM PDT 24
Finished Aug 11 05:28:44 PM PDT 24
Peak memory 222312 kb
Host smart-a951d5c0-2f00-4d8b-b4c7-147a27205308
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945616143 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_nack_txstretch.945616143
Directory /workspace/17.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/17.i2c_target_perf.3195068707
Short name T1058
Test name
Test status
Simulation time 2948064478 ps
CPU time 6.1 seconds
Started Aug 11 05:28:44 PM PDT 24
Finished Aug 11 05:28:50 PM PDT 24
Peak memory 212308 kb
Host smart-a55b34ec-5591-432d-b59c-8443f24631b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195068707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.3195068707
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smbus_maxlen.1051789639
Short name T863
Test name
Test status
Simulation time 4328453112 ps
CPU time 2.36 seconds
Started Aug 11 05:28:46 PM PDT 24
Finished Aug 11 05:28:48 PM PDT 24
Peak memory 205532 kb
Host smart-22209071-86ae-4069-84a6-53064941e487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051789639 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_smbus_maxlen.1051789639
Directory /workspace/17.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1782366636
Short name T1083
Test name
Test status
Simulation time 1726934589 ps
CPU time 5.85 seconds
Started Aug 11 05:28:36 PM PDT 24
Finished Aug 11 05:28:42 PM PDT 24
Peak memory 214128 kb
Host smart-290e43bb-cb58-4034-a4b5-e51036db5b27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782366636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1782366636
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.2013733279
Short name T1626
Test name
Test status
Simulation time 26485030028 ps
CPU time 29.04 seconds
Started Aug 11 05:28:44 PM PDT 24
Finished Aug 11 05:29:13 PM PDT 24
Peak memory 238300 kb
Host smart-9072e326-59a0-4af4-bdd8-f8f3fafa43a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013733279 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.2013733279
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.536578900
Short name T381
Test name
Test status
Simulation time 29789165324 ps
CPU time 83.52 seconds
Started Aug 11 05:28:37 PM PDT 24
Finished Aug 11 05:30:01 PM PDT 24
Peak memory 222104 kb
Host smart-22ca372d-e12c-4e09-a418-77f3b8dc92d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536578900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.536578900
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2401446041
Short name T355
Test name
Test status
Simulation time 18550238073 ps
CPU time 32.58 seconds
Started Aug 11 05:28:35 PM PDT 24
Finished Aug 11 05:29:08 PM PDT 24
Peak memory 205620 kb
Host smart-d43245c9-c904-421e-9d37-f79292e8c8a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401446041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2401446041
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2908981319
Short name T1220
Test name
Test status
Simulation time 2933538936 ps
CPU time 30.17 seconds
Started Aug 11 05:28:41 PM PDT 24
Finished Aug 11 05:29:11 PM PDT 24
Peak memory 351996 kb
Host smart-c723223f-f6eb-4fed-8475-25c21f8809fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908981319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2908981319
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.209776348
Short name T659
Test name
Test status
Simulation time 10620703369 ps
CPU time 6.58 seconds
Started Aug 11 05:28:35 PM PDT 24
Finished Aug 11 05:28:42 PM PDT 24
Peak memory 221996 kb
Host smart-1427fe3e-fb0e-4569-bf8b-65e9c7484adc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209776348 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.209776348
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.2351480448
Short name T1063
Test name
Test status
Simulation time 95769346 ps
CPU time 2.07 seconds
Started Aug 11 05:28:41 PM PDT 24
Finished Aug 11 05:28:43 PM PDT 24
Peak memory 205616 kb
Host smart-5018d664-51ef-42ec-b093-cb4375bf0de3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351480448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.2351480448
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3472001077
Short name T1080
Test name
Test status
Simulation time 16506524 ps
CPU time 0.64 seconds
Started Aug 11 05:28:59 PM PDT 24
Finished Aug 11 05:29:00 PM PDT 24
Peak memory 204700 kb
Host smart-abed1c3e-175f-4809-89c1-e0ff1f92ff5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472001077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3472001077
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.210682836
Short name T657
Test name
Test status
Simulation time 84092972 ps
CPU time 1.76 seconds
Started Aug 11 05:28:50 PM PDT 24
Finished Aug 11 05:28:52 PM PDT 24
Peak memory 205572 kb
Host smart-030a0e97-8c35-4782-8cfd-aaec575d266e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210682836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.210682836
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1726060664
Short name T1257
Test name
Test status
Simulation time 466290360 ps
CPU time 4.77 seconds
Started Aug 11 05:28:49 PM PDT 24
Finished Aug 11 05:28:54 PM PDT 24
Peak memory 258900 kb
Host smart-132070e7-499f-47a9-866b-e15ecaa3b07a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726060664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1726060664
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2963130468
Short name T365
Test name
Test status
Simulation time 16749767358 ps
CPU time 121.28 seconds
Started Aug 11 05:28:49 PM PDT 24
Finished Aug 11 05:30:50 PM PDT 24
Peak memory 800052 kb
Host smart-8bd24916-77e5-4883-bc0b-0a275cfc1fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963130468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2963130468
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3432426530
Short name T1163
Test name
Test status
Simulation time 9945843621 ps
CPU time 70.7 seconds
Started Aug 11 05:28:41 PM PDT 24
Finished Aug 11 05:29:52 PM PDT 24
Peak memory 775252 kb
Host smart-bdf33588-5ca2-4d85-b338-22e3255a6c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432426530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3432426530
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3126298832
Short name T242
Test name
Test status
Simulation time 889617537 ps
CPU time 1.18 seconds
Started Aug 11 05:28:41 PM PDT 24
Finished Aug 11 05:28:42 PM PDT 24
Peak memory 205288 kb
Host smart-c0c12a24-9ee6-4ceb-9c24-d45b5a08a34c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126298832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3126298832
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3920459117
Short name T677
Test name
Test status
Simulation time 640750191 ps
CPU time 8.08 seconds
Started Aug 11 05:28:47 PM PDT 24
Finished Aug 11 05:28:56 PM PDT 24
Peak memory 229336 kb
Host smart-4896a9c1-97ca-4735-bd95-ec948886191d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920459117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3920459117
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.20874642
Short name T107
Test name
Test status
Simulation time 4620988901 ps
CPU time 115.32 seconds
Started Aug 11 05:28:43 PM PDT 24
Finished Aug 11 05:30:38 PM PDT 24
Peak memory 1296728 kb
Host smart-fc6386eb-9754-436c-99bb-2848311a46af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20874642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.20874642
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.2779529307
Short name T1169
Test name
Test status
Simulation time 1223727842 ps
CPU time 6.05 seconds
Started Aug 11 05:28:56 PM PDT 24
Finished Aug 11 05:29:02 PM PDT 24
Peak memory 205504 kb
Host smart-fecf4278-4f12-4ac0-91b6-866e9d60324f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779529307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2779529307
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_override.1809518060
Short name T1193
Test name
Test status
Simulation time 37257108 ps
CPU time 0.66 seconds
Started Aug 11 05:28:44 PM PDT 24
Finished Aug 11 05:28:44 PM PDT 24
Peak memory 205252 kb
Host smart-2112f806-a4f1-4e93-ba93-8070ba75d6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809518060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1809518060
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1091514431
Short name T389
Test name
Test status
Simulation time 48465913018 ps
CPU time 503.28 seconds
Started Aug 11 05:28:49 PM PDT 24
Finished Aug 11 05:37:12 PM PDT 24
Peak memory 205552 kb
Host smart-9e9c582d-beb8-4543-b1b9-1364128b6fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091514431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1091514431
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.1182974881
Short name T423
Test name
Test status
Simulation time 234397209 ps
CPU time 4.25 seconds
Started Aug 11 05:28:50 PM PDT 24
Finished Aug 11 05:28:54 PM PDT 24
Peak memory 222988 kb
Host smart-601e05ad-351d-4017-92d1-48d19660aa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182974881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.1182974881
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3667034700
Short name T1114
Test name
Test status
Simulation time 2941403211 ps
CPU time 23.51 seconds
Started Aug 11 05:28:45 PM PDT 24
Finished Aug 11 05:29:08 PM PDT 24
Peak memory 289608 kb
Host smart-22b592fc-7111-40f1-ac53-24e05f83ccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667034700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3667034700
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3493439289
Short name T1385
Test name
Test status
Simulation time 563053896 ps
CPU time 10.05 seconds
Started Aug 11 05:28:49 PM PDT 24
Finished Aug 11 05:28:59 PM PDT 24
Peak memory 213624 kb
Host smart-fbf1db1f-095c-4265-a958-15ab13e280e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493439289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3493439289
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.563892518
Short name T1282
Test name
Test status
Simulation time 941939236 ps
CPU time 4.87 seconds
Started Aug 11 05:28:50 PM PDT 24
Finished Aug 11 05:28:55 PM PDT 24
Peak memory 213804 kb
Host smart-78c91e79-70ad-4673-9c54-71dc7a930fb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563892518 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.563892518
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.61530924
Short name T318
Test name
Test status
Simulation time 1261295227 ps
CPU time 1.11 seconds
Started Aug 11 05:28:50 PM PDT 24
Finished Aug 11 05:28:51 PM PDT 24
Peak memory 205420 kb
Host smart-593799c0-4fc1-474a-92ac-100aa7ddd1e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61530924 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_acq.61530924
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2764160138
Short name T547
Test name
Test status
Simulation time 366720125 ps
CPU time 1.01 seconds
Started Aug 11 05:28:48 PM PDT 24
Finished Aug 11 05:28:49 PM PDT 24
Peak memory 205364 kb
Host smart-062cbc8b-8442-455c-981d-6fe87d722681
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764160138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2764160138
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.2787805600
Short name T627
Test name
Test status
Simulation time 729836377 ps
CPU time 2.26 seconds
Started Aug 11 05:28:57 PM PDT 24
Finished Aug 11 05:28:59 PM PDT 24
Peak memory 205592 kb
Host smart-3ae43d6c-b5f4-4cb6-8fd8-6022909dc857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787805600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.2787805600
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.893964736
Short name T299
Test name
Test status
Simulation time 986397265 ps
CPU time 1.38 seconds
Started Aug 11 05:28:55 PM PDT 24
Finished Aug 11 05:28:56 PM PDT 24
Peak memory 205516 kb
Host smart-1dd98b4e-3838-45e9-9d9b-5a264a24ee75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893964736 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.893964736
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1259183596
Short name T808
Test name
Test status
Simulation time 6058532006 ps
CPU time 5 seconds
Started Aug 11 05:28:49 PM PDT 24
Finished Aug 11 05:28:54 PM PDT 24
Peak memory 216260 kb
Host smart-1748158c-4dde-4c70-87af-ea4132188e6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259183596 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1259183596
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.664949865
Short name T1164
Test name
Test status
Simulation time 11219573992 ps
CPU time 168.4 seconds
Started Aug 11 05:28:50 PM PDT 24
Finished Aug 11 05:31:39 PM PDT 24
Peak memory 2708884 kb
Host smart-8c458409-8b29-43ee-8179-96bcac1e94c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664949865 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.664949865
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_nack_acqfull.2446897203
Short name T580
Test name
Test status
Simulation time 631344363 ps
CPU time 3.21 seconds
Started Aug 11 05:28:58 PM PDT 24
Finished Aug 11 05:29:02 PM PDT 24
Peak memory 213800 kb
Host smart-9a52ffc5-d203-49fb-bed2-6279d5977296
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446897203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_acqfull.2446897203
Directory /workspace/18.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/18.i2c_target_nack_txstretch.2512770330
Short name T1508
Test name
Test status
Simulation time 181652725 ps
CPU time 1.47 seconds
Started Aug 11 05:28:56 PM PDT 24
Finished Aug 11 05:28:58 PM PDT 24
Peak memory 222164 kb
Host smart-96b6052e-44d4-4b65-9bf1-044f4a0b91c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512770330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_nack_txstretch.2512770330
Directory /workspace/18.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/18.i2c_target_perf.1525051373
Short name T1633
Test name
Test status
Simulation time 1642581042 ps
CPU time 3.07 seconds
Started Aug 11 05:28:50 PM PDT 24
Finished Aug 11 05:28:53 PM PDT 24
Peak memory 213944 kb
Host smart-bf57afaf-3436-42e1-b788-64350a8c497b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525051373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.1525051373
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smbus_maxlen.818418148
Short name T319
Test name
Test status
Simulation time 484112631 ps
CPU time 2.11 seconds
Started Aug 11 05:28:56 PM PDT 24
Finished Aug 11 05:28:59 PM PDT 24
Peak memory 205380 kb
Host smart-0266c892-3a7f-490c-8e52-3846def786ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818418148 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_smbus_maxlen.818418148
Directory /workspace/18.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1185102734
Short name T1620
Test name
Test status
Simulation time 4635024923 ps
CPU time 34.98 seconds
Started Aug 11 05:28:50 PM PDT 24
Finished Aug 11 05:29:26 PM PDT 24
Peak memory 213996 kb
Host smart-2f8674bd-2752-42e5-b226-b1667ed99044
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185102734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1185102734
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.2186206259
Short name T938
Test name
Test status
Simulation time 45880497441 ps
CPU time 129.02 seconds
Started Aug 11 05:28:47 PM PDT 24
Finished Aug 11 05:30:57 PM PDT 24
Peak memory 1658892 kb
Host smart-e5cc430a-692c-4484-bc43-2f379effe3d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186206259 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.2186206259
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3425307257
Short name T1492
Test name
Test status
Simulation time 848741713 ps
CPU time 13.96 seconds
Started Aug 11 05:28:48 PM PDT 24
Finished Aug 11 05:29:02 PM PDT 24
Peak memory 221856 kb
Host smart-73fd027c-bfa4-48e5-bb48-859c6e47d167
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425307257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3425307257
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.3064481981
Short name T405
Test name
Test status
Simulation time 40940453102 ps
CPU time 601.54 seconds
Started Aug 11 05:28:51 PM PDT 24
Finished Aug 11 05:38:53 PM PDT 24
Peak memory 5098880 kb
Host smart-368d0a81-1de1-4464-aa35-6fec768dc321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064481981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.3064481981
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2364133359
Short name T931
Test name
Test status
Simulation time 1610251773 ps
CPU time 68.6 seconds
Started Aug 11 05:28:50 PM PDT 24
Finished Aug 11 05:29:58 PM PDT 24
Peak memory 534428 kb
Host smart-369fb51c-f076-40d1-8279-ea7c7d8391dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364133359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2364133359
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3956316211
Short name T839
Test name
Test status
Simulation time 2516120385 ps
CPU time 6.38 seconds
Started Aug 11 05:28:50 PM PDT 24
Finished Aug 11 05:28:57 PM PDT 24
Peak memory 213860 kb
Host smart-b6cbbe32-5deb-45e4-ae8c-55b7f14eb98e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956316211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3956316211
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.3036924380
Short name T1656
Test name
Test status
Simulation time 165062088 ps
CPU time 3.52 seconds
Started Aug 11 05:28:57 PM PDT 24
Finished Aug 11 05:29:01 PM PDT 24
Peak memory 205568 kb
Host smart-35f924ed-8667-4403-9cdb-9df8b95a447f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036924380 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.3036924380
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.2847119126
Short name T1650
Test name
Test status
Simulation time 540418243 ps
CPU time 3.44 seconds
Started Aug 11 05:28:56 PM PDT 24
Finished Aug 11 05:29:00 PM PDT 24
Peak memory 221984 kb
Host smart-52927e64-8aad-46fa-a431-b646902fda0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847119126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.2847119126
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1103744644
Short name T898
Test name
Test status
Simulation time 201619949 ps
CPU time 3.73 seconds
Started Aug 11 05:28:56 PM PDT 24
Finished Aug 11 05:29:00 PM PDT 24
Peak memory 244120 kb
Host smart-8e6e43c6-ed5a-4061-9dfd-b064baad57f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103744644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1103744644
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.847101643
Short name T1093
Test name
Test status
Simulation time 17800820312 ps
CPU time 95.52 seconds
Started Aug 11 05:28:55 PM PDT 24
Finished Aug 11 05:30:31 PM PDT 24
Peak memory 619748 kb
Host smart-c5927725-eaa1-4a32-95c7-49777b2a0fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847101643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.847101643
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.3041137185
Short name T504
Test name
Test status
Simulation time 2885974740 ps
CPU time 36.89 seconds
Started Aug 11 05:28:56 PM PDT 24
Finished Aug 11 05:29:33 PM PDT 24
Peak memory 428592 kb
Host smart-fbca759a-3a57-4b67-82d2-f1ea1660b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041137185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3041137185
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.653101855
Short name T1487
Test name
Test status
Simulation time 120011800 ps
CPU time 1.24 seconds
Started Aug 11 05:28:58 PM PDT 24
Finished Aug 11 05:28:59 PM PDT 24
Peak memory 205388 kb
Host smart-b61736bb-de02-4b75-91f4-079e7abef1f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653101855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fm
t.653101855
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.2977352645
Short name T401
Test name
Test status
Simulation time 736356489 ps
CPU time 10.74 seconds
Started Aug 11 05:28:56 PM PDT 24
Finished Aug 11 05:29:07 PM PDT 24
Peak memory 240472 kb
Host smart-a7126881-9aa4-4891-bb2a-c1a55a14ef50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977352645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.2977352645
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2751552692
Short name T1447
Test name
Test status
Simulation time 15323551918 ps
CPU time 87.72 seconds
Started Aug 11 05:28:55 PM PDT 24
Finished Aug 11 05:30:23 PM PDT 24
Peak memory 1163544 kb
Host smart-c618c990-16bd-4344-b2ab-1d36b4202bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751552692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2751552692
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.725264736
Short name T263
Test name
Test status
Simulation time 828505930 ps
CPU time 6.61 seconds
Started Aug 11 05:29:03 PM PDT 24
Finished Aug 11 05:29:09 PM PDT 24
Peak memory 205528 kb
Host smart-036e2b5a-f473-4d35-984d-c9c254b930aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725264736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.725264736
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.344722668
Short name T733
Test name
Test status
Simulation time 168461513 ps
CPU time 6.46 seconds
Started Aug 11 05:29:02 PM PDT 24
Finished Aug 11 05:29:08 PM PDT 24
Peak memory 222432 kb
Host smart-5156cad9-66ec-4c98-808f-5d18e40c7bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344722668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.344722668
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.2959355898
Short name T356
Test name
Test status
Simulation time 88004236 ps
CPU time 0.66 seconds
Started Aug 11 05:28:54 PM PDT 24
Finished Aug 11 05:28:55 PM PDT 24
Peak memory 205164 kb
Host smart-9bea91a9-fc72-466d-8f6f-f47fc3a1db97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959355898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2959355898
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.3591725911
Short name T1599
Test name
Test status
Simulation time 54424438214 ps
CPU time 275.81 seconds
Started Aug 11 05:28:55 PM PDT 24
Finished Aug 11 05:33:31 PM PDT 24
Peak memory 1335524 kb
Host smart-7e3e55aa-9a77-4ff7-8357-7ff01b622685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591725911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.3591725911
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.2855281437
Short name T86
Test name
Test status
Simulation time 74386832 ps
CPU time 1.96 seconds
Started Aug 11 05:28:55 PM PDT 24
Finished Aug 11 05:28:57 PM PDT 24
Peak memory 205372 kb
Host smart-7266fbbb-be99-4e77-be6f-02ee419f50dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855281437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.2855281437
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1595973833
Short name T1243
Test name
Test status
Simulation time 4782639780 ps
CPU time 19.13 seconds
Started Aug 11 05:28:56 PM PDT 24
Finished Aug 11 05:29:15 PM PDT 24
Peak memory 230120 kb
Host smart-4d2fbdf2-c742-4799-af58-b567801d6884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595973833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1595973833
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2406832509
Short name T1466
Test name
Test status
Simulation time 16399190770 ps
CPU time 693.65 seconds
Started Aug 11 05:28:55 PM PDT 24
Finished Aug 11 05:40:29 PM PDT 24
Peak memory 2851776 kb
Host smart-ce7541b9-0c08-46ca-907c-7c8cb44b3e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406832509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2406832509
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2197232698
Short name T1303
Test name
Test status
Simulation time 2528932528 ps
CPU time 25.6 seconds
Started Aug 11 05:28:54 PM PDT 24
Finished Aug 11 05:29:20 PM PDT 24
Peak memory 213840 kb
Host smart-bfef2d62-335e-4701-ba71-8bf64fe69f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197232698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2197232698
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2025943014
Short name T506
Test name
Test status
Simulation time 834532058 ps
CPU time 4.2 seconds
Started Aug 11 05:29:03 PM PDT 24
Finished Aug 11 05:29:07 PM PDT 24
Peak memory 219356 kb
Host smart-dc162b0a-a7eb-48a5-ab36-5a552937f74f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025943014 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2025943014
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3863077074
Short name T455
Test name
Test status
Simulation time 713633491 ps
CPU time 1.51 seconds
Started Aug 11 05:29:00 PM PDT 24
Finished Aug 11 05:29:02 PM PDT 24
Peak memory 205596 kb
Host smart-fb65cd59-5ee2-4c81-a9e0-582ddb14dde3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863077074 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3863077074
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.473740203
Short name T146
Test name
Test status
Simulation time 200614487 ps
CPU time 0.77 seconds
Started Aug 11 05:29:00 PM PDT 24
Finished Aug 11 05:29:01 PM PDT 24
Peak memory 205396 kb
Host smart-0e328237-ae99-4e2a-b20c-63fbed0c4bf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473740203 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_fifo_reset_tx.473740203
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.440921516
Short name T625
Test name
Test status
Simulation time 2900609477 ps
CPU time 3.25 seconds
Started Aug 11 05:29:01 PM PDT 24
Finished Aug 11 05:29:04 PM PDT 24
Peak memory 205696 kb
Host smart-68920e23-1541-4d48-a165-be4f3616c663
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440921516 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.440921516
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.1109273140
Short name T872
Test name
Test status
Simulation time 748731322 ps
CPU time 1.09 seconds
Started Aug 11 05:29:02 PM PDT 24
Finished Aug 11 05:29:04 PM PDT 24
Peak memory 205340 kb
Host smart-9b90f847-a886-48c5-aab2-8c67cfe5cb60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109273140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.1109273140
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.2902657511
Short name T1505
Test name
Test status
Simulation time 199831167 ps
CPU time 1.75 seconds
Started Aug 11 05:29:01 PM PDT 24
Finished Aug 11 05:29:03 PM PDT 24
Peak memory 213948 kb
Host smart-d909a13f-4dd9-4228-97b1-4132340c96dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902657511 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.2902657511
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2130638812
Short name T1057
Test name
Test status
Simulation time 942986531 ps
CPU time 5.34 seconds
Started Aug 11 05:29:03 PM PDT 24
Finished Aug 11 05:29:08 PM PDT 24
Peak memory 221968 kb
Host smart-42b20dd3-f806-46f7-9a73-14327b31360e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130638812 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2130638812
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2284830841
Short name T1724
Test name
Test status
Simulation time 14816404102 ps
CPU time 26.61 seconds
Started Aug 11 05:29:01 PM PDT 24
Finished Aug 11 05:29:28 PM PDT 24
Peak memory 568344 kb
Host smart-96322298-ac1f-47c2-b5b7-920e64956377
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284830841 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2284830841
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull.197302666
Short name T1546
Test name
Test status
Simulation time 1571729442 ps
CPU time 2.96 seconds
Started Aug 11 05:29:07 PM PDT 24
Finished Aug 11 05:29:10 PM PDT 24
Peak memory 213768 kb
Host smart-914619da-eb9d-435a-a798-9ba8f3b27a35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197302666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_nack_acqfull.197302666
Directory /workspace/19.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/19.i2c_target_nack_acqfull_addr.2765441083
Short name T398
Test name
Test status
Simulation time 870499963 ps
CPU time 2.23 seconds
Started Aug 11 05:29:08 PM PDT 24
Finished Aug 11 05:29:10 PM PDT 24
Peak memory 205584 kb
Host smart-d0d80e65-a5e1-48a8-82bc-ef9bf2146411
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765441083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.2765441083
Directory /workspace/19.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/19.i2c_target_nack_txstretch.2877458949
Short name T1504
Test name
Test status
Simulation time 160458787 ps
CPU time 1.58 seconds
Started Aug 11 05:29:08 PM PDT 24
Finished Aug 11 05:29:10 PM PDT 24
Peak memory 222456 kb
Host smart-5d955511-8d57-449a-8e56-fa7ba7877e32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877458949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_nack_txstretch.2877458949
Directory /workspace/19.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/19.i2c_target_perf.1639462032
Short name T298
Test name
Test status
Simulation time 501942814 ps
CPU time 3.52 seconds
Started Aug 11 05:29:01 PM PDT 24
Finished Aug 11 05:29:05 PM PDT 24
Peak memory 220244 kb
Host smart-610e5ff5-e5ed-40ee-832d-6187ca37b64c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639462032 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.1639462032
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smbus_maxlen.4073413973
Short name T395
Test name
Test status
Simulation time 917131287 ps
CPU time 2.31 seconds
Started Aug 11 05:28:59 PM PDT 24
Finished Aug 11 05:29:01 PM PDT 24
Peak memory 205400 kb
Host smart-9d4c6db9-4c88-45e2-a332-a7d5b8f2d213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073413973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_smbus_maxlen.4073413973
Directory /workspace/19.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.3360257620
Short name T73
Test name
Test status
Simulation time 83199404924 ps
CPU time 30.82 seconds
Started Aug 11 05:29:03 PM PDT 24
Finished Aug 11 05:29:34 PM PDT 24
Peak memory 238768 kb
Host smart-747b18ab-329d-478c-b541-4a953391dca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360257620 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.3360257620
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2383009419
Short name T1518
Test name
Test status
Simulation time 296739456 ps
CPU time 5.06 seconds
Started Aug 11 05:29:01 PM PDT 24
Finished Aug 11 05:29:06 PM PDT 24
Peak memory 205600 kb
Host smart-8162c305-5329-47b2-9192-dc09626e90c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383009419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2383009419
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.3822352319
Short name T1424
Test name
Test status
Simulation time 15831254443 ps
CPU time 5.04 seconds
Started Aug 11 05:28:56 PM PDT 24
Finished Aug 11 05:29:01 PM PDT 24
Peak memory 205720 kb
Host smart-c1b6a46d-792c-4413-b9e0-4da16378f42c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822352319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.3822352319
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.496137259
Short name T822
Test name
Test status
Simulation time 1250093634 ps
CPU time 7.37 seconds
Started Aug 11 05:29:02 PM PDT 24
Finished Aug 11 05:29:09 PM PDT 24
Peak memory 230108 kb
Host smart-bdaa5323-51d7-4808-b966-2233113091f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496137259 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.496137259
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.2771011111
Short name T713
Test name
Test status
Simulation time 592641671 ps
CPU time 8.23 seconds
Started Aug 11 05:29:04 PM PDT 24
Finished Aug 11 05:29:12 PM PDT 24
Peak memory 205688 kb
Host smart-c6808977-b112-4db7-b1e3-7ed3e0c0451f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771011111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.2771011111
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.668804805
Short name T835
Test name
Test status
Simulation time 82888510 ps
CPU time 0.64 seconds
Started Aug 11 05:25:56 PM PDT 24
Finished Aug 11 05:25:56 PM PDT 24
Peak memory 204712 kb
Host smart-0dcd3804-add3-4a55-83d5-c361ce137047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668804805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.668804805
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1714112784
Short name T1259
Test name
Test status
Simulation time 430211614 ps
CPU time 22.69 seconds
Started Aug 11 05:25:42 PM PDT 24
Finished Aug 11 05:26:05 PM PDT 24
Peak memory 298676 kb
Host smart-c7bd29d0-379d-4413-95a8-37d4446a011e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714112784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1714112784
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.807501749
Short name T1606
Test name
Test status
Simulation time 3276950188 ps
CPU time 227.26 seconds
Started Aug 11 05:25:41 PM PDT 24
Finished Aug 11 05:29:29 PM PDT 24
Peak memory 741504 kb
Host smart-98a008d2-b2ba-42fd-ad8f-4a8de09daf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807501749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.807501749
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3763435594
Short name T602
Test name
Test status
Simulation time 5146732812 ps
CPU time 72.53 seconds
Started Aug 11 05:25:43 PM PDT 24
Finished Aug 11 05:26:56 PM PDT 24
Peak memory 675000 kb
Host smart-4f8e3a1a-9c93-4373-b221-e0104bd30255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763435594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3763435594
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2472802575
Short name T29
Test name
Test status
Simulation time 182312281 ps
CPU time 0.88 seconds
Started Aug 11 05:25:41 PM PDT 24
Finished Aug 11 05:25:42 PM PDT 24
Peak memory 205164 kb
Host smart-62d3c859-6a59-4bef-ba67-ed79000a5d5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472802575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2472802575
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3364639853
Short name T616
Test name
Test status
Simulation time 124877489 ps
CPU time 3.22 seconds
Started Aug 11 05:25:42 PM PDT 24
Finished Aug 11 05:25:45 PM PDT 24
Peak memory 205504 kb
Host smart-53c92ddb-d190-4a6c-9f61-72688e58c893
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364639853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3364639853
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.2673038522
Short name T148
Test name
Test status
Simulation time 4643501467 ps
CPU time 293.1 seconds
Started Aug 11 05:25:40 PM PDT 24
Finished Aug 11 05:30:33 PM PDT 24
Peak memory 1166372 kb
Host smart-c786226c-be50-447c-93a8-03f0db053331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673038522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.2673038522
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.451933197
Short name T1640
Test name
Test status
Simulation time 1834994033 ps
CPU time 7.57 seconds
Started Aug 11 05:25:54 PM PDT 24
Finished Aug 11 05:26:02 PM PDT 24
Peak memory 205500 kb
Host smart-b4af5c3a-afc2-41a5-9193-e24bebb95b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451933197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.451933197
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_override.1012529746
Short name T145
Test name
Test status
Simulation time 30639674 ps
CPU time 0.69 seconds
Started Aug 11 05:25:40 PM PDT 24
Finished Aug 11 05:25:41 PM PDT 24
Peak memory 205200 kb
Host smart-aaa9037d-bd15-4c9c-b285-812c73b46d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012529746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1012529746
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.624219895
Short name T1691
Test name
Test status
Simulation time 5996044191 ps
CPU time 40.95 seconds
Started Aug 11 05:25:47 PM PDT 24
Finished Aug 11 05:26:28 PM PDT 24
Peak memory 205524 kb
Host smart-bad044de-e10e-4e05-8604-6e618d476871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624219895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.624219895
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3242753324
Short name T770
Test name
Test status
Simulation time 1840626000 ps
CPU time 69.97 seconds
Started Aug 11 05:25:43 PM PDT 24
Finished Aug 11 05:26:53 PM PDT 24
Peak memory 380508 kb
Host smart-c16bbdba-7291-40c6-969d-b6f2978ee35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242753324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3242753324
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.392672430
Short name T484
Test name
Test status
Simulation time 1245609076 ps
CPU time 7.68 seconds
Started Aug 11 05:25:47 PM PDT 24
Finished Aug 11 05:25:55 PM PDT 24
Peak memory 213764 kb
Host smart-7d45e558-44f1-4d20-9449-86c03f361220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392672430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.392672430
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1888592482
Short name T186
Test name
Test status
Simulation time 36319929 ps
CPU time 0.85 seconds
Started Aug 11 05:25:56 PM PDT 24
Finished Aug 11 05:25:57 PM PDT 24
Peak memory 224064 kb
Host smart-1af9e1ee-b22f-402a-9f1b-1b5f5eac8904
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888592482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1888592482
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2852754193
Short name T1490
Test name
Test status
Simulation time 795330628 ps
CPU time 3.62 seconds
Started Aug 11 05:25:53 PM PDT 24
Finished Aug 11 05:25:57 PM PDT 24
Peak memory 216296 kb
Host smart-bb22b335-6824-4160-8617-03faf55e4f02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852754193 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2852754193
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3964813932
Short name T736
Test name
Test status
Simulation time 170138592 ps
CPU time 1.46 seconds
Started Aug 11 05:25:57 PM PDT 24
Finished Aug 11 05:25:58 PM PDT 24
Peak memory 205576 kb
Host smart-02235a44-ac92-404a-933f-89102e678077
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964813932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3964813932
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3771756835
Short name T1207
Test name
Test status
Simulation time 344926560 ps
CPU time 1.34 seconds
Started Aug 11 05:25:56 PM PDT 24
Finished Aug 11 05:25:57 PM PDT 24
Peak memory 205604 kb
Host smart-50fc56f5-c63f-4ecc-a52c-28d1d74676f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771756835 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3771756835
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.4114453557
Short name T1727
Test name
Test status
Simulation time 359279072 ps
CPU time 2.01 seconds
Started Aug 11 05:25:57 PM PDT 24
Finished Aug 11 05:25:59 PM PDT 24
Peak memory 205420 kb
Host smart-fcdc9aa4-437b-4f4f-96b2-908915eb38c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114453557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.4114453557
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.160701684
Short name T878
Test name
Test status
Simulation time 152552853 ps
CPU time 1.49 seconds
Started Aug 11 05:25:53 PM PDT 24
Finished Aug 11 05:25:54 PM PDT 24
Peak memory 205480 kb
Host smart-d29b2aa5-ce75-4540-bf41-d42eab30aaae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160701684 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.160701684
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1213009786
Short name T404
Test name
Test status
Simulation time 1525808150 ps
CPU time 5.9 seconds
Started Aug 11 05:25:56 PM PDT 24
Finished Aug 11 05:26:02 PM PDT 24
Peak memory 219104 kb
Host smart-45506b30-1083-454a-a7b5-89cc5aa0c32c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213009786 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1213009786
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.4074051841
Short name T1445
Test name
Test status
Simulation time 28882253118 ps
CPU time 957.15 seconds
Started Aug 11 05:25:57 PM PDT 24
Finished Aug 11 05:41:55 PM PDT 24
Peak memory 7070900 kb
Host smart-5f352de4-db24-4fe3-83eb-6de47b3cc565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074051841 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.4074051841
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull.3736024911
Short name T978
Test name
Test status
Simulation time 1744073643 ps
CPU time 2.56 seconds
Started Aug 11 05:25:55 PM PDT 24
Finished Aug 11 05:25:58 PM PDT 24
Peak memory 213816 kb
Host smart-7fbe9391-e257-4dc4-9062-e4b6703153c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736024911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_nack_acqfull.3736024911
Directory /workspace/2.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/2.i2c_target_nack_acqfull_addr.464287709
Short name T1432
Test name
Test status
Simulation time 2257110176 ps
CPU time 2.63 seconds
Started Aug 11 05:25:56 PM PDT 24
Finished Aug 11 05:25:58 PM PDT 24
Peak memory 205732 kb
Host smart-70d9f1c5-3487-4d2a-a7b7-7d61a2f3440c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464287709 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.464287709
Directory /workspace/2.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/2.i2c_target_nack_txstretch.4154909822
Short name T1356
Test name
Test status
Simulation time 581946844 ps
CPU time 1.55 seconds
Started Aug 11 05:25:54 PM PDT 24
Finished Aug 11 05:25:56 PM PDT 24
Peak memory 222352 kb
Host smart-9e2a756b-49ca-403c-a60d-58b3f8ff59a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154909822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_nack_txstretch.4154909822
Directory /workspace/2.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/2.i2c_target_perf.1785029084
Short name T993
Test name
Test status
Simulation time 1653100381 ps
CPU time 6.13 seconds
Started Aug 11 05:25:57 PM PDT 24
Finished Aug 11 05:26:04 PM PDT 24
Peak memory 230604 kb
Host smart-c395f56a-8a63-41da-ab7a-a9a88d0166a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785029084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.1785029084
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smbus_maxlen.48833870
Short name T745
Test name
Test status
Simulation time 531108129 ps
CPU time 2.68 seconds
Started Aug 11 05:25:56 PM PDT 24
Finished Aug 11 05:25:59 PM PDT 24
Peak memory 205336 kb
Host smart-3ed36bbd-4ea9-4314-8e29-18f2a6b7af06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48833870 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.i2c_target_smbus_maxlen.48833870
Directory /workspace/2.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1351016093
Short name T79
Test name
Test status
Simulation time 7879920334 ps
CPU time 12.91 seconds
Started Aug 11 05:25:46 PM PDT 24
Finished Aug 11 05:25:59 PM PDT 24
Peak memory 213984 kb
Host smart-f804998f-9cf7-4262-bf06-8e7a17eba29a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351016093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1351016093
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.3174842683
Short name T58
Test name
Test status
Simulation time 27803474166 ps
CPU time 391.38 seconds
Started Aug 11 05:25:54 PM PDT 24
Finished Aug 11 05:32:25 PM PDT 24
Peak memory 2951252 kb
Host smart-21c4562e-a805-44bc-9a61-82469b21e4fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174842683 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.3174842683
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3199742697
Short name T268
Test name
Test status
Simulation time 4561770411 ps
CPU time 52.7 seconds
Started Aug 11 05:25:48 PM PDT 24
Finished Aug 11 05:26:41 PM PDT 24
Peak memory 215404 kb
Host smart-b3568702-863d-4724-8db1-e3e9b6925973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199742697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3199742697
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.3216409829
Short name T1299
Test name
Test status
Simulation time 46425010909 ps
CPU time 107.3 seconds
Started Aug 11 05:25:47 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 1555108 kb
Host smart-4316c14b-ddfd-4081-83e0-1c6e1efa881f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216409829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.3216409829
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.4088157853
Short name T1249
Test name
Test status
Simulation time 379143967 ps
CPU time 1.25 seconds
Started Aug 11 05:25:55 PM PDT 24
Finished Aug 11 05:25:56 PM PDT 24
Peak memory 205360 kb
Host smart-73dc49ac-cb0c-4872-b460-32bb7b32bd5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088157853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.4088157853
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.3302230400
Short name T1219
Test name
Test status
Simulation time 1300138911 ps
CPU time 6.6 seconds
Started Aug 11 05:25:55 PM PDT 24
Finished Aug 11 05:26:02 PM PDT 24
Peak memory 222024 kb
Host smart-e288d670-0d98-4ee3-a90d-88dc09da7b30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302230400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.3302230400
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.79701246
Short name T407
Test name
Test status
Simulation time 409246202 ps
CPU time 5.75 seconds
Started Aug 11 05:25:57 PM PDT 24
Finished Aug 11 05:26:03 PM PDT 24
Peak memory 205692 kb
Host smart-f798017f-31a6-449c-9a96-bb9d977b8f2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79701246 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.79701246
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.2315279731
Short name T339
Test name
Test status
Simulation time 49225241 ps
CPU time 0.61 seconds
Started Aug 11 05:29:18 PM PDT 24
Finished Aug 11 05:29:19 PM PDT 24
Peak memory 204748 kb
Host smart-d2b90c00-0c5a-4c46-8ad1-bfb1fa74cd77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315279731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2315279731
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.440381926
Short name T1400
Test name
Test status
Simulation time 515351255 ps
CPU time 4.03 seconds
Started Aug 11 05:29:06 PM PDT 24
Finished Aug 11 05:29:11 PM PDT 24
Peak memory 213732 kb
Host smart-d9e78509-2caf-47f7-8add-cacf0cb610af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440381926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.440381926
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2239371836
Short name T1315
Test name
Test status
Simulation time 1598778114 ps
CPU time 8.79 seconds
Started Aug 11 05:29:10 PM PDT 24
Finished Aug 11 05:29:19 PM PDT 24
Peak memory 291660 kb
Host smart-a518d619-fe6a-421d-94b9-b88c8c0265cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239371836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2239371836
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1856271893
Short name T985
Test name
Test status
Simulation time 7950638281 ps
CPU time 59.71 seconds
Started Aug 11 05:29:10 PM PDT 24
Finished Aug 11 05:30:10 PM PDT 24
Peak memory 567880 kb
Host smart-bce14e87-7c1f-4928-9935-24c5887d6b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856271893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1856271893
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.1160772133
Short name T851
Test name
Test status
Simulation time 6358068869 ps
CPU time 60.61 seconds
Started Aug 11 05:29:08 PM PDT 24
Finished Aug 11 05:30:08 PM PDT 24
Peak memory 619504 kb
Host smart-6af06e6d-56ec-4396-ba02-6aa87257b7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160772133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1160772133
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.850739583
Short name T1442
Test name
Test status
Simulation time 98463693 ps
CPU time 1.17 seconds
Started Aug 11 05:29:07 PM PDT 24
Finished Aug 11 05:29:08 PM PDT 24
Peak memory 205288 kb
Host smart-59e24a36-679c-419c-99bd-8b22b683af1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850739583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fm
t.850739583
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2378609704
Short name T569
Test name
Test status
Simulation time 715032628 ps
CPU time 9.19 seconds
Started Aug 11 05:29:08 PM PDT 24
Finished Aug 11 05:29:18 PM PDT 24
Peak memory 205404 kb
Host smart-b6ffb9d5-1b62-4428-83aa-e678c64bf0a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378609704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2378609704
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.3613571054
Short name T754
Test name
Test status
Simulation time 4141561142 ps
CPU time 121.69 seconds
Started Aug 11 05:29:10 PM PDT 24
Finished Aug 11 05:31:12 PM PDT 24
Peak memory 1228792 kb
Host smart-0c1d9d57-e933-464a-af05-d85d8bfdab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613571054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3613571054
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.3717248600
Short name T250
Test name
Test status
Simulation time 1628290067 ps
CPU time 5.43 seconds
Started Aug 11 05:29:14 PM PDT 24
Finished Aug 11 05:29:19 PM PDT 24
Peak memory 205484 kb
Host smart-1b901ccb-519a-4b18-9828-77d158f28542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717248600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3717248600
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_override.304088325
Short name T1574
Test name
Test status
Simulation time 146991914 ps
CPU time 0.67 seconds
Started Aug 11 05:29:11 PM PDT 24
Finished Aug 11 05:29:11 PM PDT 24
Peak memory 205220 kb
Host smart-e77c9763-440e-4cf8-9549-622f0504e174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304088325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.304088325
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.3760113783
Short name T454
Test name
Test status
Simulation time 48861147347 ps
CPU time 522.05 seconds
Started Aug 11 05:29:07 PM PDT 24
Finished Aug 11 05:37:49 PM PDT 24
Peak memory 205564 kb
Host smart-5746f806-15de-4fa0-a833-4b5256307fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760113783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3760113783
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.3183996818
Short name T816
Test name
Test status
Simulation time 103815074 ps
CPU time 1.06 seconds
Started Aug 11 05:29:10 PM PDT 24
Finished Aug 11 05:29:11 PM PDT 24
Peak memory 223176 kb
Host smart-6fa4cfc6-ef16-434f-aa47-b8c23664496f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183996818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.3183996818
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2562984816
Short name T1226
Test name
Test status
Simulation time 2099565004 ps
CPU time 15.21 seconds
Started Aug 11 05:29:06 PM PDT 24
Finished Aug 11 05:29:21 PM PDT 24
Peak memory 270704 kb
Host smart-afecf465-21a7-466f-aacd-c2fe88e43ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562984816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2562984816
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2305202967
Short name T1247
Test name
Test status
Simulation time 2927184447 ps
CPU time 12.37 seconds
Started Aug 11 05:29:09 PM PDT 24
Finished Aug 11 05:29:21 PM PDT 24
Peak memory 216892 kb
Host smart-46b51d9d-b646-4f84-a0b6-b935d13bf428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305202967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2305202967
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.344934301
Short name T1696
Test name
Test status
Simulation time 3021778896 ps
CPU time 7.74 seconds
Started Aug 11 05:29:14 PM PDT 24
Finished Aug 11 05:29:22 PM PDT 24
Peak memory 221012 kb
Host smart-c6b68fd4-d941-4d77-825b-7ba84a4c7dfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344934301 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.344934301
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2469408381
Short name T791
Test name
Test status
Simulation time 226976412 ps
CPU time 1.3 seconds
Started Aug 11 05:29:12 PM PDT 24
Finished Aug 11 05:29:13 PM PDT 24
Peak memory 205640 kb
Host smart-205da4a3-d714-4023-84c8-c666dd5f73ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469408381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2469408381
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2177336414
Short name T4
Test name
Test status
Simulation time 277638112 ps
CPU time 0.88 seconds
Started Aug 11 05:29:13 PM PDT 24
Finished Aug 11 05:29:14 PM PDT 24
Peak memory 205428 kb
Host smart-7e93033a-d40a-44cf-bcb0-050d51072742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177336414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2177336414
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.3636935446
Short name T676
Test name
Test status
Simulation time 2213222048 ps
CPU time 3.03 seconds
Started Aug 11 05:29:14 PM PDT 24
Finished Aug 11 05:29:18 PM PDT 24
Peak memory 205784 kb
Host smart-ca1d9605-718d-43d3-b671-4cc1a52b7c9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636935446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.3636935446
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.1947115237
Short name T595
Test name
Test status
Simulation time 413036903 ps
CPU time 1.13 seconds
Started Aug 11 05:29:12 PM PDT 24
Finished Aug 11 05:29:14 PM PDT 24
Peak memory 205480 kb
Host smart-e035911e-d2ef-443d-a262-04a781a99edc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947115237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.1947115237
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3888264353
Short name T174
Test name
Test status
Simulation time 305947852 ps
CPU time 2.25 seconds
Started Aug 11 05:29:16 PM PDT 24
Finished Aug 11 05:29:18 PM PDT 24
Peak memory 213828 kb
Host smart-692a016f-defb-4708-8bcc-0b55cea19c83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888264353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3888264353
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.48090606
Short name T1297
Test name
Test status
Simulation time 5490763671 ps
CPU time 7.83 seconds
Started Aug 11 05:29:13 PM PDT 24
Finished Aug 11 05:29:21 PM PDT 24
Peak memory 230284 kb
Host smart-d3421351-f435-435a-95a9-dbca1f5c827d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48090606 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.48090606
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.3604867525
Short name T588
Test name
Test status
Simulation time 6514211121 ps
CPU time 64.55 seconds
Started Aug 11 05:29:14 PM PDT 24
Finished Aug 11 05:30:18 PM PDT 24
Peak memory 1690472 kb
Host smart-692baac7-9d9e-4a3d-b8d2-ffe3cf44c54f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604867525 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.3604867525
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull.230880438
Short name T1397
Test name
Test status
Simulation time 476265314 ps
CPU time 3.05 seconds
Started Aug 11 05:29:12 PM PDT 24
Finished Aug 11 05:29:15 PM PDT 24
Peak memory 213808 kb
Host smart-9abbcb7f-8901-48cd-b71c-0f22222acd7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230880438 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_nack_acqfull.230880438
Directory /workspace/20.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/20.i2c_target_nack_acqfull_addr.3922416504
Short name T456
Test name
Test status
Simulation time 525811839 ps
CPU time 2.83 seconds
Started Aug 11 05:29:12 PM PDT 24
Finished Aug 11 05:29:15 PM PDT 24
Peak memory 205532 kb
Host smart-a035ba64-b9ff-4d50-a4e0-2cc4ba014c83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922416504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.3922416504
Directory /workspace/20.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/20.i2c_target_nack_txstretch.1501079648
Short name T167
Test name
Test status
Simulation time 472555748 ps
CPU time 1.38 seconds
Started Aug 11 05:29:19 PM PDT 24
Finished Aug 11 05:29:21 PM PDT 24
Peak memory 222228 kb
Host smart-af532ebc-3a98-4956-939e-4f79aeb538ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501079648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_nack_txstretch.1501079648
Directory /workspace/20.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/20.i2c_target_perf.3762084882
Short name T1051
Test name
Test status
Simulation time 1820416710 ps
CPU time 7.04 seconds
Started Aug 11 05:29:11 PM PDT 24
Finished Aug 11 05:29:19 PM PDT 24
Peak memory 230108 kb
Host smart-d12a50ca-89fc-47b0-95bc-ea853dae1e08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762084882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_perf.3762084882
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smbus_maxlen.453339084
Short name T354
Test name
Test status
Simulation time 1028497597 ps
CPU time 2.58 seconds
Started Aug 11 05:29:13 PM PDT 24
Finished Aug 11 05:29:16 PM PDT 24
Peak memory 204388 kb
Host smart-128adfd4-f8f2-4ee2-8ce6-fcf9ecfe5606
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453339084 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_smbus_maxlen.453339084
Directory /workspace/20.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.2026681638
Short name T357
Test name
Test status
Simulation time 2510944263 ps
CPU time 8.98 seconds
Started Aug 11 05:29:08 PM PDT 24
Finished Aug 11 05:29:17 PM PDT 24
Peak memory 213988 kb
Host smart-eefadae2-98ba-4d97-a02f-dd01d97c1723
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026681638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.2026681638
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.1700470521
Short name T1143
Test name
Test status
Simulation time 217529119630 ps
CPU time 272.17 seconds
Started Aug 11 05:29:13 PM PDT 24
Finished Aug 11 05:33:46 PM PDT 24
Peak memory 1315356 kb
Host smart-7656f861-cd3a-4bad-939f-7948d77cf10e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700470521 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_stress_all.1700470521
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3896058829
Short name T888
Test name
Test status
Simulation time 4815773034 ps
CPU time 29.95 seconds
Started Aug 11 05:29:10 PM PDT 24
Finished Aug 11 05:29:40 PM PDT 24
Peak memory 230816 kb
Host smart-dd4503d9-b863-4e7e-8213-051d0efef921
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896058829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3896058829
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.323077669
Short name T496
Test name
Test status
Simulation time 63439396995 ps
CPU time 798.98 seconds
Started Aug 11 05:29:07 PM PDT 24
Finished Aug 11 05:42:26 PM PDT 24
Peak memory 4981952 kb
Host smart-fb334116-6ed8-4e60-9720-00807a8ed198
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323077669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.323077669
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3295559885
Short name T1258
Test name
Test status
Simulation time 1175213402 ps
CPU time 47.5 seconds
Started Aug 11 05:29:18 PM PDT 24
Finished Aug 11 05:30:06 PM PDT 24
Peak memory 430664 kb
Host smart-4f772f7f-d32a-493a-a13a-996d7f8fbaf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295559885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3295559885
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.3478973572
Short name T1512
Test name
Test status
Simulation time 1050325470 ps
CPU time 6.22 seconds
Started Aug 11 05:29:18 PM PDT 24
Finished Aug 11 05:29:25 PM PDT 24
Peak memory 221968 kb
Host smart-fc7d0b42-d1c5-4813-8348-c00d944c18cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478973572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.3478973572
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.753913939
Short name T1595
Test name
Test status
Simulation time 255161279 ps
CPU time 3.59 seconds
Started Aug 11 05:29:13 PM PDT 24
Finished Aug 11 05:29:16 PM PDT 24
Peak memory 205560 kb
Host smart-dec3372f-758d-458e-af37-ee6bf7b4e34f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753913939 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.753913939
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3652148657
Short name T1653
Test name
Test status
Simulation time 21578298 ps
CPU time 0.69 seconds
Started Aug 11 05:29:31 PM PDT 24
Finished Aug 11 05:29:32 PM PDT 24
Peak memory 204700 kb
Host smart-7885e0da-5522-41b0-8bd3-cd1c23e6f39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652148657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3652148657
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.710081227
Short name T780
Test name
Test status
Simulation time 90392599 ps
CPU time 1.33 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:29:21 PM PDT 24
Peak memory 213760 kb
Host smart-e7dd7610-b835-4731-843b-9536469c0417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710081227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.710081227
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2496540104
Short name T535
Test name
Test status
Simulation time 963277232 ps
CPU time 5.83 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:29:26 PM PDT 24
Peak memory 257524 kb
Host smart-1c1792ca-892c-4d64-be30-a58b996e42d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496540104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2496540104
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1228315859
Short name T464
Test name
Test status
Simulation time 10216869342 ps
CPU time 128.47 seconds
Started Aug 11 05:29:18 PM PDT 24
Finished Aug 11 05:31:27 PM PDT 24
Peak memory 251080 kb
Host smart-9378379e-3f8d-4028-982a-b9ff48dd22a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228315859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1228315859
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1996002873
Short name T561
Test name
Test status
Simulation time 1543388563 ps
CPU time 42.98 seconds
Started Aug 11 05:29:18 PM PDT 24
Finished Aug 11 05:30:01 PM PDT 24
Peak memory 523972 kb
Host smart-a301a35a-a1c6-4244-ab8f-10d1083d427f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996002873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1996002873
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2594941505
Short name T950
Test name
Test status
Simulation time 87607974 ps
CPU time 1.15 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:29:22 PM PDT 24
Peak memory 205228 kb
Host smart-16e41ce0-9e1f-4905-b384-6e35b920afc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594941505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2594941505
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2298894083
Short name T1594
Test name
Test status
Simulation time 177940510 ps
CPU time 8.8 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:29:29 PM PDT 24
Peak memory 205472 kb
Host smart-01a85a1d-ae1a-43d5-a76f-bc93252ca3e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298894083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2298894083
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2701057039
Short name T110
Test name
Test status
Simulation time 5118964715 ps
CPU time 140.04 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:31:40 PM PDT 24
Peak memory 1510140 kb
Host smart-fb8cc638-0de6-4067-91ad-448778529d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701057039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2701057039
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.1810698609
Short name T1733
Test name
Test status
Simulation time 393035443 ps
CPU time 5.5 seconds
Started Aug 11 05:29:25 PM PDT 24
Finished Aug 11 05:29:31 PM PDT 24
Peak memory 205424 kb
Host smart-cdd02068-8a5d-42cf-99fd-1a83ff635918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810698609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.1810698609
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_override.4108586403
Short name T744
Test name
Test status
Simulation time 41416785 ps
CPU time 0.67 seconds
Started Aug 11 05:29:18 PM PDT 24
Finished Aug 11 05:29:19 PM PDT 24
Peak memory 205248 kb
Host smart-78e5f227-bbf0-4514-86b1-87eabb88a3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108586403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.4108586403
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.801432723
Short name T1037
Test name
Test status
Simulation time 27780625791 ps
CPU time 1724.05 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:58:04 PM PDT 24
Peak memory 3915888 kb
Host smart-23f970dc-f711-4942-a0c1-346227bc7878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801432723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.801432723
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.1448938470
Short name T571
Test name
Test status
Simulation time 2604876327 ps
CPU time 27.13 seconds
Started Aug 11 05:29:18 PM PDT 24
Finished Aug 11 05:29:45 PM PDT 24
Peak memory 225404 kb
Host smart-e81ff6fa-ebf8-4ada-977f-0b519cf8e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448938470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.1448938470
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.166863301
Short name T726
Test name
Test status
Simulation time 840552082 ps
CPU time 39.3 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:29:59 PM PDT 24
Peak memory 294752 kb
Host smart-49ca918c-626b-457e-8210-0d7f1057deb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166863301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.166863301
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.3354749206
Short name T367
Test name
Test status
Simulation time 2704101638 ps
CPU time 12.18 seconds
Started Aug 11 05:29:19 PM PDT 24
Finished Aug 11 05:29:31 PM PDT 24
Peak memory 217088 kb
Host smart-08a4181e-8927-4d43-b178-4e6e75029a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354749206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3354749206
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.554374126
Short name T1336
Test name
Test status
Simulation time 1994124439 ps
CPU time 2.83 seconds
Started Aug 11 05:29:28 PM PDT 24
Finished Aug 11 05:29:31 PM PDT 24
Peak memory 213864 kb
Host smart-950249d6-75af-4754-b153-6f644ea6bbbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554374126 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.554374126
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.257655775
Short name T1024
Test name
Test status
Simulation time 143995106 ps
CPU time 0.93 seconds
Started Aug 11 05:29:27 PM PDT 24
Finished Aug 11 05:29:28 PM PDT 24
Peak memory 205416 kb
Host smart-f3d9495d-6bd4-4268-8e69-6206f1861347
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257655775 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.257655775
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1411896106
Short name T911
Test name
Test status
Simulation time 287144192 ps
CPU time 1.61 seconds
Started Aug 11 05:29:26 PM PDT 24
Finished Aug 11 05:29:27 PM PDT 24
Peak memory 211956 kb
Host smart-34025ca5-1c29-4372-a8e0-040d9114fc7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411896106 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1411896106
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.60773795
Short name T678
Test name
Test status
Simulation time 1245446249 ps
CPU time 1.95 seconds
Started Aug 11 05:29:25 PM PDT 24
Finished Aug 11 05:29:27 PM PDT 24
Peak memory 205284 kb
Host smart-4182f202-3542-45b7-ab57-2cf87eb732a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60773795 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.60773795
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.3254345386
Short name T320
Test name
Test status
Simulation time 436022523 ps
CPU time 1.04 seconds
Started Aug 11 05:29:27 PM PDT 24
Finished Aug 11 05:29:28 PM PDT 24
Peak memory 205472 kb
Host smart-ba38fda3-6896-4b95-b84f-d6b51d8821af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254345386 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.3254345386
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.594029474
Short name T698
Test name
Test status
Simulation time 8034723590 ps
CPU time 7.97 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:29:28 PM PDT 24
Peak memory 222164 kb
Host smart-b5819d0e-7923-4aa0-8f0b-5adf5d16d0e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594029474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_intr_smoke.594029474
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1082092811
Short name T337
Test name
Test status
Simulation time 51717792682 ps
CPU time 19.76 seconds
Started Aug 11 05:29:26 PM PDT 24
Finished Aug 11 05:29:46 PM PDT 24
Peak memory 479020 kb
Host smart-345f8c8c-5f7b-4cd3-8813-9449b832a738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082092811 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1082092811
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull.2635502777
Short name T1230
Test name
Test status
Simulation time 1595461747 ps
CPU time 2.85 seconds
Started Aug 11 05:29:31 PM PDT 24
Finished Aug 11 05:29:34 PM PDT 24
Peak memory 213896 kb
Host smart-065fd950-41bd-4a14-8769-1bfda596419b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635502777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_nack_acqfull.2635502777
Directory /workspace/21.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/21.i2c_target_nack_acqfull_addr.1460434679
Short name T660
Test name
Test status
Simulation time 2840739764 ps
CPU time 2.69 seconds
Started Aug 11 05:29:29 PM PDT 24
Finished Aug 11 05:29:32 PM PDT 24
Peak memory 205708 kb
Host smart-36271013-ddb6-432a-9838-1dc52b7f590d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460434679 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.1460434679
Directory /workspace/21.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/21.i2c_target_nack_txstretch.4178680604
Short name T1474
Test name
Test status
Simulation time 253048396 ps
CPU time 1.34 seconds
Started Aug 11 05:29:30 PM PDT 24
Finished Aug 11 05:29:31 PM PDT 24
Peak memory 222516 kb
Host smart-c8c1348c-ca78-451f-8110-3e8a3c2fe864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178680604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_nack_txstretch.4178680604
Directory /workspace/21.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/21.i2c_target_perf.3111931601
Short name T647
Test name
Test status
Simulation time 1981267988 ps
CPU time 3.26 seconds
Started Aug 11 05:29:27 PM PDT 24
Finished Aug 11 05:29:30 PM PDT 24
Peak memory 213820 kb
Host smart-cf4a4115-ecc7-4f55-a038-ca2f6426b6ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111931601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.3111931601
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smbus_maxlen.1496484805
Short name T1036
Test name
Test status
Simulation time 2004219138 ps
CPU time 2.2 seconds
Started Aug 11 05:29:31 PM PDT 24
Finished Aug 11 05:29:34 PM PDT 24
Peak memory 205416 kb
Host smart-f6702d82-49e2-4cc8-9240-68858fc0ab93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496484805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_smbus_maxlen.1496484805
Directory /workspace/21.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1841250710
Short name T1264
Test name
Test status
Simulation time 800880056 ps
CPU time 12.72 seconds
Started Aug 11 05:29:18 PM PDT 24
Finished Aug 11 05:29:31 PM PDT 24
Peak memory 213760 kb
Host smart-9d2aef6b-2a2d-4390-90b7-e92cf65267ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841250710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1841250710
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.2685710381
Short name T1182
Test name
Test status
Simulation time 65095206665 ps
CPU time 202.6 seconds
Started Aug 11 05:29:26 PM PDT 24
Finished Aug 11 05:32:49 PM PDT 24
Peak memory 1359268 kb
Host smart-aa8242a6-0538-480b-ac73-da263dcc3b11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685710381 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_stress_all.2685710381
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.838701430
Short name T1348
Test name
Test status
Simulation time 9229313372 ps
CPU time 74.53 seconds
Started Aug 11 05:29:17 PM PDT 24
Finished Aug 11 05:30:32 PM PDT 24
Peak memory 221028 kb
Host smart-3813b63e-0aca-4884-8376-4d7cad556a31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838701430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.838701430
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.1781700831
Short name T1552
Test name
Test status
Simulation time 24138042040 ps
CPU time 78.74 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:30:39 PM PDT 24
Peak memory 1155456 kb
Host smart-2d72ce4c-8d93-407c-81d9-a5444fa30cba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781700831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.1781700831
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.906270710
Short name T442
Test name
Test status
Simulation time 3059548318 ps
CPU time 42.04 seconds
Started Aug 11 05:29:20 PM PDT 24
Finished Aug 11 05:30:02 PM PDT 24
Peak memory 410092 kb
Host smart-1f670d89-3da8-4a3b-a803-4b2695dc535b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906270710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.906270710
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.1901324085
Short name T742
Test name
Test status
Simulation time 5413186514 ps
CPU time 7.52 seconds
Started Aug 11 05:29:27 PM PDT 24
Finished Aug 11 05:29:34 PM PDT 24
Peak memory 222056 kb
Host smart-b0fe543b-509f-4ccf-9d3e-46eecd1fceb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901324085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.1901324085
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.1815189427
Short name T336
Test name
Test status
Simulation time 364220474 ps
CPU time 4.8 seconds
Started Aug 11 05:29:31 PM PDT 24
Finished Aug 11 05:29:36 PM PDT 24
Peak memory 205616 kb
Host smart-36a12e74-6e4f-4889-bad8-a2a23e6e0cd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815189427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.1815189427
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3494183189
Short name T364
Test name
Test status
Simulation time 21584052 ps
CPU time 0.62 seconds
Started Aug 11 05:29:43 PM PDT 24
Finished Aug 11 05:29:43 PM PDT 24
Peak memory 204720 kb
Host smart-bedf479c-5193-4b4d-9a5a-4a1de4df545b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494183189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3494183189
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1603864085
Short name T859
Test name
Test status
Simulation time 276606026 ps
CPU time 1.52 seconds
Started Aug 11 05:29:35 PM PDT 24
Finished Aug 11 05:29:37 PM PDT 24
Peak memory 213812 kb
Host smart-140898a8-e6ca-4771-9821-7046df56a6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603864085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1603864085
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.2839122979
Short name T1291
Test name
Test status
Simulation time 1510129932 ps
CPU time 8.54 seconds
Started Aug 11 05:29:31 PM PDT 24
Finished Aug 11 05:29:40 PM PDT 24
Peak memory 291620 kb
Host smart-9ecd34a9-97ed-4bdc-a016-ccc28e578dfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839122979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.2839122979
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3425699083
Short name T1103
Test name
Test status
Simulation time 4746308039 ps
CPU time 94.35 seconds
Started Aug 11 05:29:34 PM PDT 24
Finished Aug 11 05:31:08 PM PDT 24
Peak memory 714580 kb
Host smart-a4ea9ea3-2a83-4304-a048-f8a20f27b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425699083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3425699083
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.18417843
Short name T500
Test name
Test status
Simulation time 10264292099 ps
CPU time 134.54 seconds
Started Aug 11 05:29:30 PM PDT 24
Finished Aug 11 05:31:45 PM PDT 24
Peak memory 665328 kb
Host smart-9e547778-c9aa-4efb-9b10-7f38ead4a27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18417843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.18417843
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2549504098
Short name T240
Test name
Test status
Simulation time 136968046 ps
CPU time 1.17 seconds
Started Aug 11 05:29:33 PM PDT 24
Finished Aug 11 05:29:35 PM PDT 24
Peak memory 205196 kb
Host smart-7f1937c0-464b-4767-8ffe-7438da53a457
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549504098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2549504098
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1099872397
Short name T541
Test name
Test status
Simulation time 601886786 ps
CPU time 3.86 seconds
Started Aug 11 05:29:31 PM PDT 24
Finished Aug 11 05:29:35 PM PDT 24
Peak memory 205492 kb
Host smart-33e3221f-498f-40cd-a183-7713f692159d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099872397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1099872397
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2748108319
Short name T1517
Test name
Test status
Simulation time 6155175442 ps
CPU time 134.48 seconds
Started Aug 11 05:29:31 PM PDT 24
Finished Aug 11 05:31:46 PM PDT 24
Peak memory 1587140 kb
Host smart-7fc17d78-08b7-42af-a0be-a64918d8423a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748108319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2748108319
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.2932627828
Short name T247
Test name
Test status
Simulation time 1139501811 ps
CPU time 5.39 seconds
Started Aug 11 05:29:45 PM PDT 24
Finished Aug 11 05:29:51 PM PDT 24
Peak memory 205488 kb
Host smart-d7dc0b38-c1e7-4acf-a21e-42cfe3fa57bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932627828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2932627828
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.5476670
Short name T1342
Test name
Test status
Simulation time 246875374 ps
CPU time 0.91 seconds
Started Aug 11 05:29:38 PM PDT 24
Finished Aug 11 05:29:39 PM PDT 24
Peak memory 204248 kb
Host smart-ee589db3-b454-4175-975f-a1cc04fbc4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5476670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.5476670
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.784824473
Short name T610
Test name
Test status
Simulation time 23066371 ps
CPU time 0.65 seconds
Started Aug 11 05:29:29 PM PDT 24
Finished Aug 11 05:29:30 PM PDT 24
Peak memory 205204 kb
Host smart-7d4ebf13-98b3-4680-af0c-eb5f8782611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784824473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.784824473
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.340524821
Short name T559
Test name
Test status
Simulation time 3713180400 ps
CPU time 30.19 seconds
Started Aug 11 05:29:31 PM PDT 24
Finished Aug 11 05:30:01 PM PDT 24
Peak memory 205892 kb
Host smart-c77c691d-5ac7-4605-a1ae-24eed4ac6622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340524821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.340524821
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.3385754470
Short name T574
Test name
Test status
Simulation time 395161343 ps
CPU time 4.97 seconds
Started Aug 11 05:29:31 PM PDT 24
Finished Aug 11 05:29:36 PM PDT 24
Peak memory 220748 kb
Host smart-a475f020-5d5c-46f1-ae85-405e483577e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385754470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.3385754470
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1325271190
Short name T1007
Test name
Test status
Simulation time 3879985410 ps
CPU time 30.7 seconds
Started Aug 11 05:29:28 PM PDT 24
Finished Aug 11 05:29:59 PM PDT 24
Peak memory 368132 kb
Host smart-edafc0eb-5f75-45c0-af4c-d04a17bc8953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325271190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1325271190
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.619305796
Short name T505
Test name
Test status
Simulation time 755185371 ps
CPU time 11.64 seconds
Started Aug 11 05:29:31 PM PDT 24
Finished Aug 11 05:29:43 PM PDT 24
Peak memory 215356 kb
Host smart-94761e7c-21ab-4b91-bc32-08f01583cc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619305796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.619305796
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.80627918
Short name T927
Test name
Test status
Simulation time 1485134346 ps
CPU time 4.16 seconds
Started Aug 11 05:29:36 PM PDT 24
Finished Aug 11 05:29:40 PM PDT 24
Peak memory 213964 kb
Host smart-0fd064fb-25cd-470d-bc84-5130622aa233
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80627918 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.80627918
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1168224240
Short name T1222
Test name
Test status
Simulation time 194979215 ps
CPU time 1.25 seconds
Started Aug 11 05:29:46 PM PDT 24
Finished Aug 11 05:29:47 PM PDT 24
Peak memory 205640 kb
Host smart-56f2dc79-aa90-450c-a324-e4367807498c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168224240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1168224240
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3836409331
Short name T945
Test name
Test status
Simulation time 185603631 ps
CPU time 0.88 seconds
Started Aug 11 05:29:46 PM PDT 24
Finished Aug 11 05:29:47 PM PDT 24
Peak memory 205428 kb
Host smart-bf5ac961-aba6-420b-93df-6166effc84c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836409331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3836409331
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.3372306637
Short name T1285
Test name
Test status
Simulation time 555788588 ps
CPU time 3.11 seconds
Started Aug 11 05:29:37 PM PDT 24
Finished Aug 11 05:29:41 PM PDT 24
Peak memory 205512 kb
Host smart-2e3cdac7-345a-4817-983d-10b05567390c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372306637 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.3372306637
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.4006410906
Short name T777
Test name
Test status
Simulation time 444911037 ps
CPU time 1.12 seconds
Started Aug 11 05:29:43 PM PDT 24
Finished Aug 11 05:29:44 PM PDT 24
Peak memory 205396 kb
Host smart-73749064-49f5-46e7-8da8-8d678857bb7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006410906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.4006410906
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2121806586
Short name T789
Test name
Test status
Simulation time 1123605842 ps
CPU time 2.59 seconds
Started Aug 11 05:29:38 PM PDT 24
Finished Aug 11 05:29:41 PM PDT 24
Peak memory 212764 kb
Host smart-35b3f82e-a531-432f-b2ef-fbdd8a66d696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121806586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2121806586
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.4120657178
Short name T634
Test name
Test status
Simulation time 866939759 ps
CPU time 5.75 seconds
Started Aug 11 05:29:38 PM PDT 24
Finished Aug 11 05:29:43 PM PDT 24
Peak memory 215772 kb
Host smart-fc1195d4-93b9-48f5-968d-9bc4800c6677
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120657178 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.4120657178
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.3445632624
Short name T1567
Test name
Test status
Simulation time 8074531767 ps
CPU time 20.47 seconds
Started Aug 11 05:29:38 PM PDT 24
Finished Aug 11 05:29:59 PM PDT 24
Peak memory 353264 kb
Host smart-b614b70a-ab7a-463f-b95c-55a0d38583cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445632624 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.3445632624
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull.2475068036
Short name T818
Test name
Test status
Simulation time 590978492 ps
CPU time 3.1 seconds
Started Aug 11 05:29:37 PM PDT 24
Finished Aug 11 05:29:41 PM PDT 24
Peak memory 213872 kb
Host smart-dae602ae-fc36-4f06-bc0c-d8ef2b236bbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475068036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_nack_acqfull.2475068036
Directory /workspace/22.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/22.i2c_target_nack_acqfull_addr.3448466766
Short name T1272
Test name
Test status
Simulation time 850728105 ps
CPU time 2.44 seconds
Started Aug 11 05:29:37 PM PDT 24
Finished Aug 11 05:29:39 PM PDT 24
Peak memory 205592 kb
Host smart-92e0be2a-2118-4122-a70a-d2ec6038c5ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448466766 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_nack_acqfull_addr.3448466766
Directory /workspace/22.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.3922469108
Short name T1634
Test name
Test status
Simulation time 2537403628 ps
CPU time 4.63 seconds
Started Aug 11 05:29:36 PM PDT 24
Finished Aug 11 05:29:41 PM PDT 24
Peak memory 213920 kb
Host smart-f08268ea-1ddc-4277-ad1f-d3d7a31e79b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922469108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.3922469108
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smbus_maxlen.2646484832
Short name T1520
Test name
Test status
Simulation time 903195595 ps
CPU time 2.32 seconds
Started Aug 11 05:29:38 PM PDT 24
Finished Aug 11 05:29:40 PM PDT 24
Peak memory 205360 kb
Host smart-fc89e754-a249-4978-b60c-5959af31e930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646484832 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_smbus_maxlen.2646484832
Directory /workspace/22.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3576756079
Short name T363
Test name
Test status
Simulation time 1573504253 ps
CPU time 22.04 seconds
Started Aug 11 05:29:30 PM PDT 24
Finished Aug 11 05:29:52 PM PDT 24
Peak memory 215472 kb
Host smart-e324860d-c580-46ea-9727-e0920358da73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576756079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3576756079
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.2938378420
Short name T482
Test name
Test status
Simulation time 69364100902 ps
CPU time 218.95 seconds
Started Aug 11 05:29:37 PM PDT 24
Finished Aug 11 05:33:16 PM PDT 24
Peak memory 1644988 kb
Host smart-e6ad162d-a3a5-4d38-b971-8ef8cdc05b26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938378420 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.2938378420
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1925285140
Short name T1545
Test name
Test status
Simulation time 400559925 ps
CPU time 7.21 seconds
Started Aug 11 05:29:33 PM PDT 24
Finished Aug 11 05:29:40 PM PDT 24
Peak memory 205664 kb
Host smart-bd824b53-e051-4fab-82bc-0e907f0b305a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925285140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1925285140
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2384244137
Short name T979
Test name
Test status
Simulation time 48937497958 ps
CPU time 361.93 seconds
Started Aug 11 05:29:30 PM PDT 24
Finished Aug 11 05:35:32 PM PDT 24
Peak memory 3529528 kb
Host smart-bf67b76f-9560-4805-a445-c36565371e4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384244137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2384244137
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.2798045579
Short name T83
Test name
Test status
Simulation time 2242371066 ps
CPU time 17.57 seconds
Started Aug 11 05:29:37 PM PDT 24
Finished Aug 11 05:29:55 PM PDT 24
Peak memory 272320 kb
Host smart-afc3ffe0-71f0-4a42-b25b-e1de75913f21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798045579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.2798045579
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1250721423
Short name T323
Test name
Test status
Simulation time 1184337065 ps
CPU time 6.35 seconds
Started Aug 11 05:29:46 PM PDT 24
Finished Aug 11 05:29:53 PM PDT 24
Peak memory 218520 kb
Host smart-89c97f48-074e-4638-923a-ce9367d291b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250721423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1250721423
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.3175035192
Short name T866
Test name
Test status
Simulation time 131271957 ps
CPU time 2.85 seconds
Started Aug 11 05:29:40 PM PDT 24
Finished Aug 11 05:29:43 PM PDT 24
Peak memory 205696 kb
Host smart-50dab1c8-e433-48fa-b92a-59b3c587873c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175035192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.3175035192
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1447712917
Short name T351
Test name
Test status
Simulation time 16845907 ps
CPU time 0.62 seconds
Started Aug 11 05:29:49 PM PDT 24
Finished Aug 11 05:29:50 PM PDT 24
Peak memory 204764 kb
Host smart-144612db-84b7-4201-9bb3-7f309eac317a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447712917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1447712917
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.1254505710
Short name T1387
Test name
Test status
Simulation time 97663385 ps
CPU time 1.74 seconds
Started Aug 11 05:29:43 PM PDT 24
Finished Aug 11 05:29:45 PM PDT 24
Peak memory 213720 kb
Host smart-49c30076-9095-4e60-986d-ef42b57923be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254505710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1254505710
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.1759970657
Short name T606
Test name
Test status
Simulation time 1715876704 ps
CPU time 9.38 seconds
Started Aug 11 05:29:37 PM PDT 24
Finished Aug 11 05:29:47 PM PDT 24
Peak memory 240404 kb
Host smart-00d8e628-ef94-463d-94d8-adc3d6cc108b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759970657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.1759970657
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.926446898
Short name T566
Test name
Test status
Simulation time 12528728428 ps
CPU time 88.04 seconds
Started Aug 11 05:29:47 PM PDT 24
Finished Aug 11 05:31:15 PM PDT 24
Peak memory 461784 kb
Host smart-a48ad396-a35d-4956-b755-1dc16a5bf897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926446898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.926446898
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2772282136
Short name T1081
Test name
Test status
Simulation time 1303240645 ps
CPU time 33.42 seconds
Started Aug 11 05:29:46 PM PDT 24
Finished Aug 11 05:30:19 PM PDT 24
Peak memory 519464 kb
Host smart-85ed8ffc-7ea6-4a5c-8309-50e54e7ce973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772282136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2772282136
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3121609609
Short name T989
Test name
Test status
Simulation time 466427830 ps
CPU time 1.03 seconds
Started Aug 11 05:29:37 PM PDT 24
Finished Aug 11 05:29:38 PM PDT 24
Peak memory 205144 kb
Host smart-219894e1-8b11-4204-8068-39dd1efaa09d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121609609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3121609609
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1064340858
Short name T237
Test name
Test status
Simulation time 155069281 ps
CPU time 8.23 seconds
Started Aug 11 05:29:44 PM PDT 24
Finished Aug 11 05:29:53 PM PDT 24
Peak memory 205548 kb
Host smart-a3e9b5c3-72b0-47a0-a716-672e1a98add4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064340858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1064340858
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1069860038
Short name T108
Test name
Test status
Simulation time 6789553395 ps
CPU time 78.73 seconds
Started Aug 11 05:29:40 PM PDT 24
Finished Aug 11 05:30:58 PM PDT 24
Peak memory 958068 kb
Host smart-18454dc2-0a2d-4e75-9617-40cc4a824f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069860038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1069860038
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.131194051
Short name T255
Test name
Test status
Simulation time 8010026008 ps
CPU time 8.99 seconds
Started Aug 11 05:29:48 PM PDT 24
Finished Aug 11 05:29:57 PM PDT 24
Peak memory 205652 kb
Host smart-d7c66ff8-a3a3-49a3-a97e-86db1df37322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131194051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.131194051
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.4074174673
Short name T343
Test name
Test status
Simulation time 79013425 ps
CPU time 0.68 seconds
Started Aug 11 05:29:39 PM PDT 24
Finished Aug 11 05:29:40 PM PDT 24
Peak memory 205216 kb
Host smart-ae3420e4-d262-4f3e-93a2-5a42820343df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074174673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.4074174673
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2834937149
Short name T737
Test name
Test status
Simulation time 727394542 ps
CPU time 3.24 seconds
Started Aug 11 05:29:46 PM PDT 24
Finished Aug 11 05:29:49 PM PDT 24
Peak memory 229984 kb
Host smart-89567cbd-2db0-469e-8cff-a1a5619a47ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834937149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2834937149
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.3457504990
Short name T771
Test name
Test status
Simulation time 306390011 ps
CPU time 1.86 seconds
Started Aug 11 05:29:43 PM PDT 24
Finished Aug 11 05:29:45 PM PDT 24
Peak memory 217516 kb
Host smart-8589d62b-690d-4f1b-8b94-5bac68e77592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457504990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.3457504990
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.4255062614
Short name T1711
Test name
Test status
Simulation time 5719610243 ps
CPU time 67.2 seconds
Started Aug 11 05:29:38 PM PDT 24
Finished Aug 11 05:30:45 PM PDT 24
Peak memory 299560 kb
Host smart-ce1b900e-4074-44b8-9e59-fe00962ebbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255062614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.4255062614
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.3250870939
Short name T176
Test name
Test status
Simulation time 24783848258 ps
CPU time 690.59 seconds
Started Aug 11 05:29:43 PM PDT 24
Finished Aug 11 05:41:13 PM PDT 24
Peak memory 2008860 kb
Host smart-82c6dc27-c9f8-4700-a41f-f125bcd61c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250870939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.3250870939
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1739766516
Short name T1418
Test name
Test status
Simulation time 1073240731 ps
CPU time 18.9 seconds
Started Aug 11 05:29:46 PM PDT 24
Finished Aug 11 05:30:05 PM PDT 24
Peak memory 221788 kb
Host smart-e2aa3d88-2093-43d6-9fab-a6c599ca8be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739766516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1739766516
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1310750000
Short name T1689
Test name
Test status
Simulation time 1040733036 ps
CPU time 2.87 seconds
Started Aug 11 05:29:51 PM PDT 24
Finished Aug 11 05:29:54 PM PDT 24
Peak memory 213864 kb
Host smart-ddbb44cd-9c73-4d71-b8f8-247e962daa30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310750000 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1310750000
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3416310444
Short name T920
Test name
Test status
Simulation time 169173092 ps
CPU time 1.25 seconds
Started Aug 11 05:29:44 PM PDT 24
Finished Aug 11 05:29:45 PM PDT 24
Peak memory 205440 kb
Host smart-4fabb3b0-f246-43c4-b1bd-38abe3f15d69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416310444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.3416310444
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.2711901793
Short name T1123
Test name
Test status
Simulation time 436569776 ps
CPU time 0.78 seconds
Started Aug 11 05:29:43 PM PDT 24
Finished Aug 11 05:29:44 PM PDT 24
Peak memory 205396 kb
Host smart-2ac944d2-2b50-4722-bf84-8025cc163222
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711901793 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.2711901793
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.1584555222
Short name T800
Test name
Test status
Simulation time 583668953 ps
CPU time 1.92 seconds
Started Aug 11 05:29:50 PM PDT 24
Finished Aug 11 05:29:52 PM PDT 24
Peak memory 205452 kb
Host smart-f23ef40e-3620-46a7-a997-922203e87b2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584555222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.1584555222
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.702734770
Short name T1392
Test name
Test status
Simulation time 278630735 ps
CPU time 1.46 seconds
Started Aug 11 05:29:49 PM PDT 24
Finished Aug 11 05:29:51 PM PDT 24
Peak memory 205520 kb
Host smart-c516bcd8-05dd-414a-9b9b-fa0aaab05064
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702734770 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.702734770
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.948619999
Short name T684
Test name
Test status
Simulation time 6351832811 ps
CPU time 9.77 seconds
Started Aug 11 05:29:44 PM PDT 24
Finished Aug 11 05:29:54 PM PDT 24
Peak memory 234112 kb
Host smart-5c297deb-3017-452a-816f-75a89104452a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948619999 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.948619999
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.3005838682
Short name T555
Test name
Test status
Simulation time 15906084738 ps
CPU time 9.87 seconds
Started Aug 11 05:29:45 PM PDT 24
Finished Aug 11 05:29:55 PM PDT 24
Peak memory 273564 kb
Host smart-8b6d74ec-fd25-40d5-8a2a-082c279bb262
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005838682 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.3005838682
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_nack_acqfull_addr.3657580742
Short name T1172
Test name
Test status
Simulation time 543928862 ps
CPU time 2.77 seconds
Started Aug 11 05:29:50 PM PDT 24
Finished Aug 11 05:29:52 PM PDT 24
Peak memory 205660 kb
Host smart-964c2ec2-58eb-46e0-a8dd-673462a1afd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657580742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.3657580742
Directory /workspace/23.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.1950271953
Short name T393
Test name
Test status
Simulation time 501256766 ps
CPU time 3.72 seconds
Started Aug 11 05:29:47 PM PDT 24
Finished Aug 11 05:29:51 PM PDT 24
Peak memory 217520 kb
Host smart-85f95dcf-09d1-485b-85c3-6a161d7cba12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950271953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.1950271953
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smbus_maxlen.1351242002
Short name T488
Test name
Test status
Simulation time 541900592 ps
CPU time 2.51 seconds
Started Aug 11 05:29:49 PM PDT 24
Finished Aug 11 05:29:52 PM PDT 24
Peak memory 205412 kb
Host smart-224029ee-c95c-4bfa-8f50-5d0ad9817793
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351242002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_smbus_maxlen.1351242002
Directory /workspace/23.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1792867253
Short name T1618
Test name
Test status
Simulation time 1757407323 ps
CPU time 11.72 seconds
Started Aug 11 05:29:48 PM PDT 24
Finished Aug 11 05:30:00 PM PDT 24
Peak memory 213788 kb
Host smart-4842ab12-c6ec-4804-96bc-91f63de09b57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792867253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.1792867253
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1361887600
Short name T887
Test name
Test status
Simulation time 1105212872 ps
CPU time 48.14 seconds
Started Aug 11 05:29:46 PM PDT 24
Finished Aug 11 05:30:34 PM PDT 24
Peak memory 214260 kb
Host smart-90b9096b-5423-42d4-8d44-a3087d3573ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361887600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1361887600
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2259706265
Short name T523
Test name
Test status
Simulation time 56825945921 ps
CPU time 181.47 seconds
Started Aug 11 05:29:45 PM PDT 24
Finished Aug 11 05:32:47 PM PDT 24
Peak memory 1940600 kb
Host smart-8d31d1c8-ec37-4b3b-a495-f141421d6693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259706265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2259706265
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2102178509
Short name T837
Test name
Test status
Simulation time 6778668485 ps
CPU time 29.1 seconds
Started Aug 11 05:29:44 PM PDT 24
Finished Aug 11 05:30:13 PM PDT 24
Peak memory 950664 kb
Host smart-5560e396-360b-4f46-882d-64e71f6ddc31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102178509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2102178509
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2315123682
Short name T1328
Test name
Test status
Simulation time 13642499585 ps
CPU time 7.08 seconds
Started Aug 11 05:29:43 PM PDT 24
Finished Aug 11 05:29:50 PM PDT 24
Peak memory 219076 kb
Host smart-eac11246-bd59-46b7-94ee-570e9693ed1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315123682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2315123682
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.1365910503
Short name T1203
Test name
Test status
Simulation time 174539156 ps
CPU time 3.93 seconds
Started Aug 11 05:29:49 PM PDT 24
Finished Aug 11 05:29:53 PM PDT 24
Peak memory 205656 kb
Host smart-0d2b4887-3942-4b33-8980-394b1954bcf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365910503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.1365910503
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1067289422
Short name T1451
Test name
Test status
Simulation time 106494343 ps
CPU time 0.63 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:29:56 PM PDT 24
Peak memory 204692 kb
Host smart-765aab57-1b14-4a38-9766-209566f61dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067289422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1067289422
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.283315397
Short name T1026
Test name
Test status
Simulation time 323116955 ps
CPU time 1.31 seconds
Started Aug 11 05:29:50 PM PDT 24
Finished Aug 11 05:29:51 PM PDT 24
Peak memory 222012 kb
Host smart-856a953f-f286-4faa-a16e-2d6dde41fcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283315397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.283315397
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.4040083376
Short name T1224
Test name
Test status
Simulation time 652812918 ps
CPU time 13.85 seconds
Started Aug 11 05:29:49 PM PDT 24
Finished Aug 11 05:30:03 PM PDT 24
Peak memory 263864 kb
Host smart-6366c1f3-3646-4625-a37d-a2612f569322
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040083376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.4040083376
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.806962985
Short name T562
Test name
Test status
Simulation time 5325504543 ps
CPU time 174.01 seconds
Started Aug 11 05:29:48 PM PDT 24
Finished Aug 11 05:32:42 PM PDT 24
Peak memory 594864 kb
Host smart-c20d45af-0553-4a6e-8e5c-0797cea48ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806962985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.806962985
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2588395716
Short name T1065
Test name
Test status
Simulation time 3850630099 ps
CPU time 54.83 seconds
Started Aug 11 05:29:50 PM PDT 24
Finished Aug 11 05:30:45 PM PDT 24
Peak memory 652308 kb
Host smart-2b9a7d37-3d1b-47d5-8150-d67dd94032ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588395716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2588395716
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1370458243
Short name T1364
Test name
Test status
Simulation time 1577976958 ps
CPU time 1.21 seconds
Started Aug 11 05:29:49 PM PDT 24
Finished Aug 11 05:29:50 PM PDT 24
Peak memory 205252 kb
Host smart-72389e26-e00e-4ebe-8bc5-e57d1fb8c9ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370458243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1370458243
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1237009971
Short name T1316
Test name
Test status
Simulation time 1990621638 ps
CPU time 10.75 seconds
Started Aug 11 05:29:49 PM PDT 24
Finished Aug 11 05:30:00 PM PDT 24
Peak memory 205472 kb
Host smart-9db3d516-35f8-469a-879f-2320c9edf0d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237009971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1237009971
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2276665015
Short name T38
Test name
Test status
Simulation time 5072611391 ps
CPU time 130.17 seconds
Started Aug 11 05:29:50 PM PDT 24
Finished Aug 11 05:32:01 PM PDT 24
Peak memory 1385796 kb
Host smart-59f4693e-36ce-4612-b4ff-dcf9f3a9e821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276665015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2276665015
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.3506551684
Short name T1573
Test name
Test status
Simulation time 1450858729 ps
CPU time 4.41 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:30:01 PM PDT 24
Peak memory 205516 kb
Host smart-d1e21627-3176-428d-a054-165f164cbbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506551684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3506551684
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_override.2609014455
Short name T1095
Test name
Test status
Simulation time 48299512 ps
CPU time 0.67 seconds
Started Aug 11 05:29:48 PM PDT 24
Finished Aug 11 05:29:49 PM PDT 24
Peak memory 205168 kb
Host smart-6fe27201-8416-4845-b4b3-175a4f4b697e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609014455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2609014455
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3140840564
Short name T1304
Test name
Test status
Simulation time 1572779887 ps
CPU time 3.67 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:30:00 PM PDT 24
Peak memory 221948 kb
Host smart-dfae34a8-ce0a-4e45-b7ff-3a7bb8b4c019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140840564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3140840564
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.224973778
Short name T120
Test name
Test status
Simulation time 51137877 ps
CPU time 1.38 seconds
Started Aug 11 05:29:50 PM PDT 24
Finished Aug 11 05:29:51 PM PDT 24
Peak memory 226276 kb
Host smart-965e0264-8c08-4944-9862-efde425b1758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224973778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.224973778
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1455651831
Short name T1152
Test name
Test status
Simulation time 1450669443 ps
CPU time 68 seconds
Started Aug 11 05:29:49 PM PDT 24
Finished Aug 11 05:30:57 PM PDT 24
Peak memory 333400 kb
Host smart-5ce22173-8d8c-42cb-9f25-c03629a97cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455651831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1455651831
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.348057146
Short name T7
Test name
Test status
Simulation time 1134063330 ps
CPU time 25.04 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:30:21 PM PDT 24
Peak memory 213708 kb
Host smart-4d2a9494-51dc-4b9c-a7dc-564b7c73ed16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348057146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.348057146
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.4056849481
Short name T1388
Test name
Test status
Simulation time 3295114841 ps
CPU time 5.3 seconds
Started Aug 11 05:29:59 PM PDT 24
Finished Aug 11 05:30:04 PM PDT 24
Peak memory 221724 kb
Host smart-d90f0e03-bcba-4bbf-b578-42702736babd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056849481 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.4056849481
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.2735015922
Short name T702
Test name
Test status
Simulation time 167112299 ps
CPU time 1.14 seconds
Started Aug 11 05:29:55 PM PDT 24
Finished Aug 11 05:29:57 PM PDT 24
Peak memory 205376 kb
Host smart-289cb1d4-c119-4821-8bcb-e474e9c40e19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735015922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.2735015922
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2423291702
Short name T1002
Test name
Test status
Simulation time 714746453 ps
CPU time 1.54 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:29:58 PM PDT 24
Peak memory 210776 kb
Host smart-23adaac4-1762-4de0-a7e9-33c49d4f3a9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423291702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2423291702
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.4195009409
Short name T1622
Test name
Test status
Simulation time 2243642709 ps
CPU time 2.72 seconds
Started Aug 11 05:29:57 PM PDT 24
Finished Aug 11 05:30:00 PM PDT 24
Peak memory 205736 kb
Host smart-43ec7319-7c24-4533-91a2-3480aff76bc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195009409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.4195009409
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.1494283529
Short name T1674
Test name
Test status
Simulation time 123004336 ps
CPU time 1.14 seconds
Started Aug 11 05:29:54 PM PDT 24
Finished Aug 11 05:29:55 PM PDT 24
Peak memory 205372 kb
Host smart-39cccc04-835f-4114-b6de-265360c10ab4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494283529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.1494283529
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.745182755
Short name T739
Test name
Test status
Simulation time 3962674379 ps
CPU time 5.69 seconds
Started Aug 11 05:29:55 PM PDT 24
Finished Aug 11 05:30:01 PM PDT 24
Peak memory 213976 kb
Host smart-f578811b-5f1e-42cc-b5fe-1e952aeb9d43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745182755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.745182755
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.3243638002
Short name T1109
Test name
Test status
Simulation time 15261891688 ps
CPU time 162.84 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:32:39 PM PDT 24
Peak memory 2049356 kb
Host smart-23b2fae3-a0b6-4a6a-829a-a3c317f38769
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243638002 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.3243638002
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull.1675403473
Short name T522
Test name
Test status
Simulation time 428004935 ps
CPU time 2.75 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:29:58 PM PDT 24
Peak memory 213792 kb
Host smart-77205b96-8f5c-4b68-b39f-c4f744541830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675403473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_nack_acqfull.1675403473
Directory /workspace/24.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/24.i2c_target_nack_acqfull_addr.541075497
Short name T552
Test name
Test status
Simulation time 489521765 ps
CPU time 2.48 seconds
Started Aug 11 05:29:59 PM PDT 24
Finished Aug 11 05:30:01 PM PDT 24
Peak memory 205652 kb
Host smart-60c6ac26-233e-4bba-87c3-69578e8cd207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541075497 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.541075497
Directory /workspace/24.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/24.i2c_target_nack_txstretch.3870312061
Short name T919
Test name
Test status
Simulation time 262504795 ps
CPU time 1.57 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:29:58 PM PDT 24
Peak memory 223224 kb
Host smart-ef25ef78-a4c1-4ffb-989b-13a6814da230
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870312061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_nack_txstretch.3870312061
Directory /workspace/24.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/24.i2c_target_perf.1803969499
Short name T654
Test name
Test status
Simulation time 1353331902 ps
CPU time 5.41 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:30:02 PM PDT 24
Peak memory 221984 kb
Host smart-4fe97e14-c4d9-4a1c-aa8f-053877138926
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803969499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.1803969499
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smbus_maxlen.1080811838
Short name T1296
Test name
Test status
Simulation time 619325491 ps
CPU time 2.12 seconds
Started Aug 11 05:29:54 PM PDT 24
Finished Aug 11 05:29:56 PM PDT 24
Peak memory 205340 kb
Host smart-59400d17-52b0-444f-95bf-ced43e413053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080811838 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_smbus_maxlen.1080811838
Directory /workspace/24.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.944201531
Short name T972
Test name
Test status
Simulation time 2194501440 ps
CPU time 8.3 seconds
Started Aug 11 05:29:55 PM PDT 24
Finished Aug 11 05:30:04 PM PDT 24
Peak memory 213956 kb
Host smart-fa17a6b6-93b7-4ce3-9d0c-c3cfabc8a6b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944201531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.944201531
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.3023904681
Short name T152
Test name
Test status
Simulation time 83970896859 ps
CPU time 58.55 seconds
Started Aug 11 05:29:55 PM PDT 24
Finished Aug 11 05:30:54 PM PDT 24
Peak memory 511728 kb
Host smart-4a2f6e88-8bfd-4d2b-a9e2-c8e6b911948f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023904681 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_stress_all.3023904681
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2271167371
Short name T615
Test name
Test status
Simulation time 23828167293 ps
CPU time 26.49 seconds
Started Aug 11 05:29:54 PM PDT 24
Finished Aug 11 05:30:21 PM PDT 24
Peak memory 230804 kb
Host smart-0507ed9e-b9a5-4b7c-8dab-641a6825eb34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271167371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2271167371
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1550303821
Short name T757
Test name
Test status
Simulation time 24517120734 ps
CPU time 14.59 seconds
Started Aug 11 05:29:57 PM PDT 24
Finished Aug 11 05:30:12 PM PDT 24
Peak memory 266296 kb
Host smart-3f27ed5f-559c-4319-9e53-a23335d4172a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550303821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1550303821
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1643202875
Short name T163
Test name
Test status
Simulation time 3652483775 ps
CPU time 191.69 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:33:08 PM PDT 24
Peak memory 1022828 kb
Host smart-b4877cb8-86ac-433b-87d8-53495fc81286
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643202875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1643202875
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2369538887
Short name T1344
Test name
Test status
Simulation time 1387732743 ps
CPU time 7.05 seconds
Started Aug 11 05:29:57 PM PDT 24
Finished Aug 11 05:30:04 PM PDT 24
Peak memory 222064 kb
Host smart-d1b84bf5-d73f-48fa-b56e-3f95ab88879f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369538887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2369538887
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.500294846
Short name T930
Test name
Test status
Simulation time 127644080 ps
CPU time 2.81 seconds
Started Aug 11 05:29:57 PM PDT 24
Finished Aug 11 05:30:00 PM PDT 24
Peak memory 205652 kb
Host smart-e8072cb5-c9d2-49ea-9454-2b2b0054df34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500294846 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.500294846
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1952684999
Short name T1463
Test name
Test status
Simulation time 17160243 ps
CPU time 0.64 seconds
Started Aug 11 05:30:06 PM PDT 24
Finished Aug 11 05:30:07 PM PDT 24
Peak memory 204700 kb
Host smart-63f27db1-c3cc-4738-8e99-d4ce7e8d1408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952684999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1952684999
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.4283526504
Short name T425
Test name
Test status
Simulation time 2872274609 ps
CPU time 3.73 seconds
Started Aug 11 05:30:02 PM PDT 24
Finished Aug 11 05:30:05 PM PDT 24
Peak memory 234540 kb
Host smart-3ecf2c25-ed15-4972-bb2e-ddc66205a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283526504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.4283526504
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.1567874256
Short name T440
Test name
Test status
Simulation time 321367954 ps
CPU time 7.19 seconds
Started Aug 11 05:30:01 PM PDT 24
Finished Aug 11 05:30:08 PM PDT 24
Peak memory 266668 kb
Host smart-ad0f0d74-ab2a-40a9-af94-cc25ed454a2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567874256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.1567874256
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2015209691
Short name T1260
Test name
Test status
Simulation time 5920525540 ps
CPU time 114.8 seconds
Started Aug 11 05:30:01 PM PDT 24
Finished Aug 11 05:31:56 PM PDT 24
Peak memory 729604 kb
Host smart-e460ae13-94e2-4ddd-b696-69bb8f61ffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015209691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2015209691
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3380819759
Short name T490
Test name
Test status
Simulation time 10518512831 ps
CPU time 195.87 seconds
Started Aug 11 05:30:01 PM PDT 24
Finished Aug 11 05:33:17 PM PDT 24
Peak memory 835068 kb
Host smart-01f4d9fc-85b4-41e8-aaa2-f76c347fe080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380819759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3380819759
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2919248932
Short name T369
Test name
Test status
Simulation time 86573766 ps
CPU time 1.06 seconds
Started Aug 11 05:30:02 PM PDT 24
Finished Aug 11 05:30:03 PM PDT 24
Peak memory 205176 kb
Host smart-9c23e1cb-de6e-46e3-948c-d83471db4398
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919248932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2919248932
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3927750331
Short name T1229
Test name
Test status
Simulation time 110796560 ps
CPU time 3.29 seconds
Started Aug 11 05:30:03 PM PDT 24
Finished Aug 11 05:30:06 PM PDT 24
Peak memory 219660 kb
Host smart-6af22dc3-654e-4101-87d6-e6b148f919f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927750331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3927750331
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3847753249
Short name T1462
Test name
Test status
Simulation time 4843042197 ps
CPU time 305.06 seconds
Started Aug 11 05:29:55 PM PDT 24
Finished Aug 11 05:35:00 PM PDT 24
Peak memory 1245744 kb
Host smart-3d2c6b44-df47-4b98-8edb-e8a64fe0624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847753249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3847753249
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.1560651430
Short name T875
Test name
Test status
Simulation time 737295577 ps
CPU time 4.6 seconds
Started Aug 11 05:30:06 PM PDT 24
Finished Aug 11 05:30:11 PM PDT 24
Peak memory 205456 kb
Host smart-673a150b-3998-45b8-8eee-4fce1a0cea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560651430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1560651430
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.1152917187
Short name T1128
Test name
Test status
Simulation time 721153332 ps
CPU time 4.22 seconds
Started Aug 11 05:30:08 PM PDT 24
Finished Aug 11 05:30:12 PM PDT 24
Peak memory 213736 kb
Host smart-3fc00606-fddf-4a94-bd91-4f5a66e33f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152917187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.1152917187
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.1362850970
Short name T564
Test name
Test status
Simulation time 19383021 ps
CPU time 0.65 seconds
Started Aug 11 05:29:55 PM PDT 24
Finished Aug 11 05:29:56 PM PDT 24
Peak memory 205192 kb
Host smart-d22b2f40-de15-47da-96c5-1bd3b5ac9b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362850970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1362850970
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.201935609
Short name T1330
Test name
Test status
Simulation time 3043152441 ps
CPU time 37.87 seconds
Started Aug 11 05:30:01 PM PDT 24
Finished Aug 11 05:30:39 PM PDT 24
Peak memory 543444 kb
Host smart-b482e20f-2b71-43ba-9354-9421aa78a13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201935609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.201935609
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.933623620
Short name T1613
Test name
Test status
Simulation time 599562829 ps
CPU time 7.42 seconds
Started Aug 11 05:30:02 PM PDT 24
Finished Aug 11 05:30:10 PM PDT 24
Peak memory 205460 kb
Host smart-21ac7aee-870d-498e-a142-da80b4bf8367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933623620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.933623620
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3359890439
Short name T1593
Test name
Test status
Simulation time 3761856666 ps
CPU time 27.06 seconds
Started Aug 11 05:29:56 PM PDT 24
Finished Aug 11 05:30:23 PM PDT 24
Peak memory 322164 kb
Host smart-c569cc10-dffd-4183-bf7e-8fd3fa90985d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359890439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3359890439
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2803054763
Short name T17
Test name
Test status
Simulation time 9723684266 ps
CPU time 914.2 seconds
Started Aug 11 05:30:01 PM PDT 24
Finished Aug 11 05:45:16 PM PDT 24
Peak memory 1647448 kb
Host smart-42adf271-03be-47e1-b283-92c599a69988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803054763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2803054763
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.3108434429
Short name T814
Test name
Test status
Simulation time 2521555959 ps
CPU time 28.37 seconds
Started Aug 11 05:30:03 PM PDT 24
Finished Aug 11 05:30:32 PM PDT 24
Peak memory 213792 kb
Host smart-b8508f0d-0e38-454c-be9b-8410f10a1223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108434429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3108434429
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.4166130955
Short name T584
Test name
Test status
Simulation time 1832919547 ps
CPU time 3.67 seconds
Started Aug 11 05:30:06 PM PDT 24
Finished Aug 11 05:30:10 PM PDT 24
Peak memory 216416 kb
Host smart-52341079-01ac-4a45-a518-a8cf71f4b977
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166130955 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.4166130955
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.2893096961
Short name T1352
Test name
Test status
Simulation time 450959156 ps
CPU time 1.4 seconds
Started Aug 11 05:30:07 PM PDT 24
Finished Aug 11 05:30:09 PM PDT 24
Peak memory 205616 kb
Host smart-b657d4a7-1b13-47c3-90ac-00d5be13fa6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893096961 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.2893096961
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2196569362
Short name T1135
Test name
Test status
Simulation time 294585902 ps
CPU time 1.66 seconds
Started Aug 11 05:30:08 PM PDT 24
Finished Aug 11 05:30:10 PM PDT 24
Peak memory 209944 kb
Host smart-4de3beca-1a94-442d-ac36-940ffbf2cf3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196569362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2196569362
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.1422919729
Short name T1131
Test name
Test status
Simulation time 329287227 ps
CPU time 1.91 seconds
Started Aug 11 05:30:08 PM PDT 24
Finished Aug 11 05:30:10 PM PDT 24
Peak memory 205468 kb
Host smart-5b9b92cd-f2c0-4af6-b81a-46516f6f62f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422919729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.1422919729
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.2505525600
Short name T1638
Test name
Test status
Simulation time 1112654068 ps
CPU time 1.49 seconds
Started Aug 11 05:30:07 PM PDT 24
Finished Aug 11 05:30:08 PM PDT 24
Peak memory 205388 kb
Host smart-ede66c65-7a86-4d88-8617-95fcf7b3c2c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505525600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.2505525600
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.1069371726
Short name T969
Test name
Test status
Simulation time 1180657303 ps
CPU time 2.32 seconds
Started Aug 11 05:30:06 PM PDT 24
Finished Aug 11 05:30:09 PM PDT 24
Peak memory 213860 kb
Host smart-cdc2d349-ad9f-4da9-b9ec-872978f5dc76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069371726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.1069371726
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1767940433
Short name T1168
Test name
Test status
Simulation time 2813379437 ps
CPU time 8.48 seconds
Started Aug 11 05:30:02 PM PDT 24
Finished Aug 11 05:30:11 PM PDT 24
Peak memory 223344 kb
Host smart-8a315d3d-1351-4c0e-9a6e-32a669bfbfda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767940433 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1767940433
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1831576948
Short name T273
Test name
Test status
Simulation time 12805569865 ps
CPU time 215.6 seconds
Started Aug 11 05:30:07 PM PDT 24
Finished Aug 11 05:33:43 PM PDT 24
Peak memory 3199300 kb
Host smart-54fcd50e-114f-45d1-960b-de682e2c7c9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831576948 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1831576948
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_acqfull_addr.3463621694
Short name T1355
Test name
Test status
Simulation time 514218224 ps
CPU time 2.57 seconds
Started Aug 11 05:30:08 PM PDT 24
Finished Aug 11 05:30:10 PM PDT 24
Peak memory 205584 kb
Host smart-514e40a5-6d06-4c3f-a02a-1179dac2c182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463621694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_nack_acqfull_addr.3463621694
Directory /workspace/25.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/25.i2c_target_nack_txstretch.625660400
Short name T1423
Test name
Test status
Simulation time 128917585 ps
CPU time 1.3 seconds
Started Aug 11 05:30:08 PM PDT 24
Finished Aug 11 05:30:10 PM PDT 24
Peak memory 222572 kb
Host smart-daac2345-b883-4e64-8335-167b15222fb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625660400 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_nack_txstretch.625660400
Directory /workspace/25.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/25.i2c_target_perf.3266185201
Short name T648
Test name
Test status
Simulation time 2438023761 ps
CPU time 4.43 seconds
Started Aug 11 05:30:08 PM PDT 24
Finished Aug 11 05:30:12 PM PDT 24
Peak memory 222092 kb
Host smart-db35c7c2-2024-497d-86be-7d4c9b52bc30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266185201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.3266185201
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smbus_maxlen.478215914
Short name T621
Test name
Test status
Simulation time 4129431810 ps
CPU time 2.16 seconds
Started Aug 11 05:30:09 PM PDT 24
Finished Aug 11 05:30:11 PM PDT 24
Peak memory 205480 kb
Host smart-bc32ec05-3515-47d9-8abb-87273a5d240e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478215914 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_smbus_maxlen.478215914
Directory /workspace/25.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.3406379181
Short name T1441
Test name
Test status
Simulation time 4060486931 ps
CPU time 26.01 seconds
Started Aug 11 05:30:01 PM PDT 24
Finished Aug 11 05:30:27 PM PDT 24
Peak memory 222144 kb
Host smart-03b9eaf2-c060-4db9-beda-a05ded1dd2a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406379181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.3406379181
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.2716237574
Short name T933
Test name
Test status
Simulation time 51197174605 ps
CPU time 42.12 seconds
Started Aug 11 05:30:08 PM PDT 24
Finished Aug 11 05:30:50 PM PDT 24
Peak memory 335744 kb
Host smart-5d197a5d-8d8e-4a81-b507-258be127efe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716237574 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_stress_all.2716237574
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.381863805
Short name T1003
Test name
Test status
Simulation time 1534457716 ps
CPU time 13.51 seconds
Started Aug 11 05:30:00 PM PDT 24
Finished Aug 11 05:30:14 PM PDT 24
Peak memory 218748 kb
Host smart-0256a5f9-13c3-4b26-8049-8e6dfd1a6b34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381863805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_rd.381863805
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.408800389
Short name T450
Test name
Test status
Simulation time 26300570890 ps
CPU time 48.53 seconds
Started Aug 11 05:30:03 PM PDT 24
Finished Aug 11 05:30:52 PM PDT 24
Peak memory 884388 kb
Host smart-3fb25a35-7eea-43f6-912f-4017cdc1f0f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408800389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_wr.408800389
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3790765624
Short name T1158
Test name
Test status
Simulation time 2573090597 ps
CPU time 7.39 seconds
Started Aug 11 05:30:07 PM PDT 24
Finished Aug 11 05:30:15 PM PDT 24
Peak memory 221420 kb
Host smart-d97cdedf-c074-4fb0-94b7-b4dc863f11ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790765624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3790765624
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.3928369837
Short name T870
Test name
Test status
Simulation time 174612665 ps
CPU time 3.63 seconds
Started Aug 11 05:30:08 PM PDT 24
Finished Aug 11 05:30:11 PM PDT 24
Peak memory 205752 kb
Host smart-8986b0af-7b4e-4623-ae3c-04200e856b11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928369837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.3928369837
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1985447204
Short name T1171
Test name
Test status
Simulation time 16123439 ps
CPU time 0.64 seconds
Started Aug 11 05:30:20 PM PDT 24
Finished Aug 11 05:30:20 PM PDT 24
Peak memory 204816 kb
Host smart-74825509-a220-4d93-ad5c-aa3c873ae298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985447204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1985447204
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1150798217
Short name T904
Test name
Test status
Simulation time 773700839 ps
CPU time 2.22 seconds
Started Aug 11 05:30:15 PM PDT 24
Finished Aug 11 05:30:17 PM PDT 24
Peak memory 221812 kb
Host smart-d5d1efbe-7aaf-4f2e-a699-051cefd0abeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150798217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1150798217
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2320188103
Short name T641
Test name
Test status
Simulation time 4570323763 ps
CPU time 6 seconds
Started Aug 11 05:30:15 PM PDT 24
Finished Aug 11 05:30:21 PM PDT 24
Peak memory 278236 kb
Host smart-6d4391ce-5f42-4b00-ac9e-68fa7ccef382
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320188103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2320188103
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.3367156072
Short name T358
Test name
Test status
Simulation time 26195637565 ps
CPU time 49.37 seconds
Started Aug 11 05:30:15 PM PDT 24
Finished Aug 11 05:31:04 PM PDT 24
Peak memory 388552 kb
Host smart-1c2bf2e0-4623-4dd6-93eb-b5445d9b9dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367156072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3367156072
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3053490378
Short name T380
Test name
Test status
Simulation time 2978212558 ps
CPU time 85.59 seconds
Started Aug 11 05:30:06 PM PDT 24
Finished Aug 11 05:31:32 PM PDT 24
Peak memory 533064 kb
Host smart-cc1f11d2-ecb2-4a61-85f5-be08a63a7e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053490378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3053490378
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1485653255
Short name T467
Test name
Test status
Simulation time 566426732 ps
CPU time 1.08 seconds
Started Aug 11 05:30:13 PM PDT 24
Finished Aug 11 05:30:14 PM PDT 24
Peak memory 205292 kb
Host smart-12f921b8-ca19-4157-881d-c1ff63e29fdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485653255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1485653255
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3671019876
Short name T499
Test name
Test status
Simulation time 164894497 ps
CPU time 8.63 seconds
Started Aug 11 05:30:16 PM PDT 24
Finished Aug 11 05:30:25 PM PDT 24
Peak memory 205520 kb
Host smart-f221e456-06f3-4f65-887a-ad2ad79ba05f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671019876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.3671019876
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3453611281
Short name T883
Test name
Test status
Simulation time 20394012321 ps
CPU time 76.45 seconds
Started Aug 11 05:30:08 PM PDT 24
Finished Aug 11 05:31:25 PM PDT 24
Peak memory 1018744 kb
Host smart-dc8fceda-4fab-408a-aaa4-fa8ac177af81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453611281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3453611281
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.4156988736
Short name T256
Test name
Test status
Simulation time 1996571630 ps
CPU time 21.23 seconds
Started Aug 11 05:30:19 PM PDT 24
Finished Aug 11 05:30:41 PM PDT 24
Peak memory 205600 kb
Host smart-3542a9aa-e08a-4be4-a0e3-13911a71f89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156988736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.4156988736
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.1866123752
Short name T477
Test name
Test status
Simulation time 158398208 ps
CPU time 2.3 seconds
Started Aug 11 05:30:56 PM PDT 24
Finished Aug 11 05:30:58 PM PDT 24
Peak memory 205400 kb
Host smart-fda5cd56-32dc-45d5-90e4-384870aaf647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866123752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.1866123752
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.3898774103
Short name T142
Test name
Test status
Simulation time 53196767 ps
CPU time 0.67 seconds
Started Aug 11 05:30:06 PM PDT 24
Finished Aug 11 05:30:07 PM PDT 24
Peak memory 205128 kb
Host smart-389d4fff-ed60-40a1-8ccc-1c8bf5bb7b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898774103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.3898774103
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.3030423647
Short name T781
Test name
Test status
Simulation time 28875896426 ps
CPU time 253.39 seconds
Started Aug 11 05:30:15 PM PDT 24
Finished Aug 11 05:34:29 PM PDT 24
Peak memory 205596 kb
Host smart-b14b9ccd-ec69-41b4-b9e0-d1440e702110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030423647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3030423647
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.1261233043
Short name T1734
Test name
Test status
Simulation time 71818770 ps
CPU time 3.72 seconds
Started Aug 11 05:30:13 PM PDT 24
Finished Aug 11 05:30:17 PM PDT 24
Peak memory 228824 kb
Host smart-f1c64e0a-acd2-4f00-8542-deedc3a29b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261233043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.1261233043
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1783254253
Short name T1107
Test name
Test status
Simulation time 5726952635 ps
CPU time 72.12 seconds
Started Aug 11 05:30:08 PM PDT 24
Finished Aug 11 05:31:20 PM PDT 24
Peak memory 347668 kb
Host smart-4b39dc7b-8548-4a79-92f6-7fc9127eade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783254253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1783254253
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3908236094
Short name T929
Test name
Test status
Simulation time 822388743 ps
CPU time 32.87 seconds
Started Aug 11 05:30:15 PM PDT 24
Finished Aug 11 05:30:48 PM PDT 24
Peak memory 213712 kb
Host smart-830f77f0-ee3f-4473-a9c9-bb990c65dc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908236094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3908236094
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.629629930
Short name T746
Test name
Test status
Simulation time 1688765507 ps
CPU time 4.7 seconds
Started Aug 11 05:30:15 PM PDT 24
Finished Aug 11 05:30:20 PM PDT 24
Peak memory 215156 kb
Host smart-d771106f-e4d4-4743-810b-d1de4f986fdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629629930 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.629629930
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1206495626
Short name T976
Test name
Test status
Simulation time 257581163 ps
CPU time 1.72 seconds
Started Aug 11 05:30:16 PM PDT 24
Finished Aug 11 05:30:17 PM PDT 24
Peak memory 205908 kb
Host smart-4f4739bc-6367-42e7-a060-9cc72d64c8fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206495626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1206495626
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.229017655
Short name T1359
Test name
Test status
Simulation time 185619419 ps
CPU time 1.25 seconds
Started Aug 11 05:30:13 PM PDT 24
Finished Aug 11 05:30:14 PM PDT 24
Peak memory 205364 kb
Host smart-d42dadc5-e3af-4892-b4ee-118c63de2cb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229017655 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.229017655
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.1842276516
Short name T1212
Test name
Test status
Simulation time 892243022 ps
CPU time 2.45 seconds
Started Aug 11 05:30:22 PM PDT 24
Finished Aug 11 05:30:24 PM PDT 24
Peak memory 205552 kb
Host smart-41c969b0-47ec-497d-86ef-bcabb02822bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842276516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.1842276516
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.2031071562
Short name T1533
Test name
Test status
Simulation time 131815494 ps
CPU time 1.55 seconds
Started Aug 11 05:30:23 PM PDT 24
Finished Aug 11 05:30:24 PM PDT 24
Peak memory 205376 kb
Host smart-a3fd817a-77df-48c1-b5fa-c4613e7f8d79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031071562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.2031071562
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.987547373
Short name T1167
Test name
Test status
Simulation time 420165029 ps
CPU time 1.21 seconds
Started Aug 11 05:30:16 PM PDT 24
Finished Aug 11 05:30:17 PM PDT 24
Peak memory 213880 kb
Host smart-50888f9f-46a2-4c86-801d-4ba96fc992e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987547373 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_hrst.987547373
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.2821891630
Short name T1368
Test name
Test status
Simulation time 2004000940 ps
CPU time 5.88 seconds
Started Aug 11 05:30:12 PM PDT 24
Finished Aug 11 05:30:18 PM PDT 24
Peak memory 214868 kb
Host smart-fafa32b8-09b8-4b53-a14f-f2b351ef1293
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821891630 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.2821891630
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.928786565
Short name T360
Test name
Test status
Simulation time 19372313492 ps
CPU time 149.04 seconds
Started Aug 11 05:30:16 PM PDT 24
Finished Aug 11 05:32:45 PM PDT 24
Peak memory 2252160 kb
Host smart-a24a061d-5cc7-417e-a88a-e1b414bfae92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928786565 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.928786565
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull.3156969585
Short name T55
Test name
Test status
Simulation time 2149719262 ps
CPU time 3.05 seconds
Started Aug 11 05:30:21 PM PDT 24
Finished Aug 11 05:30:25 PM PDT 24
Peak memory 213940 kb
Host smart-34af392d-ad4c-4d30-847f-4c363143bb33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156969585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_nack_acqfull.3156969585
Directory /workspace/26.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/26.i2c_target_nack_acqfull_addr.2133570399
Short name T1160
Test name
Test status
Simulation time 525760677 ps
CPU time 2.53 seconds
Started Aug 11 05:30:18 PM PDT 24
Finished Aug 11 05:30:21 PM PDT 24
Peak memory 206060 kb
Host smart-0e468e11-193c-4476-9017-6374d9a377b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133570399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.2133570399
Directory /workspace/26.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.613558962
Short name T1694
Test name
Test status
Simulation time 3878678081 ps
CPU time 7.5 seconds
Started Aug 11 05:30:14 PM PDT 24
Finished Aug 11 05:30:21 PM PDT 24
Peak memory 222208 kb
Host smart-758aefe6-085c-4a32-8c4b-d56417be33ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613558962 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_perf.613558962
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smbus_maxlen.3919953078
Short name T1337
Test name
Test status
Simulation time 1811937173 ps
CPU time 2.42 seconds
Started Aug 11 05:30:19 PM PDT 24
Finished Aug 11 05:30:21 PM PDT 24
Peak memory 205404 kb
Host smart-175b90b8-5ffe-46a5-8ffc-76a1017b9948
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919953078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_smbus_maxlen.3919953078
Directory /workspace/26.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.3596977185
Short name T77
Test name
Test status
Simulation time 2439110789 ps
CPU time 8.98 seconds
Started Aug 11 05:30:15 PM PDT 24
Finished Aug 11 05:30:24 PM PDT 24
Peak memory 213984 kb
Host smart-f008bda5-dc8f-4bed-ae2d-7488aeee5ace
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596977185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.3596977185
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.3453928155
Short name T130
Test name
Test status
Simulation time 24207623408 ps
CPU time 155.02 seconds
Started Aug 11 05:30:14 PM PDT 24
Finished Aug 11 05:32:50 PM PDT 24
Peak memory 1676940 kb
Host smart-2e76205e-0944-4e78-8729-68c79f4c6133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453928155 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.3453928155
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3296542300
Short name T922
Test name
Test status
Simulation time 1834235048 ps
CPU time 40.2 seconds
Started Aug 11 05:30:14 PM PDT 24
Finished Aug 11 05:30:54 PM PDT 24
Peak memory 213792 kb
Host smart-5de8c7d4-468e-4d7d-b360-99b215ae1a21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296542300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3296542300
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.4242828084
Short name T408
Test name
Test status
Simulation time 35409162322 ps
CPU time 47.03 seconds
Started Aug 11 05:30:16 PM PDT 24
Finished Aug 11 05:31:03 PM PDT 24
Peak memory 971620 kb
Host smart-fafb7fa3-4a1e-4989-a1a7-d758c4ec8e43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242828084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.4242828084
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1929800471
Short name T556
Test name
Test status
Simulation time 4360921734 ps
CPU time 20.15 seconds
Started Aug 11 05:30:16 PM PDT 24
Finished Aug 11 05:30:36 PM PDT 24
Peak memory 436476 kb
Host smart-cd661d9d-18be-4a85-bbea-ff0ba5d5b762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929800471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1929800471
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2463180691
Short name T1673
Test name
Test status
Simulation time 22841118423 ps
CPU time 7.68 seconds
Started Aug 11 05:30:14 PM PDT 24
Finished Aug 11 05:30:21 PM PDT 24
Peak memory 230212 kb
Host smart-c61bb1d3-9c9e-4742-aae4-eab6cfe60307
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463180691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2463180691
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.2053716100
Short name T516
Test name
Test status
Simulation time 310391621 ps
CPU time 4.42 seconds
Started Aug 11 05:30:21 PM PDT 24
Finished Aug 11 05:30:26 PM PDT 24
Peak memory 204576 kb
Host smart-8b06fbfa-599e-4ed4-82d5-b3efbcd42bb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053716100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.2053716100
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2428559947
Short name T85
Test name
Test status
Simulation time 17190583 ps
CPU time 0.62 seconds
Started Aug 11 05:30:24 PM PDT 24
Finished Aug 11 05:30:24 PM PDT 24
Peak memory 204796 kb
Host smart-572473fc-9b7a-41c1-a318-6083e2d9de73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428559947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2428559947
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3725342462
Short name T784
Test name
Test status
Simulation time 207406586 ps
CPU time 2.88 seconds
Started Aug 11 05:30:19 PM PDT 24
Finished Aug 11 05:30:22 PM PDT 24
Peak memory 221152 kb
Host smart-ee567e74-0fe1-4542-a00c-9961a828712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725342462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3725342462
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3214768812
Short name T1090
Test name
Test status
Simulation time 928035192 ps
CPU time 13.47 seconds
Started Aug 11 05:30:22 PM PDT 24
Finished Aug 11 05:30:36 PM PDT 24
Peak memory 259784 kb
Host smart-9aa6e788-534b-40cd-bbe7-e5ede0fa694c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214768812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3214768812
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.882120940
Short name T663
Test name
Test status
Simulation time 3166149471 ps
CPU time 205.91 seconds
Started Aug 11 05:30:19 PM PDT 24
Finished Aug 11 05:33:46 PM PDT 24
Peak memory 585364 kb
Host smart-2600cee1-1b81-4b24-8823-c7d1e62d4b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882120940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.882120940
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.4143219296
Short name T716
Test name
Test status
Simulation time 4088720437 ps
CPU time 73.49 seconds
Started Aug 11 05:30:22 PM PDT 24
Finished Aug 11 05:31:36 PM PDT 24
Peak memory 704448 kb
Host smart-9a54ef9d-62ab-42be-b998-75ac8a752f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143219296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.4143219296
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.4071443292
Short name T462
Test name
Test status
Simulation time 283540579 ps
CPU time 1.07 seconds
Started Aug 11 05:30:21 PM PDT 24
Finished Aug 11 05:30:22 PM PDT 24
Peak memory 205240 kb
Host smart-0ff02560-efd0-4a3e-8b32-13cbe6eb9494
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071443292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.4071443292
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2253653610
Short name T598
Test name
Test status
Simulation time 734056639 ps
CPU time 8.65 seconds
Started Aug 11 05:30:19 PM PDT 24
Finished Aug 11 05:30:28 PM PDT 24
Peak memory 233612 kb
Host smart-7f5ce858-3dca-43bd-8634-52e4c3aad2ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253653610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2253653610
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3431584261
Short name T111
Test name
Test status
Simulation time 17767567676 ps
CPU time 84.27 seconds
Started Aug 11 05:30:22 PM PDT 24
Finished Aug 11 05:31:47 PM PDT 24
Peak memory 1182256 kb
Host smart-1432bf8c-9b8c-4c6a-8317-acf85a02bcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431584261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3431584261
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2033447259
Short name T253
Test name
Test status
Simulation time 277109055 ps
CPU time 3.5 seconds
Started Aug 11 05:30:26 PM PDT 24
Finished Aug 11 05:30:29 PM PDT 24
Peak memory 205508 kb
Host smart-b1a31fe6-f1ab-4d08-bbfd-55b2624ec9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033447259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2033447259
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_override.3805823602
Short name T267
Test name
Test status
Simulation time 25242212 ps
CPU time 0.7 seconds
Started Aug 11 05:30:21 PM PDT 24
Finished Aug 11 05:30:22 PM PDT 24
Peak memory 205144 kb
Host smart-543e6ba4-0cd4-4481-8ef5-b326c9e94c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805823602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3805823602
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.784190625
Short name T39
Test name
Test status
Simulation time 5573767923 ps
CPU time 23.51 seconds
Started Aug 11 05:30:21 PM PDT 24
Finished Aug 11 05:30:45 PM PDT 24
Peak memory 204604 kb
Host smart-5411c6b5-5a31-4271-ad5d-2eccf6b53f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784190625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.784190625
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.2808111133
Short name T847
Test name
Test status
Simulation time 2547334565 ps
CPU time 92.75 seconds
Started Aug 11 05:30:21 PM PDT 24
Finished Aug 11 05:31:54 PM PDT 24
Peak memory 593316 kb
Host smart-1031a598-e1d1-491a-b97d-ee4cc9f43bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808111133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.2808111133
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.4201283403
Short name T1030
Test name
Test status
Simulation time 5581387709 ps
CPU time 73.19 seconds
Started Aug 11 05:30:19 PM PDT 24
Finished Aug 11 05:31:33 PM PDT 24
Peak memory 365764 kb
Host smart-b5651f3c-eada-4016-9f8e-d3534a1b2ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201283403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.4201283403
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.1812287857
Short name T33
Test name
Test status
Simulation time 19509514034 ps
CPU time 2162.36 seconds
Started Aug 11 05:30:22 PM PDT 24
Finished Aug 11 06:06:25 PM PDT 24
Peak memory 3486848 kb
Host smart-2b878e47-d28d-4218-b8be-46cdcb40fab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812287857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.1812287857
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1245024069
Short name T1292
Test name
Test status
Simulation time 2621252956 ps
CPU time 10.85 seconds
Started Aug 11 05:30:18 PM PDT 24
Finished Aug 11 05:30:29 PM PDT 24
Peak memory 221488 kb
Host smart-bc4e4629-c965-4b26-8823-7be42a22eeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245024069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1245024069
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.904583724
Short name T731
Test name
Test status
Simulation time 3099904853 ps
CPU time 4.6 seconds
Started Aug 11 05:30:28 PM PDT 24
Finished Aug 11 05:30:33 PM PDT 24
Peak memory 222208 kb
Host smart-4dbbc372-3595-434e-82db-e031549dcbb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904583724 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.904583724
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.132550103
Short name T558
Test name
Test status
Simulation time 140748298 ps
CPU time 0.94 seconds
Started Aug 11 05:30:26 PM PDT 24
Finished Aug 11 05:30:27 PM PDT 24
Peak memory 205388 kb
Host smart-6d87598f-89f8-4a2e-8681-57160c613c7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132550103 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_acq.132550103
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.1572530084
Short name T649
Test name
Test status
Simulation time 185902964 ps
CPU time 0.88 seconds
Started Aug 11 05:30:28 PM PDT 24
Finished Aug 11 05:30:29 PM PDT 24
Peak memory 213664 kb
Host smart-83c91087-4512-42cd-b4df-df7f9b1b1cb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572530084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.1572530084
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.2967293319
Short name T1473
Test name
Test status
Simulation time 510207085 ps
CPU time 2.65 seconds
Started Aug 11 05:30:27 PM PDT 24
Finished Aug 11 05:30:29 PM PDT 24
Peak memory 205608 kb
Host smart-b5509411-6100-4a7b-abdd-d423646a5af7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967293319 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.2967293319
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.3054633357
Short name T1616
Test name
Test status
Simulation time 148434364 ps
CPU time 1.17 seconds
Started Aug 11 05:30:28 PM PDT 24
Finished Aug 11 05:30:29 PM PDT 24
Peak memory 205412 kb
Host smart-12e1be16-82d0-407a-8a5f-260c4e758ae9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054633357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.3054633357
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3861848156
Short name T1241
Test name
Test status
Simulation time 3716768982 ps
CPU time 6.66 seconds
Started Aug 11 05:30:25 PM PDT 24
Finished Aug 11 05:30:31 PM PDT 24
Peak memory 220424 kb
Host smart-2ae3c951-8b03-4d8c-9b43-ef3d5cb9854f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861848156 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3861848156
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3932519249
Short name T1376
Test name
Test status
Simulation time 9615155411 ps
CPU time 25.49 seconds
Started Aug 11 05:30:24 PM PDT 24
Finished Aug 11 05:30:50 PM PDT 24
Peak memory 597936 kb
Host smart-a8a22d43-cf54-4cab-b1e8-d1b079c8dc19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932519249 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3932519249
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull.2204600838
Short name T762
Test name
Test status
Simulation time 1067675825 ps
CPU time 2.98 seconds
Started Aug 11 05:30:28 PM PDT 24
Finished Aug 11 05:30:31 PM PDT 24
Peak memory 213916 kb
Host smart-b1a25d59-ee8f-45e1-a0df-8dd55584e0ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204600838 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_nack_acqfull.2204600838
Directory /workspace/27.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/27.i2c_target_nack_acqfull_addr.3065077787
Short name T1195
Test name
Test status
Simulation time 1036591596 ps
CPU time 2.78 seconds
Started Aug 11 05:30:28 PM PDT 24
Finished Aug 11 05:30:30 PM PDT 24
Peak memory 205712 kb
Host smart-27d98df2-9afc-491b-94b4-5c96f7870225
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065077787 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.i2c_target_nack_acqfull_addr.3065077787
Directory /workspace/27.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.2367120250
Short name T629
Test name
Test status
Simulation time 2412975414 ps
CPU time 4.61 seconds
Started Aug 11 05:30:27 PM PDT 24
Finished Aug 11 05:30:32 PM PDT 24
Peak memory 214204 kb
Host smart-742eb305-a473-4b29-a683-715769f5e3c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367120250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.2367120250
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smbus_maxlen.2540077017
Short name T982
Test name
Test status
Simulation time 2432078345 ps
CPU time 2.38 seconds
Started Aug 11 05:30:29 PM PDT 24
Finished Aug 11 05:30:31 PM PDT 24
Peak memory 205584 kb
Host smart-5f596964-090a-4235-ba01-5bf1d86bf918
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540077017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_smbus_maxlen.2540077017
Directory /workspace/27.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.1396868450
Short name T352
Test name
Test status
Simulation time 2177833287 ps
CPU time 29.49 seconds
Started Aug 11 05:30:25 PM PDT 24
Finished Aug 11 05:30:55 PM PDT 24
Peak memory 221740 kb
Host smart-99b09580-f0cb-4a01-9522-be7036e42065
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396868450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.1396868450
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.2572840393
Short name T551
Test name
Test status
Simulation time 13850447758 ps
CPU time 56.78 seconds
Started Aug 11 05:30:26 PM PDT 24
Finished Aug 11 05:31:23 PM PDT 24
Peak memory 781900 kb
Host smart-66e17f4c-0567-480e-bb3a-01ad7ec025f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572840393 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.2572840393
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1720740070
Short name T1678
Test name
Test status
Simulation time 13299210392 ps
CPU time 73.3 seconds
Started Aug 11 05:30:25 PM PDT 24
Finished Aug 11 05:31:39 PM PDT 24
Peak memory 217064 kb
Host smart-7bded69a-e74c-47cb-9202-d01539d47c57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720740070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1720740070
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.4271958193
Short name T1235
Test name
Test status
Simulation time 46247149817 ps
CPU time 992.1 seconds
Started Aug 11 05:30:27 PM PDT 24
Finished Aug 11 05:47:00 PM PDT 24
Peak memory 6521252 kb
Host smart-9b381aa0-9b83-4266-bbed-2bb49af8e851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271958193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.4271958193
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3697854005
Short name T328
Test name
Test status
Simulation time 5852069160 ps
CPU time 7.45 seconds
Started Aug 11 05:30:27 PM PDT 24
Finished Aug 11 05:30:34 PM PDT 24
Peak memory 230296 kb
Host smart-3faa1d68-5086-4722-987a-e93b73d8a94d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697854005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3697854005
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.2736673519
Short name T909
Test name
Test status
Simulation time 480072956 ps
CPU time 6.68 seconds
Started Aug 11 05:30:27 PM PDT 24
Finished Aug 11 05:30:34 PM PDT 24
Peak memory 205652 kb
Host smart-1917b628-aba8-41e5-8e60-25571b891980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736673519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.2736673519
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.4241333489
Short name T1536
Test name
Test status
Simulation time 17031187 ps
CPU time 0.68 seconds
Started Aug 11 05:30:41 PM PDT 24
Finished Aug 11 05:30:42 PM PDT 24
Peak memory 205184 kb
Host smart-bdd9e048-3746-4b39-b498-f25d4a7a829a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241333489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.4241333489
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.393411177
Short name T1715
Test name
Test status
Simulation time 865605630 ps
CPU time 1.6 seconds
Started Aug 11 05:30:35 PM PDT 24
Finished Aug 11 05:30:37 PM PDT 24
Peak memory 217076 kb
Host smart-e1f2be89-fced-4f1c-9857-cb7519846f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393411177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.393411177
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.3672103438
Short name T1039
Test name
Test status
Simulation time 1949855562 ps
CPU time 10.67 seconds
Started Aug 11 05:30:39 PM PDT 24
Finished Aug 11 05:30:50 PM PDT 24
Peak memory 311316 kb
Host smart-dbfd523f-a346-42db-b38d-007c778fa384
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672103438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.3672103438
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2261114122
Short name T1097
Test name
Test status
Simulation time 6121493873 ps
CPU time 98.36 seconds
Started Aug 11 05:30:33 PM PDT 24
Finished Aug 11 05:32:11 PM PDT 24
Peak memory 611736 kb
Host smart-3bca9d45-1b1f-4642-988c-9c0b7ec9c1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261114122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2261114122
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.4232367135
Short name T439
Test name
Test status
Simulation time 2223235054 ps
CPU time 70.07 seconds
Started Aug 11 05:30:32 PM PDT 24
Finished Aug 11 05:31:42 PM PDT 24
Peak memory 733376 kb
Host smart-e3c34ce3-b793-415b-859c-190998b08b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232367135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.4232367135
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2949582979
Short name T1378
Test name
Test status
Simulation time 101317914 ps
CPU time 1.25 seconds
Started Aug 11 05:30:35 PM PDT 24
Finished Aug 11 05:30:36 PM PDT 24
Peak memory 205388 kb
Host smart-0b73ef70-6e1f-4fc7-8515-20ca2cab2879
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949582979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2949582979
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.3046070890
Short name T1298
Test name
Test status
Simulation time 752287347 ps
CPU time 4.75 seconds
Started Aug 11 05:30:36 PM PDT 24
Finished Aug 11 05:30:40 PM PDT 24
Peak memory 240572 kb
Host smart-9ff99b1d-ce19-45b7-9350-aa75f745e8ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046070890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.3046070890
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.1669706592
Short name T973
Test name
Test status
Simulation time 21704561602 ps
CPU time 92.83 seconds
Started Aug 11 05:30:32 PM PDT 24
Finished Aug 11 05:32:05 PM PDT 24
Peak memory 995296 kb
Host smart-a5199cc3-9d2c-4d45-957c-3029b93c431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669706592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1669706592
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_override.3353721779
Short name T1124
Test name
Test status
Simulation time 20795803 ps
CPU time 0.69 seconds
Started Aug 11 05:30:33 PM PDT 24
Finished Aug 11 05:30:33 PM PDT 24
Peak memory 205192 kb
Host smart-cc6b04d9-e4cc-4713-83f3-af03d8870a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353721779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3353721779
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.901237637
Short name T1183
Test name
Test status
Simulation time 451838641 ps
CPU time 21.77 seconds
Started Aug 11 05:30:43 PM PDT 24
Finished Aug 11 05:31:05 PM PDT 24
Peak memory 298660 kb
Host smart-36c04305-df06-4db8-9e69-1c66ad706a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901237637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.901237637
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.2398560832
Short name T1319
Test name
Test status
Simulation time 52438590 ps
CPU time 1.32 seconds
Started Aug 11 05:30:33 PM PDT 24
Finished Aug 11 05:30:35 PM PDT 24
Peak memory 229956 kb
Host smart-86f3a206-6ee5-418f-8fab-a73a95748118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398560832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.2398560832
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.2664377278
Short name T27
Test name
Test status
Simulation time 904802808 ps
CPU time 44.26 seconds
Started Aug 11 05:30:30 PM PDT 24
Finished Aug 11 05:31:14 PM PDT 24
Peak memory 335152 kb
Host smart-0c504062-42b0-4026-bc56-6f179777b20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664377278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.2664377278
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.432513981
Short name T1723
Test name
Test status
Simulation time 3888689451 ps
CPU time 33.22 seconds
Started Aug 11 05:30:36 PM PDT 24
Finished Aug 11 05:31:09 PM PDT 24
Peak memory 213976 kb
Host smart-a4b3d3e0-ca95-4dd3-88be-dd754fdb58b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432513981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.432513981
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3014284029
Short name T65
Test name
Test status
Simulation time 2463811995 ps
CPU time 3.71 seconds
Started Aug 11 05:30:39 PM PDT 24
Finished Aug 11 05:30:43 PM PDT 24
Peak memory 219244 kb
Host smart-7e924ae3-069e-4ea7-a9c8-21dc00dd49c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014284029 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3014284029
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.3776170729
Short name T1154
Test name
Test status
Simulation time 455331242 ps
CPU time 1.07 seconds
Started Aug 11 05:30:39 PM PDT 24
Finished Aug 11 05:30:40 PM PDT 24
Peak memory 205472 kb
Host smart-607653d1-f981-4946-a07a-2d1a5312c17e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776170729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.3776170729
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.2120580179
Short name T1605
Test name
Test status
Simulation time 164616838 ps
CPU time 0.91 seconds
Started Aug 11 05:30:40 PM PDT 24
Finished Aug 11 05:30:41 PM PDT 24
Peak memory 205328 kb
Host smart-6ebfce87-2364-41c8-8f69-c4a1cba03b01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120580179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.2120580179
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.3584267874
Short name T334
Test name
Test status
Simulation time 1529771639 ps
CPU time 2.38 seconds
Started Aug 11 05:30:39 PM PDT 24
Finished Aug 11 05:30:41 PM PDT 24
Peak memory 205412 kb
Host smart-f83fe3de-3326-4256-bb7a-b75691589348
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584267874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.3584267874
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.1345497393
Short name T906
Test name
Test status
Simulation time 121402841 ps
CPU time 1.13 seconds
Started Aug 11 05:30:39 PM PDT 24
Finished Aug 11 05:30:41 PM PDT 24
Peak memory 205484 kb
Host smart-df9224e2-b2d2-4835-a61a-719444f283d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345497393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.1345497393
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1870280445
Short name T309
Test name
Test status
Simulation time 599937733 ps
CPU time 4.62 seconds
Started Aug 11 05:30:36 PM PDT 24
Finished Aug 11 05:30:41 PM PDT 24
Peak memory 213776 kb
Host smart-8778b895-2437-43a2-a3c2-6e40f39e200b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870280445 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1870280445
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.3804897835
Short name T1472
Test name
Test status
Simulation time 3792395209 ps
CPU time 1.67 seconds
Started Aug 11 05:30:32 PM PDT 24
Finished Aug 11 05:30:34 PM PDT 24
Peak memory 205720 kb
Host smart-5ef2bdaa-4b16-4e27-8233-f708122315b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804897835 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.3804897835
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull.112112778
Short name T1347
Test name
Test status
Simulation time 1969750945 ps
CPU time 2.98 seconds
Started Aug 11 05:30:38 PM PDT 24
Finished Aug 11 05:30:41 PM PDT 24
Peak memory 213888 kb
Host smart-e4bea0a1-0277-430a-aa31-7907573701e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112112778 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_nack_acqfull.112112778
Directory /workspace/28.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/28.i2c_target_nack_acqfull_addr.2753760412
Short name T1705
Test name
Test status
Simulation time 5917229476 ps
CPU time 2.68 seconds
Started Aug 11 05:30:38 PM PDT 24
Finished Aug 11 05:30:41 PM PDT 24
Peak memory 205576 kb
Host smart-9f33b1a8-9c87-4b50-ac7f-5a3264be6f2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753760412 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.2753760412
Directory /workspace/28.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.2162418097
Short name T797
Test name
Test status
Simulation time 767297015 ps
CPU time 5.55 seconds
Started Aug 11 05:30:38 PM PDT 24
Finished Aug 11 05:30:44 PM PDT 24
Peak memory 221976 kb
Host smart-e7ec2fef-957f-4fe5-b9a2-0f3696d9e578
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162418097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.2162418097
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smbus_maxlen.1166566280
Short name T593
Test name
Test status
Simulation time 1817056199 ps
CPU time 2.2 seconds
Started Aug 11 05:30:42 PM PDT 24
Finished Aug 11 05:30:44 PM PDT 24
Peak memory 205456 kb
Host smart-73446c99-882f-48d0-8aa5-f0b777cd5f53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166566280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_smbus_maxlen.1166566280
Directory /workspace/28.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1713465750
Short name T507
Test name
Test status
Simulation time 675404138 ps
CPU time 11.33 seconds
Started Aug 11 05:30:33 PM PDT 24
Finished Aug 11 05:30:45 PM PDT 24
Peak memory 213752 kb
Host smart-162a55b1-da8b-4822-be40-d4af7d451aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713465750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1713465750
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.214314056
Short name T1704
Test name
Test status
Simulation time 49375238725 ps
CPU time 1159.39 seconds
Started Aug 11 05:30:38 PM PDT 24
Finished Aug 11 05:49:58 PM PDT 24
Peak memory 7170520 kb
Host smart-2c4a4aef-4050-4ea6-bb2e-4377ea43634a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214314056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.i2c_target_stress_all.214314056
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.1575597340
Short name T1144
Test name
Test status
Simulation time 1836131705 ps
CPU time 30.36 seconds
Started Aug 11 05:30:36 PM PDT 24
Finished Aug 11 05:31:06 PM PDT 24
Peak memory 238184 kb
Host smart-da536cf3-f07b-475a-bf7b-be554297a97e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575597340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.1575597340
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.3499042649
Short name T1564
Test name
Test status
Simulation time 47280985350 ps
CPU time 1037.15 seconds
Started Aug 11 05:30:34 PM PDT 24
Finished Aug 11 05:47:51 PM PDT 24
Peak memory 6776068 kb
Host smart-a7aa44fc-333e-4d79-ad2e-84fdfd1569a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499042649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.3499042649
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2601983741
Short name T1562
Test name
Test status
Simulation time 551562486 ps
CPU time 3.87 seconds
Started Aug 11 05:30:33 PM PDT 24
Finished Aug 11 05:30:37 PM PDT 24
Peak memory 238304 kb
Host smart-2c433415-e362-4a3c-86a9-601f45469f43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601983741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2601983741
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1256568071
Short name T1351
Test name
Test status
Simulation time 1526816771 ps
CPU time 7.41 seconds
Started Aug 11 05:30:39 PM PDT 24
Finished Aug 11 05:30:46 PM PDT 24
Peak memory 222008 kb
Host smart-bc66b922-c2ca-4bc0-bd8e-cef389ea83d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256568071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1256568071
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.1639693868
Short name T1680
Test name
Test status
Simulation time 193909313 ps
CPU time 3.1 seconds
Started Aug 11 05:30:37 PM PDT 24
Finished Aug 11 05:30:40 PM PDT 24
Peak memory 205640 kb
Host smart-402fd41d-30dc-452e-961a-d7165290ccfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639693868 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1639693868
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3568777068
Short name T1601
Test name
Test status
Simulation time 24196614 ps
CPU time 0.65 seconds
Started Aug 11 05:30:56 PM PDT 24
Finished Aug 11 05:30:57 PM PDT 24
Peak memory 204720 kb
Host smart-837de8a7-9b8e-421f-8408-e103087947e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568777068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3568777068
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3806747433
Short name T974
Test name
Test status
Simulation time 172125345 ps
CPU time 2.72 seconds
Started Aug 11 05:30:48 PM PDT 24
Finished Aug 11 05:30:51 PM PDT 24
Peak memory 229936 kb
Host smart-eff90dd3-0eb4-4c43-82c8-e8baf21ed071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806747433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3806747433
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2108123645
Short name T327
Test name
Test status
Simulation time 434874248 ps
CPU time 10.88 seconds
Started Aug 11 05:30:49 PM PDT 24
Finished Aug 11 05:31:00 PM PDT 24
Peak memory 248648 kb
Host smart-074c7771-45ca-469d-85ad-d327c0e55f5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108123645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2108123645
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1476501983
Short name T942
Test name
Test status
Simulation time 4553161938 ps
CPU time 127.75 seconds
Started Aug 11 05:30:49 PM PDT 24
Finished Aug 11 05:32:57 PM PDT 24
Peak memory 416516 kb
Host smart-47fed7d2-feba-492f-9d9f-96a0c09c1c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476501983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1476501983
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.517141859
Short name T986
Test name
Test status
Simulation time 3590344192 ps
CPU time 58.14 seconds
Started Aug 11 05:30:38 PM PDT 24
Finished Aug 11 05:31:36 PM PDT 24
Peak memory 607768 kb
Host smart-518e28ec-aa8a-498c-9c65-3f77f0e582d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517141859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.517141859
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3739054391
Short name T1345
Test name
Test status
Simulation time 101851289 ps
CPU time 1.1 seconds
Started Aug 11 05:30:49 PM PDT 24
Finished Aug 11 05:30:50 PM PDT 24
Peak memory 205212 kb
Host smart-1e272d74-dab7-47c7-add6-b6e0b3f2ec8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739054391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3739054391
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.412470642
Short name T1334
Test name
Test status
Simulation time 214967265 ps
CPU time 4.82 seconds
Started Aug 11 05:30:47 PM PDT 24
Finished Aug 11 05:30:52 PM PDT 24
Peak memory 205496 kb
Host smart-a41563ca-3b6b-419d-aa25-33308c2be923
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412470642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
412470642
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.3746016533
Short name T579
Test name
Test status
Simulation time 30509069559 ps
CPU time 354.56 seconds
Started Aug 11 05:30:40 PM PDT 24
Finished Aug 11 05:36:35 PM PDT 24
Peak memory 1350252 kb
Host smart-1482144f-b4b4-431c-a200-325e99c253a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746016533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3746016533
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_override.812030400
Short name T1427
Test name
Test status
Simulation time 17479333 ps
CPU time 0.68 seconds
Started Aug 11 05:30:40 PM PDT 24
Finished Aug 11 05:30:41 PM PDT 24
Peak memory 205160 kb
Host smart-6620f08d-b2de-48e9-896e-6b189eecab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812030400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.812030400
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.4105689088
Short name T1197
Test name
Test status
Simulation time 29632067971 ps
CPU time 1109.32 seconds
Started Aug 11 05:30:50 PM PDT 24
Finished Aug 11 05:49:20 PM PDT 24
Peak memory 205616 kb
Host smart-bba458c3-72b9-4014-beb8-8316bccedcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105689088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.4105689088
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.3937141951
Short name T1670
Test name
Test status
Simulation time 241632977 ps
CPU time 0.91 seconds
Started Aug 11 05:30:49 PM PDT 24
Finished Aug 11 05:30:50 PM PDT 24
Peak memory 205164 kb
Host smart-9ad03102-7ad1-4676-b714-ad722f54aab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937141951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.3937141951
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.243164841
Short name T1365
Test name
Test status
Simulation time 4596649734 ps
CPU time 48.8 seconds
Started Aug 11 05:30:37 PM PDT 24
Finished Aug 11 05:31:26 PM PDT 24
Peak memory 310748 kb
Host smart-e5528c03-fe32-4de7-abfa-e4ef9cee32fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243164841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.243164841
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3931755373
Short name T301
Test name
Test status
Simulation time 760220799 ps
CPU time 35.15 seconds
Started Aug 11 05:30:50 PM PDT 24
Finished Aug 11 05:31:25 PM PDT 24
Peak memory 213660 kb
Host smart-f53de6e1-b11c-4e87-a1bb-2bfd693b1a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931755373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3931755373
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3458417535
Short name T1381
Test name
Test status
Simulation time 1539407589 ps
CPU time 4.45 seconds
Started Aug 11 05:30:53 PM PDT 24
Finished Aug 11 05:30:58 PM PDT 24
Peak memory 219748 kb
Host smart-ea89fa53-42b1-4433-b96c-044e0f9fb468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458417535 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3458417535
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3398097278
Short name T691
Test name
Test status
Simulation time 811361869 ps
CPU time 1.38 seconds
Started Aug 11 05:30:47 PM PDT 24
Finished Aug 11 05:30:48 PM PDT 24
Peak memory 205696 kb
Host smart-5d0eb20c-77d6-4769-8852-eba87aa156f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398097278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3398097278
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3996891857
Short name T783
Test name
Test status
Simulation time 544298124 ps
CPU time 0.9 seconds
Started Aug 11 05:30:50 PM PDT 24
Finished Aug 11 05:30:51 PM PDT 24
Peak memory 205460 kb
Host smart-ade1f8d2-bd63-44b9-9ee9-942f3d7c3c97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996891857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3996891857
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.3221389451
Short name T1354
Test name
Test status
Simulation time 416982011 ps
CPU time 2.4 seconds
Started Aug 11 05:30:53 PM PDT 24
Finished Aug 11 05:30:55 PM PDT 24
Peak memory 205616 kb
Host smart-4b8b7305-559f-4b06-bb50-0958c61076a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221389451 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.3221389451
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.825991762
Short name T815
Test name
Test status
Simulation time 343182864 ps
CPU time 1.02 seconds
Started Aug 11 05:30:49 PM PDT 24
Finished Aug 11 05:30:50 PM PDT 24
Peak memory 205432 kb
Host smart-c8552deb-5dd0-4173-a68e-007cd0aca37f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825991762 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.825991762
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.3076868497
Short name T848
Test name
Test status
Simulation time 1085017057 ps
CPU time 5.95 seconds
Started Aug 11 05:30:48 PM PDT 24
Finished Aug 11 05:30:54 PM PDT 24
Peak memory 222032 kb
Host smart-73b83056-42ad-41ea-bdd6-45bad15d52e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076868497 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.3076868497
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.423874865
Short name T1671
Test name
Test status
Simulation time 10734914375 ps
CPU time 50.78 seconds
Started Aug 11 05:30:47 PM PDT 24
Finished Aug 11 05:31:38 PM PDT 24
Peak memory 1049576 kb
Host smart-726887d4-2f1c-4dd3-99c0-72de7633e600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423874865 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.423874865
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull.3264377799
Short name T1186
Test name
Test status
Simulation time 6130051019 ps
CPU time 2.79 seconds
Started Aug 11 05:30:53 PM PDT 24
Finished Aug 11 05:30:56 PM PDT 24
Peak memory 213880 kb
Host smart-4579ddbb-aa80-4824-8306-6b4e7aa04fd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264377799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_nack_acqfull.3264377799
Directory /workspace/29.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/29.i2c_target_nack_acqfull_addr.230668955
Short name T1210
Test name
Test status
Simulation time 955043288 ps
CPU time 2.63 seconds
Started Aug 11 05:30:49 PM PDT 24
Finished Aug 11 05:30:52 PM PDT 24
Peak memory 205576 kb
Host smart-760add64-c2c6-4df4-8682-f7254fd5695a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230668955 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.230668955
Directory /workspace/29.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.3278526942
Short name T1317
Test name
Test status
Simulation time 1651915384 ps
CPU time 6.13 seconds
Started Aug 11 05:30:50 PM PDT 24
Finished Aug 11 05:30:57 PM PDT 24
Peak memory 230200 kb
Host smart-6f48956b-7083-472e-a6ad-be4c1dcea980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278526942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.3278526942
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smbus_maxlen.1038465658
Short name T262
Test name
Test status
Simulation time 1000654578 ps
CPU time 2.26 seconds
Started Aug 11 05:30:53 PM PDT 24
Finished Aug 11 05:30:55 PM PDT 24
Peak memory 205364 kb
Host smart-4bb61649-1609-40a6-9e75-752f6baae47c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038465658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_smbus_maxlen.1038465658
Directory /workspace/29.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.3332905610
Short name T1279
Test name
Test status
Simulation time 947825496 ps
CPU time 29.29 seconds
Started Aug 11 05:30:48 PM PDT 24
Finished Aug 11 05:31:18 PM PDT 24
Peak memory 222004 kb
Host smart-3f30022e-8c2a-4246-a0dc-dd364a56ca7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332905610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.3332905610
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.2081105821
Short name T1067
Test name
Test status
Simulation time 42400736409 ps
CPU time 103.1 seconds
Started Aug 11 05:30:53 PM PDT 24
Finished Aug 11 05:32:36 PM PDT 24
Peak memory 594780 kb
Host smart-36d582bc-7e0f-4fa2-bac4-e2c08e3e999b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081105821 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.2081105821
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.4174123899
Short name T912
Test name
Test status
Simulation time 3862627610 ps
CPU time 14.76 seconds
Started Aug 11 05:30:49 PM PDT 24
Finished Aug 11 05:31:04 PM PDT 24
Peak memory 219668 kb
Host smart-8274c09a-071d-4bf1-ac7f-809ce61536ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174123899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.4174123899
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.4023508701
Short name T1209
Test name
Test status
Simulation time 43876260924 ps
CPU time 81.17 seconds
Started Aug 11 05:30:47 PM PDT 24
Finished Aug 11 05:32:09 PM PDT 24
Peak memory 1366972 kb
Host smart-46a202ac-a388-482b-ac0b-001775ddd5c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023508701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.4023508701
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.715966636
Short name T498
Test name
Test status
Simulation time 1407307243 ps
CPU time 10.64 seconds
Started Aug 11 05:30:49 PM PDT 24
Finished Aug 11 05:31:00 PM PDT 24
Peak memory 352076 kb
Host smart-2e68b520-bd64-4fbf-9258-a2379a6312c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715966636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_t
arget_stretch.715966636
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.743893285
Short name T793
Test name
Test status
Simulation time 5280615504 ps
CPU time 7.7 seconds
Started Aug 11 05:30:50 PM PDT 24
Finished Aug 11 05:30:58 PM PDT 24
Peak memory 222072 kb
Host smart-57995cba-8ea8-40a1-aea3-5cd658d4cae6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743893285 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.743893285
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.3878252004
Short name T1513
Test name
Test status
Simulation time 106260341 ps
CPU time 2.04 seconds
Started Aug 11 05:30:51 PM PDT 24
Finished Aug 11 05:30:53 PM PDT 24
Peak memory 214748 kb
Host smart-b40181d9-9e86-4839-a9a7-82bafa86cdcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878252004 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.3878252004
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1560446405
Short name T453
Test name
Test status
Simulation time 63574828 ps
CPU time 0.6 seconds
Started Aug 11 05:26:05 PM PDT 24
Finished Aug 11 05:26:06 PM PDT 24
Peak memory 204824 kb
Host smart-a61eb9c8-24da-4938-a46a-7bfa31e23415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560446405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1560446405
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.2941757346
Short name T16
Test name
Test status
Simulation time 448458875 ps
CPU time 3.49 seconds
Started Aug 11 05:25:54 PM PDT 24
Finished Aug 11 05:25:58 PM PDT 24
Peak memory 213740 kb
Host smart-bdf15395-3404-49c5-844c-8273afc93cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941757346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.2941757346
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.864904153
Short name T1548
Test name
Test status
Simulation time 502598674 ps
CPU time 26.14 seconds
Started Aug 11 05:25:56 PM PDT 24
Finished Aug 11 05:26:22 PM PDT 24
Peak memory 316148 kb
Host smart-a4383f84-48fd-4c02-a28a-43974f870fd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864904153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.864904153
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2269769791
Short name T767
Test name
Test status
Simulation time 9500242970 ps
CPU time 127.93 seconds
Started Aug 11 05:25:53 PM PDT 24
Finished Aug 11 05:28:02 PM PDT 24
Peak memory 362336 kb
Host smart-cfc713bd-980d-4ffe-855c-e94511232552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269769791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2269769791
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.3850838050
Short name T956
Test name
Test status
Simulation time 2451248894 ps
CPU time 184.28 seconds
Started Aug 11 05:25:55 PM PDT 24
Finished Aug 11 05:28:59 PM PDT 24
Peak memory 811696 kb
Host smart-08d2056d-5066-44af-a263-45acbd70e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850838050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.3850838050
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.359094522
Short name T1459
Test name
Test status
Simulation time 168352939 ps
CPU time 1.38 seconds
Started Aug 11 05:25:54 PM PDT 24
Finished Aug 11 05:25:55 PM PDT 24
Peak memory 205332 kb
Host smart-f46c9761-ada8-4469-b975-94d386643e34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359094522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt
.359094522
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1889657287
Short name T437
Test name
Test status
Simulation time 525098317 ps
CPU time 3.45 seconds
Started Aug 11 05:25:56 PM PDT 24
Finished Aug 11 05:26:00 PM PDT 24
Peak memory 205488 kb
Host smart-f0e9f2ce-9013-4cca-b09c-2abb7aeebbdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889657287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1889657287
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.567627207
Short name T916
Test name
Test status
Simulation time 4489420001 ps
CPU time 318.27 seconds
Started Aug 11 05:25:53 PM PDT 24
Finished Aug 11 05:31:12 PM PDT 24
Peak memory 1301160 kb
Host smart-0bffb653-0d7b-46ae-8469-d9e8c788fa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567627207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.567627207
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3011283015
Short name T1609
Test name
Test status
Simulation time 1154269834 ps
CPU time 6.9 seconds
Started Aug 11 05:26:03 PM PDT 24
Finished Aug 11 05:26:10 PM PDT 24
Peak memory 205436 kb
Host smart-67100e81-b4c5-44bf-9870-1e91b067933a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011283015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3011283015
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_override.767736033
Short name T1300
Test name
Test status
Simulation time 21972175 ps
CPU time 0.67 seconds
Started Aug 11 05:25:54 PM PDT 24
Finished Aug 11 05:25:54 PM PDT 24
Peak memory 205468 kb
Host smart-afef05fb-f8aa-4f24-8603-6e5fafc2d030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767736033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.767736033
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.2536267989
Short name T1428
Test name
Test status
Simulation time 15141357284 ps
CPU time 63.34 seconds
Started Aug 11 05:25:53 PM PDT 24
Finished Aug 11 05:26:57 PM PDT 24
Peak memory 504612 kb
Host smart-d4bc8728-ac45-4c6c-bde0-82b6e4d1ab3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536267989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2536267989
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.3648176895
Short name T235
Test name
Test status
Simulation time 936908083 ps
CPU time 39.08 seconds
Started Aug 11 05:25:56 PM PDT 24
Finished Aug 11 05:26:36 PM PDT 24
Peak memory 213636 kb
Host smart-5d8c801b-700e-40b5-8036-296191cb0227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648176895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.3648176895
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2567584323
Short name T795
Test name
Test status
Simulation time 8973573680 ps
CPU time 32.14 seconds
Started Aug 11 05:25:53 PM PDT 24
Finished Aug 11 05:26:25 PM PDT 24
Peak memory 302236 kb
Host smart-e6f09354-6927-43d4-b90a-f470a8499856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567584323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2567584323
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3533001974
Short name T1444
Test name
Test status
Simulation time 981030348 ps
CPU time 22.6 seconds
Started Aug 11 05:25:52 PM PDT 24
Finished Aug 11 05:26:15 PM PDT 24
Peak memory 213812 kb
Host smart-b6087ef1-0ea6-4547-8a2b-94c0ee7fae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533001974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3533001974
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.617483089
Short name T183
Test name
Test status
Simulation time 49231084 ps
CPU time 0.86 seconds
Started Aug 11 05:26:09 PM PDT 24
Finished Aug 11 05:26:10 PM PDT 24
Peak memory 223680 kb
Host smart-02b971ff-0749-4145-9f9b-c8004748f63a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617483089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.617483089
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1161002447
Short name T292
Test name
Test status
Simulation time 2360672706 ps
CPU time 4.22 seconds
Started Aug 11 05:26:03 PM PDT 24
Finished Aug 11 05:26:07 PM PDT 24
Peak memory 218828 kb
Host smart-5345267e-c79b-4170-b68b-9811f417b596
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161002447 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1161002447
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3271186455
Short name T1174
Test name
Test status
Simulation time 400039809 ps
CPU time 1.43 seconds
Started Aug 11 05:26:01 PM PDT 24
Finished Aug 11 05:26:03 PM PDT 24
Peak memory 221792 kb
Host smart-7c92b4b2-6a2f-4ae0-8db5-c96f5e6aa6d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271186455 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3271186455
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3059991934
Short name T332
Test name
Test status
Simulation time 238712888 ps
CPU time 1.24 seconds
Started Aug 11 05:26:03 PM PDT 24
Finished Aug 11 05:26:04 PM PDT 24
Peak memory 205544 kb
Host smart-90f34c40-c629-4a40-882e-ecd5d86a7144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059991934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3059991934
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.2001953280
Short name T1106
Test name
Test status
Simulation time 1188082880 ps
CPU time 2.18 seconds
Started Aug 11 05:26:01 PM PDT 24
Finished Aug 11 05:26:04 PM PDT 24
Peak memory 205368 kb
Host smart-190ac2d4-6c77-484b-8eea-196e315146b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001953280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.2001953280
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.2718243176
Short name T1531
Test name
Test status
Simulation time 148820640 ps
CPU time 1.58 seconds
Started Aug 11 05:26:08 PM PDT 24
Finished Aug 11 05:26:10 PM PDT 24
Peak memory 205376 kb
Host smart-47b2dc9d-ef5f-46be-9c82-078cc211d851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718243176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.2718243176
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.3208774417
Short name T1268
Test name
Test status
Simulation time 355924735 ps
CPU time 2.78 seconds
Started Aug 11 05:26:01 PM PDT 24
Finished Aug 11 05:26:04 PM PDT 24
Peak memory 213808 kb
Host smart-e2f5b584-815e-42ab-8bd0-03da970bf031
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208774417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.3208774417
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.86515684
Short name T768
Test name
Test status
Simulation time 1046424646 ps
CPU time 6.59 seconds
Started Aug 11 05:26:01 PM PDT 24
Finished Aug 11 05:26:07 PM PDT 24
Peak memory 213828 kb
Host smart-46367195-b5f2-4827-8775-36a1c773956a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86515684 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_intr_smoke.86515684
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2006681777
Short name T665
Test name
Test status
Simulation time 3663631757 ps
CPU time 4.56 seconds
Started Aug 11 05:25:59 PM PDT 24
Finished Aug 11 05:26:04 PM PDT 24
Peak memory 205712 kb
Host smart-ddcdf85c-d57d-473e-a7a6-01ad70a53ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006681777 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2006681777
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull.44846600
Short name T865
Test name
Test status
Simulation time 1743390644 ps
CPU time 2.92 seconds
Started Aug 11 05:26:00 PM PDT 24
Finished Aug 11 05:26:03 PM PDT 24
Peak memory 213856 kb
Host smart-36e0b210-1f02-4430-b5f1-7f3e717ad45a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44846600 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.i2c_target_nack_acqfull.44846600
Directory /workspace/3.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/3.i2c_target_nack_acqfull_addr.3420304482
Short name T1116
Test name
Test status
Simulation time 1994474716 ps
CPU time 2.78 seconds
Started Aug 11 05:26:00 PM PDT 24
Finished Aug 11 05:26:03 PM PDT 24
Peak memory 205696 kb
Host smart-e38c7b95-3c2d-47df-87bd-46a623e41ef5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420304482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.3420304482
Directory /workspace/3.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.3972371437
Short name T596
Test name
Test status
Simulation time 1493198082 ps
CPU time 6.04 seconds
Started Aug 11 05:26:03 PM PDT 24
Finished Aug 11 05:26:09 PM PDT 24
Peak memory 218200 kb
Host smart-7819390b-7820-4527-8677-1a8cef341cd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972371437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.3972371437
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smbus_maxlen.4058683293
Short name T796
Test name
Test status
Simulation time 423287037 ps
CPU time 2.15 seconds
Started Aug 11 05:26:02 PM PDT 24
Finished Aug 11 05:26:04 PM PDT 24
Peak memory 205352 kb
Host smart-d7208c2b-95d3-4871-a953-757da06db372
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058683293 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_smbus_maxlen.4058683293
Directory /workspace/3.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1541730316
Short name T487
Test name
Test status
Simulation time 1113374848 ps
CPU time 34.11 seconds
Started Aug 11 05:26:07 PM PDT 24
Finished Aug 11 05:26:41 PM PDT 24
Peak memory 213760 kb
Host smart-3e335674-d9f0-494f-9735-7655248c73f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541730316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1541730316
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.2023390183
Short name T214
Test name
Test status
Simulation time 64325702209 ps
CPU time 2830.2 seconds
Started Aug 11 05:26:01 PM PDT 24
Finished Aug 11 06:13:12 PM PDT 24
Peak memory 8100948 kb
Host smart-7333e47d-077a-4e3f-bfde-7bdda833e13f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023390183 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.2023390183
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1693536914
Short name T445
Test name
Test status
Simulation time 543749968 ps
CPU time 5.35 seconds
Started Aug 11 05:26:02 PM PDT 24
Finished Aug 11 05:26:08 PM PDT 24
Peak memory 205632 kb
Host smart-b0316383-fbe5-4113-91de-cc6d1d2132f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693536914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1693536914
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.1530353720
Short name T591
Test name
Test status
Simulation time 23509131312 ps
CPU time 30.18 seconds
Started Aug 11 05:26:09 PM PDT 24
Finished Aug 11 05:26:39 PM PDT 24
Peak memory 543920 kb
Host smart-c30b5765-b377-43dc-a96a-a9fe372b9fb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530353720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.1530353720
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.527167695
Short name T999
Test name
Test status
Simulation time 1719571665 ps
CPU time 9.34 seconds
Started Aug 11 05:26:03 PM PDT 24
Finished Aug 11 05:26:13 PM PDT 24
Peak memory 277232 kb
Host smart-22810d3b-a927-4167-af08-26a44173ae44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527167695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.527167695
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.2670291361
Short name T1149
Test name
Test status
Simulation time 1425610710 ps
CPU time 8.15 seconds
Started Aug 11 05:26:00 PM PDT 24
Finished Aug 11 05:26:08 PM PDT 24
Peak memory 230124 kb
Host smart-17ad3742-7e79-4848-8abf-fddc697ce511
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670291361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.2670291361
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.3924610177
Short name T1373
Test name
Test status
Simulation time 119086122 ps
CPU time 1.65 seconds
Started Aug 11 05:26:00 PM PDT 24
Finished Aug 11 05:26:02 PM PDT 24
Peak memory 205628 kb
Host smart-c800ca7e-9a33-490a-bfb0-426791dd0a4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924610177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.3924610177
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1551760349
Short name T855
Test name
Test status
Simulation time 28736936 ps
CPU time 0.64 seconds
Started Aug 11 05:30:56 PM PDT 24
Finished Aug 11 05:30:56 PM PDT 24
Peak memory 204812 kb
Host smart-c886956f-952c-4f0c-a3ad-f032672a5e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551760349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1551760349
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.3597167390
Short name T37
Test name
Test status
Simulation time 63194308 ps
CPU time 1.51 seconds
Started Aug 11 05:30:59 PM PDT 24
Finished Aug 11 05:31:00 PM PDT 24
Peak memory 205876 kb
Host smart-d04ff662-4a46-437a-b65b-e90ded9d9848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597167390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3597167390
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2510246563
Short name T340
Test name
Test status
Simulation time 382211857 ps
CPU time 18.55 seconds
Started Aug 11 05:30:53 PM PDT 24
Finished Aug 11 05:31:12 PM PDT 24
Peak memory 270764 kb
Host smart-202d1558-b4d3-434d-b2a2-11f0737cf551
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510246563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2510246563
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.3689917325
Short name T156
Test name
Test status
Simulation time 2740936564 ps
CPU time 161.76 seconds
Started Aug 11 05:30:55 PM PDT 24
Finished Aug 11 05:33:36 PM PDT 24
Peak memory 598908 kb
Host smart-54c71743-f959-4666-b34d-44337a5c9b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689917325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.3689917325
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.1216452373
Short name T661
Test name
Test status
Simulation time 1693520764 ps
CPU time 45.43 seconds
Started Aug 11 05:30:53 PM PDT 24
Finished Aug 11 05:31:39 PM PDT 24
Peak memory 537476 kb
Host smart-03277693-1c3b-4dda-b1a3-10b35a844c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216452373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1216452373
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.434782078
Short name T1541
Test name
Test status
Simulation time 226383566 ps
CPU time 1.26 seconds
Started Aug 11 05:30:53 PM PDT 24
Finished Aug 11 05:30:54 PM PDT 24
Peak memory 205172 kb
Host smart-dccba742-aa00-49ed-a8bc-c3c244d9ed21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434782078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.434782078
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2304844708
Short name T458
Test name
Test status
Simulation time 146133477 ps
CPU time 3.65 seconds
Started Aug 11 05:30:53 PM PDT 24
Finished Aug 11 05:30:57 PM PDT 24
Peak memory 205560 kb
Host smart-8cfb22e8-d560-43e1-a3e0-112332209006
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304844708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2304844708
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1834716860
Short name T1199
Test name
Test status
Simulation time 18363754451 ps
CPU time 299.9 seconds
Started Aug 11 05:30:52 PM PDT 24
Finished Aug 11 05:35:52 PM PDT 24
Peak memory 1178016 kb
Host smart-d5aa88c6-74d6-4507-a602-fedd885c35b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834716860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1834716860
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.855765322
Short name T251
Test name
Test status
Simulation time 561071658 ps
CPU time 7.68 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:31:05 PM PDT 24
Peak memory 205536 kb
Host smart-3b05cb45-4689-4dd6-baf3-24985a274fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855765322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.855765322
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_override.2113024278
Short name T141
Test name
Test status
Simulation time 52941303 ps
CPU time 0.68 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:30:57 PM PDT 24
Peak memory 205208 kb
Host smart-ebda7352-7da1-48fb-9c7b-7ff0f8bf4fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113024278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2113024278
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3663997202
Short name T582
Test name
Test status
Simulation time 25983507254 ps
CPU time 615.13 seconds
Started Aug 11 05:30:52 PM PDT 24
Finished Aug 11 05:41:07 PM PDT 24
Peak memory 852164 kb
Host smart-c1e8311b-ce9a-48f1-ad07-183983c97798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663997202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3663997202
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.1565620036
Short name T1588
Test name
Test status
Simulation time 64507330 ps
CPU time 1.62 seconds
Started Aug 11 05:30:50 PM PDT 24
Finished Aug 11 05:30:51 PM PDT 24
Peak memory 205464 kb
Host smart-e87616ca-6e7a-475c-b228-a21dc6a7b109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565620036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.1565620036
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1285525836
Short name T1125
Test name
Test status
Simulation time 5288592475 ps
CPU time 27.79 seconds
Started Aug 11 05:30:52 PM PDT 24
Finished Aug 11 05:31:20 PM PDT 24
Peak memory 368444 kb
Host smart-78802b38-d889-46d6-92cb-137901849eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285525836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1285525836
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.1424561170
Short name T1500
Test name
Test status
Simulation time 813474309 ps
CPU time 35.57 seconds
Started Aug 11 05:31:01 PM PDT 24
Finished Aug 11 05:31:37 PM PDT 24
Peak memory 213600 kb
Host smart-27edb4cf-c16c-42ef-b1f3-7c5490ed7257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424561170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1424561170
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.180868527
Short name T1521
Test name
Test status
Simulation time 1605393617 ps
CPU time 4.12 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:31:02 PM PDT 24
Peak memory 216716 kb
Host smart-f83d32fd-2a5c-45c8-88a9-93588d92de9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180868527 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.180868527
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1547331888
Short name T895
Test name
Test status
Simulation time 191072473 ps
CPU time 0.85 seconds
Started Aug 11 05:30:59 PM PDT 24
Finished Aug 11 05:31:00 PM PDT 24
Peak memory 205404 kb
Host smart-b1833e92-cf94-4590-b49e-61f8eb059adc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547331888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1547331888
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.3162146043
Short name T1270
Test name
Test status
Simulation time 757407032 ps
CPU time 1.42 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:30:58 PM PDT 24
Peak memory 205644 kb
Host smart-18817347-d921-4e4d-a877-b4e5d6e5cdf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162146043 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.3162146043
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.2940293574
Short name T1312
Test name
Test status
Simulation time 756563224 ps
CPU time 2.59 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:31:00 PM PDT 24
Peak memory 205648 kb
Host smart-b444e144-c879-45ec-a391-c56e8e04905e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940293574 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.2940293574
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.3684790334
Short name T1558
Test name
Test status
Simulation time 172868275 ps
CPU time 1.62 seconds
Started Aug 11 05:30:59 PM PDT 24
Finished Aug 11 05:31:01 PM PDT 24
Peak memory 205388 kb
Host smart-42c18076-3067-486e-97d8-31f7add0a345
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684790334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.3684790334
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1936579084
Short name T843
Test name
Test status
Simulation time 6913839108 ps
CPU time 5.75 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:31:03 PM PDT 24
Peak memory 214956 kb
Host smart-0f0a4220-bc34-4afe-8b66-eb08acefce8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936579084 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1936579084
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1495904875
Short name T1489
Test name
Test status
Simulation time 22533410818 ps
CPU time 369.41 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:37:07 PM PDT 24
Peak memory 3941416 kb
Host smart-0a1b47b3-8ade-4958-89c5-3f711e598df6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495904875 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1495904875
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull.2026604459
Short name T826
Test name
Test status
Simulation time 581911229 ps
CPU time 3.18 seconds
Started Aug 11 05:31:02 PM PDT 24
Finished Aug 11 05:31:06 PM PDT 24
Peak memory 213780 kb
Host smart-2a87b962-6aca-44b0-9805-b317fe3925fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026604459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_nack_acqfull.2026604459
Directory /workspace/30.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/30.i2c_target_nack_acqfull_addr.3734706067
Short name T69
Test name
Test status
Simulation time 10021530780 ps
CPU time 2.65 seconds
Started Aug 11 05:30:59 PM PDT 24
Finished Aug 11 05:31:02 PM PDT 24
Peak memory 205760 kb
Host smart-2c422a9b-54c8-46e0-a5bc-dd6ff91033dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734706067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.3734706067
Directory /workspace/30.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/30.i2c_target_nack_txstretch.3702349865
Short name T772
Test name
Test status
Simulation time 514074755 ps
CPU time 1.4 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:30:58 PM PDT 24
Peak memory 222596 kb
Host smart-6ea57c1d-ed15-4633-8127-3a8de300cdcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702349865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_nack_txstretch.3702349865
Directory /workspace/30.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/30.i2c_target_perf.2937952565
Short name T1515
Test name
Test status
Simulation time 1317003534 ps
CPU time 4.65 seconds
Started Aug 11 05:30:56 PM PDT 24
Finished Aug 11 05:31:00 PM PDT 24
Peak memory 222008 kb
Host smart-2e201196-f5a3-40b7-8d2b-0fdd8f750e57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937952565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_perf.2937952565
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smbus_maxlen.684893032
Short name T1737
Test name
Test status
Simulation time 844555718 ps
CPU time 2.07 seconds
Started Aug 11 05:31:00 PM PDT 24
Finished Aug 11 05:31:02 PM PDT 24
Peak memory 205400 kb
Host smart-4d07807a-d840-4447-9f1e-e1cef798b351
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684893032 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_smbus_maxlen.684893032
Directory /workspace/30.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2081359639
Short name T1055
Test name
Test status
Simulation time 17967808483 ps
CPU time 43.94 seconds
Started Aug 11 05:30:56 PM PDT 24
Finished Aug 11 05:31:40 PM PDT 24
Peak memory 222116 kb
Host smart-76ee3c49-c16a-4a27-9e6c-6ba7af4fd93a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081359639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2081359639
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.3243531315
Short name T548
Test name
Test status
Simulation time 32469639155 ps
CPU time 80.4 seconds
Started Aug 11 05:30:58 PM PDT 24
Finished Aug 11 05:32:19 PM PDT 24
Peak memory 917164 kb
Host smart-e5b89c42-0f00-4b94-b030-a50ad15ee86d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243531315 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.3243531315
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.1684177344
Short name T70
Test name
Test status
Simulation time 5127440589 ps
CPU time 79.83 seconds
Started Aug 11 05:31:01 PM PDT 24
Finished Aug 11 05:32:20 PM PDT 24
Peak memory 218120 kb
Host smart-c6c5c736-a463-4c5f-8fad-35fea4fbc1cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684177344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.1684177344
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.753187521
Short name T1333
Test name
Test status
Simulation time 45983513885 ps
CPU time 1135.48 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:49:53 PM PDT 24
Peak memory 6563076 kb
Host smart-be97eab1-bc5a-4c34-866a-4999d268f498
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753187521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_wr.753187521
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.786762041
Short name T1099
Test name
Test status
Simulation time 3283566109 ps
CPU time 52.09 seconds
Started Aug 11 05:30:57 PM PDT 24
Finished Aug 11 05:31:49 PM PDT 24
Peak memory 911352 kb
Host smart-cdc373a9-3118-4a88-9a8a-8e6a7e37d053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786762041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_t
arget_stretch.786762041
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1574289123
Short name T1329
Test name
Test status
Simulation time 2203582349 ps
CPU time 6.5 seconds
Started Aug 11 05:30:58 PM PDT 24
Finished Aug 11 05:31:04 PM PDT 24
Peak memory 221472 kb
Host smart-8326406e-91af-49f6-8f82-1f2a46e4233b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574289123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1574289123
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.1469893821
Short name T294
Test name
Test status
Simulation time 280379605 ps
CPU time 4.76 seconds
Started Aug 11 05:30:56 PM PDT 24
Finished Aug 11 05:31:01 PM PDT 24
Peak memory 205620 kb
Host smart-37f8f8ab-bb58-42ba-81da-c0d4db556672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469893821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.1469893821
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3813760078
Short name T444
Test name
Test status
Simulation time 17971099 ps
CPU time 0.62 seconds
Started Aug 11 05:31:13 PM PDT 24
Finished Aug 11 05:31:14 PM PDT 24
Peak memory 204724 kb
Host smart-8fc37147-e2e4-4fd0-852b-5d0da2880464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813760078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3813760078
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1611446341
Short name T1619
Test name
Test status
Simulation time 60151896 ps
CPU time 1.78 seconds
Started Aug 11 05:31:02 PM PDT 24
Finished Aug 11 05:31:04 PM PDT 24
Peak memory 213656 kb
Host smart-0ddf320e-86c3-496c-9084-7667ab2028fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611446341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1611446341
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.55930519
Short name T137
Test name
Test status
Simulation time 934314696 ps
CPU time 8.38 seconds
Started Aug 11 05:31:07 PM PDT 24
Finished Aug 11 05:31:16 PM PDT 24
Peak memory 299484 kb
Host smart-a1933484-59b1-423d-b742-8057770ab615
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55930519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty
.55930519
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2424247700
Short name T465
Test name
Test status
Simulation time 18590879633 ps
CPU time 69.47 seconds
Started Aug 11 05:31:02 PM PDT 24
Finished Aug 11 05:32:11 PM PDT 24
Peak memory 588560 kb
Host smart-b629bba6-6fcb-42f9-a82d-43f995ff084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424247700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2424247700
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1021258868
Short name T1335
Test name
Test status
Simulation time 24563720080 ps
CPU time 172.06 seconds
Started Aug 11 05:31:05 PM PDT 24
Finished Aug 11 05:33:57 PM PDT 24
Peak memory 690420 kb
Host smart-5d56a308-0fca-4450-9c09-0b4d269856a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021258868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1021258868
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1171286124
Short name T1017
Test name
Test status
Simulation time 616913216 ps
CPU time 1.34 seconds
Started Aug 11 05:31:03 PM PDT 24
Finished Aug 11 05:31:04 PM PDT 24
Peak memory 205396 kb
Host smart-a8ed502b-c87c-48b3-9247-e07eec37ce01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171286124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1171286124
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.896745229
Short name T313
Test name
Test status
Simulation time 1533866220 ps
CPU time 4.13 seconds
Started Aug 11 05:31:02 PM PDT 24
Finished Aug 11 05:31:07 PM PDT 24
Peak memory 205560 kb
Host smart-8dfe1625-0d9e-4df9-9ab1-131ef98e4cda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896745229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
896745229
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.2769913863
Short name T1669
Test name
Test status
Simulation time 14720325204 ps
CPU time 85.2 seconds
Started Aug 11 05:31:04 PM PDT 24
Finished Aug 11 05:32:29 PM PDT 24
Peak memory 954784 kb
Host smart-e2990d94-88ad-4bec-9b5b-0b01b94218c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769913863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.2769913863
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.3281058979
Short name T245
Test name
Test status
Simulation time 1862714744 ps
CPU time 7.76 seconds
Started Aug 11 05:31:10 PM PDT 24
Finished Aug 11 05:31:18 PM PDT 24
Peak memory 205580 kb
Host smart-26d2e330-48d0-4a3d-b0ad-65d91459e107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281058979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3281058979
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.2941958360
Short name T764
Test name
Test status
Simulation time 131871970 ps
CPU time 1.26 seconds
Started Aug 11 05:31:11 PM PDT 24
Finished Aug 11 05:31:12 PM PDT 24
Peak memory 205440 kb
Host smart-9c6be5e5-73e7-43d6-9bc1-ad6dee0d2ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941958360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2941958360
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1676017790
Short name T712
Test name
Test status
Simulation time 57599316 ps
CPU time 0.64 seconds
Started Aug 11 05:31:01 PM PDT 24
Finished Aug 11 05:31:02 PM PDT 24
Peak memory 205200 kb
Host smart-4fc38330-15ea-43ba-8cfe-a1b9fafe2e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676017790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1676017790
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.229967881
Short name T1693
Test name
Test status
Simulation time 2832221377 ps
CPU time 14.26 seconds
Started Aug 11 05:31:10 PM PDT 24
Finished Aug 11 05:31:25 PM PDT 24
Peak memory 346020 kb
Host smart-def86929-40b9-44cc-aa6c-c11cd8ad5000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229967881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.229967881
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.2871302101
Short name T371
Test name
Test status
Simulation time 52300982 ps
CPU time 1.46 seconds
Started Aug 11 05:31:02 PM PDT 24
Finished Aug 11 05:31:04 PM PDT 24
Peak memory 229936 kb
Host smart-0c02ec30-ba33-480d-8a1c-05925fcf21ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871302101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.2871302101
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2755351313
Short name T776
Test name
Test status
Simulation time 1906533838 ps
CPU time 93.74 seconds
Started Aug 11 05:31:12 PM PDT 24
Finished Aug 11 05:32:46 PM PDT 24
Peak memory 376120 kb
Host smart-8d28610f-2192-457d-b52f-c023da020009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755351313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2755351313
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.2817344707
Short name T560
Test name
Test status
Simulation time 1923289216 ps
CPU time 8.04 seconds
Started Aug 11 05:31:05 PM PDT 24
Finished Aug 11 05:31:13 PM PDT 24
Peak memory 221792 kb
Host smart-bcb81b51-7871-425a-852e-9caae7c9e1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817344707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.2817344707
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.1965798197
Short name T64
Test name
Test status
Simulation time 1236092321 ps
CPU time 7 seconds
Started Aug 11 05:31:08 PM PDT 24
Finished Aug 11 05:31:15 PM PDT 24
Peak memory 213868 kb
Host smart-3f19aa91-81a8-4003-8588-f57d3ab05796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965798197 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.1965798197
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1640765192
Short name T1117
Test name
Test status
Simulation time 241312839 ps
CPU time 1.42 seconds
Started Aug 11 05:31:05 PM PDT 24
Finished Aug 11 05:31:07 PM PDT 24
Peak memory 206188 kb
Host smart-de238bb2-775a-42c6-a2f4-fd39dad50349
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640765192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1640765192
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1682058645
Short name T436
Test name
Test status
Simulation time 160968996 ps
CPU time 1.24 seconds
Started Aug 11 05:31:07 PM PDT 24
Finished Aug 11 05:31:08 PM PDT 24
Peak memory 205516 kb
Host smart-e317abf3-b257-44d7-b57e-e08dd1a0857a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682058645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1682058645
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.2641206617
Short name T1559
Test name
Test status
Simulation time 1998971727 ps
CPU time 2.59 seconds
Started Aug 11 05:31:09 PM PDT 24
Finished Aug 11 05:31:12 PM PDT 24
Peak memory 205572 kb
Host smart-aab510b8-9f37-44aa-ac24-344bf89bde43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641206617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.2641206617
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.3828376688
Short name T1730
Test name
Test status
Simulation time 469961657 ps
CPU time 1.1 seconds
Started Aug 11 05:31:12 PM PDT 24
Finished Aug 11 05:31:13 PM PDT 24
Peak memory 205512 kb
Host smart-3e5b6b04-1dce-4bcd-ae06-64c00ef9d0cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828376688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.3828376688
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.868502962
Short name T589
Test name
Test status
Simulation time 492079701 ps
CPU time 3.25 seconds
Started Aug 11 05:31:01 PM PDT 24
Finished Aug 11 05:31:05 PM PDT 24
Peak memory 213796 kb
Host smart-5e46fd2e-4fcf-4195-aa58-bc7f0cb79a73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868502962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.868502962
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.623076676
Short name T1645
Test name
Test status
Simulation time 3375833636 ps
CPU time 25.02 seconds
Started Aug 11 05:31:02 PM PDT 24
Finished Aug 11 05:31:27 PM PDT 24
Peak memory 949484 kb
Host smart-7701e6a8-a60b-4f4d-bb17-90517a0012ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623076676 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.623076676
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull.2852391153
Short name T88
Test name
Test status
Simulation time 769569146 ps
CPU time 3.1 seconds
Started Aug 11 05:31:10 PM PDT 24
Finished Aug 11 05:31:13 PM PDT 24
Peak memory 213864 kb
Host smart-77fe645d-14e3-43f8-8756-a9ecb6562350
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852391153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_nack_acqfull.2852391153
Directory /workspace/31.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/31.i2c_target_nack_acqfull_addr.68406627
Short name T158
Test name
Test status
Simulation time 538520093 ps
CPU time 2.81 seconds
Started Aug 11 05:31:09 PM PDT 24
Finished Aug 11 05:31:12 PM PDT 24
Peak memory 205780 kb
Host smart-4e845b91-90b2-4e12-a64f-6317083f23d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68406627 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_nack_acqfull_addr.68406627
Directory /workspace/31.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/31.i2c_target_nack_txstretch.9565683
Short name T166
Test name
Test status
Simulation time 235422505 ps
CPU time 1.35 seconds
Started Aug 11 05:31:13 PM PDT 24
Finished Aug 11 05:31:14 PM PDT 24
Peak memory 222392 kb
Host smart-fbbff06b-ceac-48e8-9761-d1f9d9c44eb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9565683 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_nack_txstretch.9565683
Directory /workspace/31.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/31.i2c_target_perf.3875145882
Short name T1483
Test name
Test status
Simulation time 527273878 ps
CPU time 3.68 seconds
Started Aug 11 05:31:08 PM PDT 24
Finished Aug 11 05:31:11 PM PDT 24
Peak memory 214800 kb
Host smart-dc50b306-9f25-42ea-988e-5d57a4a24748
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875145882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.3875145882
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smbus_maxlen.3947579721
Short name T1659
Test name
Test status
Simulation time 931511201 ps
CPU time 2.34 seconds
Started Aug 11 05:31:10 PM PDT 24
Finished Aug 11 05:31:12 PM PDT 24
Peak memory 205488 kb
Host smart-1e3c9a4a-6731-4b73-9a73-bcf19fbf4227
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947579721 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_smbus_maxlen.3947579721
Directory /workspace/31.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2875914439
Short name T620
Test name
Test status
Simulation time 1470887339 ps
CPU time 11.26 seconds
Started Aug 11 05:31:04 PM PDT 24
Finished Aug 11 05:31:16 PM PDT 24
Peak memory 213800 kb
Host smart-22ab78ab-ae40-4b2f-bd77-fd05d6e2cd1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875914439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2875914439
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.780507256
Short name T1623
Test name
Test status
Simulation time 106798270832 ps
CPU time 93.15 seconds
Started Aug 11 05:31:10 PM PDT 24
Finished Aug 11 05:32:44 PM PDT 24
Peak memory 870712 kb
Host smart-1ade3bdc-21d0-4a2f-98cf-f6c0f6b7063c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780507256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.i2c_target_stress_all.780507256
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1779363053
Short name T600
Test name
Test status
Simulation time 1622307731 ps
CPU time 26.65 seconds
Started Aug 11 05:31:11 PM PDT 24
Finished Aug 11 05:31:38 PM PDT 24
Peak memory 233320 kb
Host smart-109bd8d8-5e32-42f1-851e-42d2d59d1b83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779363053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1779363053
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.1204522248
Short name T56
Test name
Test status
Simulation time 52202303848 ps
CPU time 167.98 seconds
Started Aug 11 05:31:04 PM PDT 24
Finished Aug 11 05:33:53 PM PDT 24
Peak memory 2003832 kb
Host smart-1956b52e-9595-4d9c-a4f0-9629edc72d9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204522248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.1204522248
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1345900672
Short name T91
Test name
Test status
Simulation time 2000539154 ps
CPU time 89.79 seconds
Started Aug 11 05:31:06 PM PDT 24
Finished Aug 11 05:32:36 PM PDT 24
Peak memory 634596 kb
Host smart-e76df08b-febe-4abb-be62-f35c592d323b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345900672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1345900672
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.833234410
Short name T1252
Test name
Test status
Simulation time 9300518259 ps
CPU time 6.68 seconds
Started Aug 11 05:31:06 PM PDT 24
Finished Aug 11 05:31:13 PM PDT 24
Peak memory 222156 kb
Host smart-4ff0d636-5b9d-429b-b674-db7407d7fcde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833234410 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_timeout.833234410
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.3321527477
Short name T1363
Test name
Test status
Simulation time 175183690 ps
CPU time 2.96 seconds
Started Aug 11 05:31:08 PM PDT 24
Finished Aug 11 05:31:11 PM PDT 24
Peak memory 205648 kb
Host smart-88e31097-b791-4b88-8163-bd8c98db7b43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321527477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.3321527477
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2896473151
Short name T880
Test name
Test status
Simulation time 18069026 ps
CPU time 0.64 seconds
Started Aug 11 05:31:20 PM PDT 24
Finished Aug 11 05:31:20 PM PDT 24
Peak memory 204644 kb
Host smart-7ed12474-f43b-48c9-81d0-296585d39966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896473151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2896473151
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.4076600266
Short name T1053
Test name
Test status
Simulation time 598565666 ps
CPU time 1.85 seconds
Started Aug 11 05:31:16 PM PDT 24
Finished Aug 11 05:31:19 PM PDT 24
Peak memory 213416 kb
Host smart-03be1cac-1d9b-4168-b91a-2fe45d0e5a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076600266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.4076600266
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.634538874
Short name T907
Test name
Test status
Simulation time 2567294371 ps
CPU time 6.07 seconds
Started Aug 11 05:31:08 PM PDT 24
Finished Aug 11 05:31:14 PM PDT 24
Peak memory 271524 kb
Host smart-55d3c525-34bc-419c-af92-0d88eb9b7ee7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634538874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.634538874
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.3612929306
Short name T1040
Test name
Test status
Simulation time 7959065288 ps
CPU time 134.92 seconds
Started Aug 11 05:31:16 PM PDT 24
Finished Aug 11 05:33:31 PM PDT 24
Peak memory 543928 kb
Host smart-a473b2eb-3953-44b2-83c3-19f10adfdb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612929306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3612929306
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3287792703
Short name T998
Test name
Test status
Simulation time 7540972981 ps
CPU time 63.85 seconds
Started Aug 11 05:31:07 PM PDT 24
Finished Aug 11 05:32:11 PM PDT 24
Peak memory 676160 kb
Host smart-0a700aa0-0094-4e81-8959-b393c661ceea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287792703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3287792703
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2027323100
Short name T1250
Test name
Test status
Simulation time 458802756 ps
CPU time 1.12 seconds
Started Aug 11 05:31:14 PM PDT 24
Finished Aug 11 05:31:15 PM PDT 24
Peak memory 205220 kb
Host smart-14f54643-c196-42cc-8410-b03c9299958f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027323100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2027323100
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.412312004
Short name T433
Test name
Test status
Simulation time 260231795 ps
CPU time 3.2 seconds
Started Aug 11 05:31:13 PM PDT 24
Finished Aug 11 05:31:17 PM PDT 24
Peak memory 205476 kb
Host smart-0e668a78-d384-4313-bef8-53d573215851
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412312004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
412312004
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.841625614
Short name T594
Test name
Test status
Simulation time 20348648824 ps
CPU time 154.66 seconds
Started Aug 11 05:31:13 PM PDT 24
Finished Aug 11 05:33:48 PM PDT 24
Peak memory 1474056 kb
Host smart-8a6d9892-837b-4300-91e0-7d784640430b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841625614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.841625614
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.2165230237
Short name T1736
Test name
Test status
Simulation time 2145814954 ps
CPU time 18.55 seconds
Started Aug 11 05:31:14 PM PDT 24
Finished Aug 11 05:31:33 PM PDT 24
Peak memory 205436 kb
Host smart-225a52b7-6421-4ccc-a297-1814b3c6a0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165230237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.2165230237
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_perf.208160526
Short name T1440
Test name
Test status
Simulation time 432343021 ps
CPU time 8.35 seconds
Started Aug 11 05:31:15 PM PDT 24
Finished Aug 11 05:31:24 PM PDT 24
Peak memory 269460 kb
Host smart-288ecd62-71d6-4058-8669-755042fdbe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208160526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.208160526
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.3822871713
Short name T741
Test name
Test status
Simulation time 275246261 ps
CPU time 1.63 seconds
Started Aug 11 05:31:15 PM PDT 24
Finished Aug 11 05:31:17 PM PDT 24
Peak memory 205396 kb
Host smart-49c8c6fe-3c50-40e4-b87d-e0a91a904459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822871713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.3822871713
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.4031073178
Short name T891
Test name
Test status
Simulation time 10470487432 ps
CPU time 84.56 seconds
Started Aug 11 05:31:14 PM PDT 24
Finished Aug 11 05:32:39 PM PDT 24
Peak memory 412728 kb
Host smart-bb587632-1a8e-4307-9b53-b863b22c60d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031073178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.4031073178
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.529226691
Short name T544
Test name
Test status
Simulation time 858820913 ps
CPU time 16.07 seconds
Started Aug 11 05:31:16 PM PDT 24
Finished Aug 11 05:31:32 PM PDT 24
Peak memory 221952 kb
Host smart-759d63e9-c217-4ad0-bad8-ade8681d51e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529226691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.529226691
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.3981587526
Short name T1496
Test name
Test status
Simulation time 2617674020 ps
CPU time 6.24 seconds
Started Aug 11 05:31:15 PM PDT 24
Finished Aug 11 05:31:21 PM PDT 24
Peak memory 213932 kb
Host smart-c9511a51-d858-4ce6-95d6-fcf2bca5cdb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981587526 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.3981587526
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.2364606630
Short name T994
Test name
Test status
Simulation time 627220104 ps
CPU time 1.48 seconds
Started Aug 11 05:31:17 PM PDT 24
Finished Aug 11 05:31:18 PM PDT 24
Peak memory 205616 kb
Host smart-1534caf2-432f-46b8-85ec-126727822423
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364606630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.2364606630
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3717578209
Short name T1529
Test name
Test status
Simulation time 276025291 ps
CPU time 1.69 seconds
Started Aug 11 05:31:17 PM PDT 24
Finished Aug 11 05:31:19 PM PDT 24
Peak memory 213736 kb
Host smart-c0130182-61c7-42be-8bb8-8b99f4614e49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717578209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3717578209
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.3604539924
Short name T1465
Test name
Test status
Simulation time 992204269 ps
CPU time 2.77 seconds
Started Aug 11 05:31:23 PM PDT 24
Finished Aug 11 05:31:26 PM PDT 24
Peak memory 205640 kb
Host smart-cc139f25-57f9-4b06-90e3-dba656c8aeb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604539924 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.3604539924
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.1690313927
Short name T1175
Test name
Test status
Simulation time 245822445 ps
CPU time 1.19 seconds
Started Aug 11 05:31:17 PM PDT 24
Finished Aug 11 05:31:18 PM PDT 24
Peak memory 205440 kb
Host smart-11c5b6ce-c59c-4ab3-a65f-27692341a33c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690313927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.1690313927
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3750220105
Short name T1510
Test name
Test status
Simulation time 3354114869 ps
CPU time 2.32 seconds
Started Aug 11 05:31:14 PM PDT 24
Finished Aug 11 05:31:16 PM PDT 24
Peak memory 214080 kb
Host smart-c0fc569d-6f83-45e4-8f8f-25246a12c537
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750220105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3750220105
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3045830048
Short name T1148
Test name
Test status
Simulation time 2205047937 ps
CPU time 6.45 seconds
Started Aug 11 05:31:17 PM PDT 24
Finished Aug 11 05:31:24 PM PDT 24
Peak memory 213948 kb
Host smart-97c28531-f3b9-4fc6-be16-5ab95e957d10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045830048 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3045830048
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.454751421
Short name T687
Test name
Test status
Simulation time 21610353450 ps
CPU time 65.92 seconds
Started Aug 11 05:31:16 PM PDT 24
Finished Aug 11 05:32:22 PM PDT 24
Peak memory 1207052 kb
Host smart-e68639cd-69e0-4b84-b74a-761fdcd13f6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454751421 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.454751421
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull.354138123
Short name T1456
Test name
Test status
Simulation time 4602008133 ps
CPU time 2.85 seconds
Started Aug 11 05:31:12 PM PDT 24
Finished Aug 11 05:31:15 PM PDT 24
Peak memory 213916 kb
Host smart-8c067c10-7f39-44ff-8dfe-dd85f6d0fe58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354138123 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_nack_acqfull.354138123
Directory /workspace/32.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/32.i2c_target_nack_acqfull_addr.3919208479
Short name T61
Test name
Test status
Simulation time 3181028150 ps
CPU time 2.37 seconds
Started Aug 11 05:31:23 PM PDT 24
Finished Aug 11 05:31:25 PM PDT 24
Peak memory 205824 kb
Host smart-27e39888-46f9-4a87-aff3-67ddaf97b6c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919208479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.3919208479
Directory /workspace/32.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.2843746956
Short name T526
Test name
Test status
Simulation time 702612934 ps
CPU time 5.03 seconds
Started Aug 11 05:31:13 PM PDT 24
Finished Aug 11 05:31:19 PM PDT 24
Peak memory 221956 kb
Host smart-cc8676fe-7622-48be-ae54-1b87acca3d2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843746956 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_perf.2843746956
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smbus_maxlen.197956422
Short name T375
Test name
Test status
Simulation time 1860591186 ps
CPU time 2.29 seconds
Started Aug 11 05:31:16 PM PDT 24
Finished Aug 11 05:31:18 PM PDT 24
Peak memory 205416 kb
Host smart-5eaaa419-1a40-48a4-b4c2-cdd996c353da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197956422 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_smbus_maxlen.197956422
Directory /workspace/32.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3550181433
Short name T497
Test name
Test status
Simulation time 1940139875 ps
CPU time 8.16 seconds
Started Aug 11 05:31:15 PM PDT 24
Finished Aug 11 05:31:24 PM PDT 24
Peak memory 213884 kb
Host smart-6e25c1c2-39a6-4428-ae65-780e682365a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550181433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3550181433
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.3217136295
Short name T1608
Test name
Test status
Simulation time 51318124404 ps
CPU time 82.45 seconds
Started Aug 11 05:31:16 PM PDT 24
Finished Aug 11 05:32:39 PM PDT 24
Peak memory 553688 kb
Host smart-81cfb734-71d6-4e90-af91-be1d2ed3ca96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217136295 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.3217136295
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1839009219
Short name T335
Test name
Test status
Simulation time 13339940676 ps
CPU time 30.5 seconds
Started Aug 11 05:31:15 PM PDT 24
Finished Aug 11 05:31:46 PM PDT 24
Peak memory 246620 kb
Host smart-6deb5087-1c60-44cf-94da-a89c3e337154
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839009219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1839009219
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.2211335343
Short name T172
Test name
Test status
Simulation time 44030831528 ps
CPU time 291.52 seconds
Started Aug 11 05:31:16 PM PDT 24
Finished Aug 11 05:36:08 PM PDT 24
Peak memory 3038456 kb
Host smart-fa03bd89-b90f-494d-9576-c0ced1243d32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211335343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.2211335343
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1376778942
Short name T550
Test name
Test status
Simulation time 1671004190 ps
CPU time 15.52 seconds
Started Aug 11 05:31:15 PM PDT 24
Finished Aug 11 05:31:30 PM PDT 24
Peak memory 274472 kb
Host smart-8e27c899-32a0-42b4-a2fd-162bf766169c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376778942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1376778942
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.248714486
Short name T587
Test name
Test status
Simulation time 5213213171 ps
CPU time 7.16 seconds
Started Aug 11 05:31:16 PM PDT 24
Finished Aug 11 05:31:24 PM PDT 24
Peak memory 213992 kb
Host smart-b42b7de1-6cc2-4abd-8be4-5808e506a3b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248714486 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_timeout.248714486
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.906093113
Short name T690
Test name
Test status
Simulation time 126409815 ps
CPU time 2.72 seconds
Started Aug 11 05:31:14 PM PDT 24
Finished Aug 11 05:31:17 PM PDT 24
Peak memory 205636 kb
Host smart-011d05f1-71ee-49fb-8e92-7fd17af25815
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906093113 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.906093113
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1668059959
Short name T370
Test name
Test status
Simulation time 40626871 ps
CPU time 0.63 seconds
Started Aug 11 05:31:36 PM PDT 24
Finished Aug 11 05:31:36 PM PDT 24
Peak memory 204776 kb
Host smart-27c34d95-50b9-4fe3-b67c-128bd3326fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668059959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1668059959
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.1996545573
Short name T607
Test name
Test status
Simulation time 181474743 ps
CPU time 1.62 seconds
Started Aug 11 05:31:18 PM PDT 24
Finished Aug 11 05:31:20 PM PDT 24
Peak memory 221792 kb
Host smart-2b3bcf08-24d7-48ba-b5f0-b20fb6cd545f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996545573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.1996545573
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.198055859
Short name T1568
Test name
Test status
Simulation time 1674403677 ps
CPU time 33.03 seconds
Started Aug 11 05:31:21 PM PDT 24
Finished Aug 11 05:31:55 PM PDT 24
Peak memory 347676 kb
Host smart-5ff2f9bf-7c77-4df0-b2a9-ff03fe1871db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198055859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.198055859
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3155321780
Short name T954
Test name
Test status
Simulation time 12127109010 ps
CPU time 233.84 seconds
Started Aug 11 05:31:22 PM PDT 24
Finished Aug 11 05:35:16 PM PDT 24
Peak memory 798932 kb
Host smart-e5025b0a-5fa1-40a6-9a37-43da0c70fd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155321780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3155321780
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.4272542550
Short name T1019
Test name
Test status
Simulation time 8878948284 ps
CPU time 107.77 seconds
Started Aug 11 05:31:20 PM PDT 24
Finished Aug 11 05:33:08 PM PDT 24
Peak memory 573992 kb
Host smart-25c78350-9b87-4692-9978-712f37f6baed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272542550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.4272542550
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.2011180298
Short name T1050
Test name
Test status
Simulation time 497222502 ps
CPU time 1.17 seconds
Started Aug 11 05:31:21 PM PDT 24
Finished Aug 11 05:31:22 PM PDT 24
Peak memory 205168 kb
Host smart-f1c60771-8f12-4719-82d1-1e69bc483e06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011180298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.2011180298
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2969727966
Short name T1461
Test name
Test status
Simulation time 560019264 ps
CPU time 4.48 seconds
Started Aug 11 05:31:21 PM PDT 24
Finished Aug 11 05:31:26 PM PDT 24
Peak memory 231732 kb
Host smart-2935fc5d-5a66-4f68-83fd-e44b2aa9d742
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969727966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2969727966
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3570263800
Short name T1528
Test name
Test status
Simulation time 2988581674 ps
CPU time 72.05 seconds
Started Aug 11 05:31:21 PM PDT 24
Finished Aug 11 05:32:33 PM PDT 24
Peak memory 823764 kb
Host smart-20797ba2-0927-4aa9-a6e5-ed7bd1de5ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570263800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3570263800
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.652831812
Short name T470
Test name
Test status
Simulation time 1437789343 ps
CPU time 14.6 seconds
Started Aug 11 05:31:26 PM PDT 24
Finished Aug 11 05:31:40 PM PDT 24
Peak memory 205544 kb
Host smart-fbb356a0-89c6-4856-b512-b04abbed3871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652831812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.652831812
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.4201396894
Short name T1139
Test name
Test status
Simulation time 251406039 ps
CPU time 4.05 seconds
Started Aug 11 05:31:28 PM PDT 24
Finished Aug 11 05:31:32 PM PDT 24
Peak memory 213772 kb
Host smart-1f876644-d575-44a9-9096-00962800c455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201396894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.4201396894
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.2636355095
Short name T1491
Test name
Test status
Simulation time 25597418 ps
CPU time 0.72 seconds
Started Aug 11 05:31:23 PM PDT 24
Finished Aug 11 05:31:24 PM PDT 24
Peak memory 205128 kb
Host smart-f77a90f1-3670-4568-9bc7-9f47a858ef81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636355095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2636355095
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3475660850
Short name T1450
Test name
Test status
Simulation time 28099091439 ps
CPU time 1785.58 seconds
Started Aug 11 05:31:21 PM PDT 24
Finished Aug 11 06:01:07 PM PDT 24
Peak memory 4006628 kb
Host smart-3ba24462-4d73-4eba-a8dd-4265ab830f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475660850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3475660850
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.1127106177
Short name T711
Test name
Test status
Simulation time 5804548120 ps
CPU time 41.75 seconds
Started Aug 11 05:31:20 PM PDT 24
Finished Aug 11 05:32:02 PM PDT 24
Peak memory 213752 kb
Host smart-c3c01f4d-a084-4c0a-ba79-a2b522900f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127106177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.1127106177
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.1714201635
Short name T1225
Test name
Test status
Simulation time 1541785699 ps
CPU time 24.1 seconds
Started Aug 11 05:31:18 PM PDT 24
Finished Aug 11 05:31:42 PM PDT 24
Peak memory 303048 kb
Host smart-7d450b93-0596-4bbb-9074-ef494bb7bbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714201635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.1714201635
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.3593856536
Short name T1155
Test name
Test status
Simulation time 1198425422 ps
CPU time 26.68 seconds
Started Aug 11 05:31:19 PM PDT 24
Finished Aug 11 05:31:46 PM PDT 24
Peak memory 213788 kb
Host smart-890bca8f-8005-4031-b4a2-b1c2bf83b1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593856536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.3593856536
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3192943685
Short name T1009
Test name
Test status
Simulation time 11112613438 ps
CPU time 4.96 seconds
Started Aug 11 05:31:26 PM PDT 24
Finished Aug 11 05:31:31 PM PDT 24
Peak memory 222020 kb
Host smart-27eedb84-aa04-4683-9a6c-c1b626d24919
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192943685 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3192943685
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2340181494
Short name T763
Test name
Test status
Simulation time 464775485 ps
CPU time 1.19 seconds
Started Aug 11 05:31:28 PM PDT 24
Finished Aug 11 05:31:29 PM PDT 24
Peak memory 205428 kb
Host smart-885b8465-ae23-429a-9b25-d38beefb50ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340181494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2340181494
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3325136963
Short name T1069
Test name
Test status
Simulation time 216513736 ps
CPU time 1.1 seconds
Started Aug 11 05:31:25 PM PDT 24
Finished Aug 11 05:31:26 PM PDT 24
Peak memory 213796 kb
Host smart-84c35a0f-f270-4d32-ad4d-84af7ffebef3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325136963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3325136963
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.4081849856
Short name T316
Test name
Test status
Simulation time 1258142850 ps
CPU time 3.25 seconds
Started Aug 11 05:31:27 PM PDT 24
Finished Aug 11 05:31:31 PM PDT 24
Peak memory 205572 kb
Host smart-80e01bf4-6af1-40f0-af4c-7cd7bccc6c26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081849856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.4081849856
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.3471576108
Short name T114
Test name
Test status
Simulation time 151382270 ps
CPU time 1.44 seconds
Started Aug 11 05:31:28 PM PDT 24
Finished Aug 11 05:31:30 PM PDT 24
Peak memory 205464 kb
Host smart-47f9086f-24ab-41be-bd95-07f566a4d5bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471576108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.3471576108
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.316333230
Short name T1408
Test name
Test status
Simulation time 1569324414 ps
CPU time 2.13 seconds
Started Aug 11 05:31:29 PM PDT 24
Finished Aug 11 05:31:31 PM PDT 24
Peak memory 213932 kb
Host smart-3c9326a3-2d49-4281-8c08-522cdc1f6fe5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316333230 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.i2c_target_hrst.316333230
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.157047204
Short name T1554
Test name
Test status
Simulation time 18611097758 ps
CPU time 7.25 seconds
Started Aug 11 05:31:24 PM PDT 24
Finished Aug 11 05:31:32 PM PDT 24
Peak memory 222084 kb
Host smart-152fb8be-5e88-4b51-a4cd-e8a7fbbeaca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157047204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.157047204
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.3467531562
Short name T760
Test name
Test status
Simulation time 13013568094 ps
CPU time 247.53 seconds
Started Aug 11 05:31:28 PM PDT 24
Finished Aug 11 05:35:36 PM PDT 24
Peak memory 3243072 kb
Host smart-4ea3c78b-59a1-4545-b456-949fd98f32ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467531562 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3467531562
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull.2436423255
Short name T670
Test name
Test status
Simulation time 1981154292 ps
CPU time 3.04 seconds
Started Aug 11 05:31:27 PM PDT 24
Finished Aug 11 05:31:30 PM PDT 24
Peak memory 213904 kb
Host smart-51780941-8c12-4754-99d4-b2cb87d6a3c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436423255 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_nack_acqfull.2436423255
Directory /workspace/33.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/33.i2c_target_nack_acqfull_addr.1999873894
Short name T1457
Test name
Test status
Simulation time 1098817759 ps
CPU time 2.82 seconds
Started Aug 11 05:31:28 PM PDT 24
Finished Aug 11 05:31:31 PM PDT 24
Peak memory 205536 kb
Host smart-9ed075be-5f66-4be7-b884-3bfde920b074
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999873894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_nack_acqfull_addr.1999873894
Directory /workspace/33.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.1967420654
Short name T1082
Test name
Test status
Simulation time 860053772 ps
CPU time 5.77 seconds
Started Aug 11 05:31:28 PM PDT 24
Finished Aug 11 05:31:34 PM PDT 24
Peak memory 213936 kb
Host smart-97a33f45-90d2-45f1-9e4b-6f88d74568be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967420654 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.1967420654
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smbus_maxlen.4173674475
Short name T890
Test name
Test status
Simulation time 447081304 ps
CPU time 2.14 seconds
Started Aug 11 05:31:25 PM PDT 24
Finished Aug 11 05:31:28 PM PDT 24
Peak memory 205380 kb
Host smart-7cbc7412-6476-4715-a10f-39de8cf4431c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173674475 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_smbus_maxlen.4173674475
Directory /workspace/33.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3911724241
Short name T1683
Test name
Test status
Simulation time 8092412842 ps
CPU time 40.93 seconds
Started Aug 11 05:31:27 PM PDT 24
Finished Aug 11 05:32:08 PM PDT 24
Peak memory 213880 kb
Host smart-5a76a7a1-d4fe-493e-9582-ec2c1554bac8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911724241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3911724241
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.1951588360
Short name T811
Test name
Test status
Simulation time 137121815919 ps
CPU time 60.65 seconds
Started Aug 11 05:31:27 PM PDT 24
Finished Aug 11 05:32:28 PM PDT 24
Peak memory 444220 kb
Host smart-14ba2708-eec1-4427-942f-5512eafafcbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951588360 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.1951588360
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.4285733086
Short name T8
Test name
Test status
Simulation time 3517514090 ps
CPU time 11.05 seconds
Started Aug 11 05:31:26 PM PDT 24
Finished Aug 11 05:31:37 PM PDT 24
Peak memory 220332 kb
Host smart-e04c21c6-fbb1-42fb-b2ad-33856a52864d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285733086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.4285733086
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.3138613395
Short name T581
Test name
Test status
Simulation time 41963290972 ps
CPU time 833.88 seconds
Started Aug 11 05:31:27 PM PDT 24
Finished Aug 11 05:45:21 PM PDT 24
Peak memory 5808856 kb
Host smart-4826c798-db06-493f-99e8-e2eaa050579f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138613395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.3138613395
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.2589874780
Short name T1021
Test name
Test status
Simulation time 4795649986 ps
CPU time 2.24 seconds
Started Aug 11 05:31:30 PM PDT 24
Finished Aug 11 05:31:32 PM PDT 24
Peak memory 237692 kb
Host smart-4ccbcecd-d8d9-4f4b-baa9-f64cd5841e36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589874780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.2589874780
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.801980610
Short name T708
Test name
Test status
Simulation time 2766599989 ps
CPU time 7.82 seconds
Started Aug 11 05:31:26 PM PDT 24
Finished Aug 11 05:31:34 PM PDT 24
Peak memory 222100 kb
Host smart-e23d24dd-e788-4633-8e39-81bcb728878f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801980610 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_timeout.801980610
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.686244712
Short name T1140
Test name
Test status
Simulation time 175012410 ps
CPU time 2.52 seconds
Started Aug 11 05:31:25 PM PDT 24
Finished Aug 11 05:31:27 PM PDT 24
Peak memory 205624 kb
Host smart-089f0750-4dea-4661-b0ee-52e9a30b5145
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686244712 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.686244712
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.639418684
Short name T536
Test name
Test status
Simulation time 31891272 ps
CPU time 0.67 seconds
Started Aug 11 05:31:38 PM PDT 24
Finished Aug 11 05:31:38 PM PDT 24
Peak memory 204816 kb
Host smart-ce05c9cf-1701-4858-a184-2c5b07d6d404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639418684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.639418684
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.4134725483
Short name T321
Test name
Test status
Simulation time 1620355772 ps
CPU time 20.82 seconds
Started Aug 11 05:31:34 PM PDT 24
Finished Aug 11 05:31:54 PM PDT 24
Peak memory 291740 kb
Host smart-08d229d7-d402-4e35-bde6-d3bfc3a32fbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134725483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.4134725483
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.4093854547
Short name T1615
Test name
Test status
Simulation time 1894892095 ps
CPU time 107.04 seconds
Started Aug 11 05:31:31 PM PDT 24
Finished Aug 11 05:33:18 PM PDT 24
Peak memory 430200 kb
Host smart-ea3b34d9-209e-4eb9-937d-a8543413dbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093854547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.4093854547
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.140060116
Short name T1062
Test name
Test status
Simulation time 1306588678 ps
CPU time 37.16 seconds
Started Aug 11 05:31:32 PM PDT 24
Finished Aug 11 05:32:09 PM PDT 24
Peak memory 530636 kb
Host smart-8981fa3d-7066-456c-aebb-646133f29f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140060116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.140060116
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3785985152
Short name T525
Test name
Test status
Simulation time 115543738 ps
CPU time 1.06 seconds
Started Aug 11 05:31:34 PM PDT 24
Finished Aug 11 05:31:36 PM PDT 24
Peak memory 205224 kb
Host smart-25846785-4219-4618-b4fe-6f943b538a8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785985152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3785985152
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.4042015101
Short name T1703
Test name
Test status
Simulation time 524120746 ps
CPU time 2.98 seconds
Started Aug 11 05:31:36 PM PDT 24
Finished Aug 11 05:31:39 PM PDT 24
Peak memory 205484 kb
Host smart-1e551eb2-7791-407b-bd07-78d9f80ed4bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042015101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.4042015101
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.3221345315
Short name T975
Test name
Test status
Simulation time 14514640551 ps
CPU time 85.87 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:33:03 PM PDT 24
Peak memory 851136 kb
Host smart-312f11d7-4b08-4cc3-8059-ece740cfaa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221345315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3221345315
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.343418609
Short name T20
Test name
Test status
Simulation time 2747596365 ps
CPU time 12.72 seconds
Started Aug 11 05:31:39 PM PDT 24
Finished Aug 11 05:31:52 PM PDT 24
Peak memory 205880 kb
Host smart-9d8841cc-eea2-4c7a-b507-df17524eb383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343418609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.343418609
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_override.2672520934
Short name T1628
Test name
Test status
Simulation time 31957844 ps
CPU time 0.68 seconds
Started Aug 11 05:31:35 PM PDT 24
Finished Aug 11 05:31:36 PM PDT 24
Peak memory 205128 kb
Host smart-5d811431-626f-4ead-8565-22465734e690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672520934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.2672520934
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3155598407
Short name T700
Test name
Test status
Simulation time 7899445563 ps
CPU time 67.6 seconds
Started Aug 11 05:31:36 PM PDT 24
Finished Aug 11 05:32:43 PM PDT 24
Peak memory 485916 kb
Host smart-7e328415-161b-48eb-a188-6bd4a45a2074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155598407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3155598407
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.3257406262
Short name T568
Test name
Test status
Simulation time 726136909 ps
CPU time 14.92 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:31:52 PM PDT 24
Peak memory 332988 kb
Host smart-b05691b0-9098-4e65-8a62-5a8884feb8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257406262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.3257406262
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2991524936
Short name T642
Test name
Test status
Simulation time 1692504313 ps
CPU time 28.31 seconds
Started Aug 11 05:31:31 PM PDT 24
Finished Aug 11 05:31:59 PM PDT 24
Peak memory 294864 kb
Host smart-52bf14ce-727b-495a-ac4f-1d2a29f7ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991524936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2991524936
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.672470104
Short name T1709
Test name
Test status
Simulation time 1395496074 ps
CPU time 13.72 seconds
Started Aug 11 05:31:32 PM PDT 24
Finished Aug 11 05:31:46 PM PDT 24
Peak memory 217852 kb
Host smart-d4a3be43-b67c-4071-af1d-8b0392fa8e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672470104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.672470104
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.4066332217
Short name T1145
Test name
Test status
Simulation time 2256198094 ps
CPU time 6.38 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:31:43 PM PDT 24
Peak memory 222100 kb
Host smart-08551356-ea98-42a1-a744-f3a28267e46b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066332217 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.4066332217
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1107958574
Short name T291
Test name
Test status
Simulation time 277863443 ps
CPU time 0.9 seconds
Started Aug 11 05:31:32 PM PDT 24
Finished Aug 11 05:31:33 PM PDT 24
Peak memory 205440 kb
Host smart-683ecfe1-10dc-4920-9c98-73fb330b5d4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107958574 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1107958574
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1746482547
Short name T1384
Test name
Test status
Simulation time 381529331 ps
CPU time 1.06 seconds
Started Aug 11 05:31:35 PM PDT 24
Finished Aug 11 05:31:36 PM PDT 24
Peak memory 205408 kb
Host smart-f5bbebb6-dbed-472b-a2fd-38bbca0c1783
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746482547 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1746482547
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.3002007643
Short name T1410
Test name
Test status
Simulation time 3158219944 ps
CPU time 2.69 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:31:40 PM PDT 24
Peak memory 205720 kb
Host smart-4e3546c6-384d-4dbf-b151-bc318538ea4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002007643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.3002007643
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.1043295094
Short name T1134
Test name
Test status
Simulation time 62145708 ps
CPU time 0.89 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:31:38 PM PDT 24
Peak memory 205352 kb
Host smart-27f6ad66-de1c-45ea-b134-1212496918ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043295094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.1043295094
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.3564010881
Short name T1228
Test name
Test status
Simulation time 547560017 ps
CPU time 1.85 seconds
Started Aug 11 05:31:39 PM PDT 24
Finished Aug 11 05:31:41 PM PDT 24
Peak memory 205628 kb
Host smart-8e51eae5-7a4b-4df2-8b4c-afdd86e419a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564010881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.3564010881
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1936246928
Short name T1238
Test name
Test status
Simulation time 6623472025 ps
CPU time 6.61 seconds
Started Aug 11 05:31:36 PM PDT 24
Finished Aug 11 05:31:42 PM PDT 24
Peak memory 222132 kb
Host smart-4f9c688d-716e-4d98-8b47-733512b6921d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936246928 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1936246928
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.4197072075
Short name T1434
Test name
Test status
Simulation time 22598608290 ps
CPU time 651.81 seconds
Started Aug 11 05:31:32 PM PDT 24
Finished Aug 11 05:42:24 PM PDT 24
Peak memory 5314340 kb
Host smart-9efa4693-a13f-4199-959e-38cba67caf70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197072075 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.4197072075
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull.1654612321
Short name T727
Test name
Test status
Simulation time 3578804526 ps
CPU time 2.63 seconds
Started Aug 11 05:31:38 PM PDT 24
Finished Aug 11 05:31:41 PM PDT 24
Peak memory 213952 kb
Host smart-ff6eeae9-d18a-4d70-8c00-49d0038af7d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654612321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_acqfull.1654612321
Directory /workspace/34.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/34.i2c_target_nack_acqfull_addr.1777210630
Short name T812
Test name
Test status
Simulation time 1547190797 ps
CPU time 2.54 seconds
Started Aug 11 05:31:38 PM PDT 24
Finished Aug 11 05:31:41 PM PDT 24
Peak memory 205648 kb
Host smart-88c56da9-728a-4a7d-b610-7b1068a6beb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777210630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.1777210630
Directory /workspace/34.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/34.i2c_target_nack_txstretch.3318563771
Short name T48
Test name
Test status
Simulation time 195378494 ps
CPU time 1.54 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:31:39 PM PDT 24
Peak memory 222444 kb
Host smart-350464fd-b96c-4746-b2ba-e61cd2b902a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318563771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_nack_txstretch.3318563771
Directory /workspace/34.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/34.i2c_target_perf.82776964
Short name T612
Test name
Test status
Simulation time 2348642840 ps
CPU time 5.02 seconds
Started Aug 11 05:31:32 PM PDT 24
Finished Aug 11 05:31:37 PM PDT 24
Peak memory 221256 kb
Host smart-9e413e63-5e88-4909-84d2-3dbb4d911981
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82776964 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.i2c_target_perf.82776964
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smbus_maxlen.2009638104
Short name T385
Test name
Test status
Simulation time 1665774414 ps
CPU time 2.14 seconds
Started Aug 11 05:31:36 PM PDT 24
Finished Aug 11 05:31:38 PM PDT 24
Peak memory 205468 kb
Host smart-9690c457-21f2-4986-ac97-689b0e756da0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009638104 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_smbus_maxlen.2009638104
Directory /workspace/34.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3109649067
Short name T1028
Test name
Test status
Simulation time 1671987679 ps
CPU time 10.45 seconds
Started Aug 11 05:31:34 PM PDT 24
Finished Aug 11 05:31:45 PM PDT 24
Peak memory 213916 kb
Host smart-aa8c4aa0-8d1c-4a0d-9ce7-71b68a5f649d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109649067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3109649067
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.3510553680
Short name T900
Test name
Test status
Simulation time 37652454958 ps
CPU time 100.94 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:33:18 PM PDT 24
Peak memory 834488 kb
Host smart-99324dd4-f000-4623-82a7-007ec6428dd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510553680 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_stress_all.3510553680
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.1602470037
Short name T828
Test name
Test status
Simulation time 830406378 ps
CPU time 14.02 seconds
Started Aug 11 05:31:31 PM PDT 24
Finished Aug 11 05:31:46 PM PDT 24
Peak memory 217276 kb
Host smart-dcba8061-b095-4a53-a38e-df3f4bb8a4ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602470037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.1602470037
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2132491330
Short name T1712
Test name
Test status
Simulation time 40917247462 ps
CPU time 703.73 seconds
Started Aug 11 05:31:32 PM PDT 24
Finished Aug 11 05:43:16 PM PDT 24
Peak memory 5336552 kb
Host smart-c61d6dbe-33fd-42d7-a3e1-922da8e66b35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132491330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2132491330
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.4196343862
Short name T293
Test name
Test status
Simulation time 1537322694 ps
CPU time 31.88 seconds
Started Aug 11 05:31:35 PM PDT 24
Finished Aug 11 05:32:07 PM PDT 24
Peak memory 347784 kb
Host smart-a62ee9a4-36ac-4d39-b185-24daa5a3b688
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196343862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.4196343862
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2077503274
Short name T472
Test name
Test status
Simulation time 4902893673 ps
CPU time 7.12 seconds
Started Aug 11 05:31:33 PM PDT 24
Finished Aug 11 05:31:40 PM PDT 24
Peak memory 222180 kb
Host smart-f17451fa-6288-4931-865b-d629af0e102d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077503274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2077503274
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.3464633385
Short name T441
Test name
Test status
Simulation time 89198648 ps
CPU time 2.05 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:31:39 PM PDT 24
Peak memory 205700 kb
Host smart-990f5ed4-4389-4df1-b044-3e99239942ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464633385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.3464633385
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2279621307
Short name T116
Test name
Test status
Simulation time 48679949 ps
CPU time 0.65 seconds
Started Aug 11 05:31:52 PM PDT 24
Finished Aug 11 05:31:53 PM PDT 24
Peak memory 204784 kb
Host smart-3e7d8491-d489-47f8-987c-875bc727d3a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279621307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2279621307
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3553118814
Short name T1719
Test name
Test status
Simulation time 360850527 ps
CPU time 1.35 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:31:38 PM PDT 24
Peak memory 213744 kb
Host smart-cb77b98a-786c-4b54-bc3e-86cd42b729b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553118814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3553118814
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.553259371
Short name T1382
Test name
Test status
Simulation time 1580990322 ps
CPU time 18.79 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:31:56 PM PDT 24
Peak memory 289272 kb
Host smart-1aff7cc4-a7d9-4065-8141-e99e1f5d8cae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553259371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empt
y.553259371
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3501267565
Short name T75
Test name
Test status
Simulation time 4045305272 ps
CPU time 127.84 seconds
Started Aug 11 05:31:40 PM PDT 24
Finished Aug 11 05:33:48 PM PDT 24
Peak memory 577924 kb
Host smart-8dcab2f9-6871-4163-987d-4191ba089a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501267565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3501267565
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.820843247
Short name T1305
Test name
Test status
Simulation time 509691285 ps
CPU time 1.27 seconds
Started Aug 11 05:31:40 PM PDT 24
Finished Aug 11 05:31:41 PM PDT 24
Peak memory 205492 kb
Host smart-a7f7c9ff-ed51-4cd2-a694-dfdd1e3113e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820843247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fm
t.820843247
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2864275832
Short name T1540
Test name
Test status
Simulation time 213580215 ps
CPU time 4 seconds
Started Aug 11 05:31:38 PM PDT 24
Finished Aug 11 05:31:42 PM PDT 24
Peak memory 231832 kb
Host smart-4f9f2e4b-24ff-4d27-af5e-1ab528f7809c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864275832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2864275832
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1233044053
Short name T858
Test name
Test status
Simulation time 10350219647 ps
CPU time 154.46 seconds
Started Aug 11 05:31:40 PM PDT 24
Finished Aug 11 05:34:14 PM PDT 24
Peak memory 827056 kb
Host smart-5f2cb2c1-d41f-4df5-8f29-eeefd1a157f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233044053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1233044053
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1663840530
Short name T1420
Test name
Test status
Simulation time 1645352780 ps
CPU time 6.72 seconds
Started Aug 11 05:32:04 PM PDT 24
Finished Aug 11 05:32:11 PM PDT 24
Peak memory 205520 kb
Host smart-fca71c69-49bd-4fc7-8c68-e694b3ffd9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663840530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1663840530
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_override.1601066617
Short name T1179
Test name
Test status
Simulation time 53300103 ps
CPU time 0.7 seconds
Started Aug 11 05:31:39 PM PDT 24
Finished Aug 11 05:31:40 PM PDT 24
Peak memory 205168 kb
Host smart-fc5a35ea-3804-456b-98b1-47204622b778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601066617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1601066617
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2224195459
Short name T1218
Test name
Test status
Simulation time 49339701304 ps
CPU time 552.54 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:40:49 PM PDT 24
Peak memory 476208 kb
Host smart-1c4e270c-e4ef-4312-945f-ac4df2f030d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224195459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2224195459
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.2306267272
Short name T1181
Test name
Test status
Simulation time 40592829 ps
CPU time 1.99 seconds
Started Aug 11 05:31:37 PM PDT 24
Finished Aug 11 05:31:39 PM PDT 24
Peak memory 214336 kb
Host smart-4b86e3ca-582b-461e-ad95-034fc4501454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306267272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2306267272
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3718895707
Short name T1357
Test name
Test status
Simulation time 10214496987 ps
CPU time 33.18 seconds
Started Aug 11 05:31:46 PM PDT 24
Finished Aug 11 05:32:19 PM PDT 24
Peak memory 388196 kb
Host smart-bb52b96e-0aa0-4a0a-8d87-aa42a7f4fddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718895707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3718895707
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.3679214388
Short name T838
Test name
Test status
Simulation time 2511163687 ps
CPU time 10.65 seconds
Started Aug 11 05:31:36 PM PDT 24
Finished Aug 11 05:31:47 PM PDT 24
Peak memory 221268 kb
Host smart-d1d94829-404a-416f-ad32-b6104add7ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679214388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.3679214388
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2713141754
Short name T520
Test name
Test status
Simulation time 1852789319 ps
CPU time 6.67 seconds
Started Aug 11 05:31:50 PM PDT 24
Finished Aug 11 05:31:57 PM PDT 24
Peak memory 213892 kb
Host smart-a1d0209a-fb69-4d1c-a4f8-d0fbac04d696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713141754 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2713141754
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3836587113
Short name T1560
Test name
Test status
Simulation time 207685170 ps
CPU time 1.35 seconds
Started Aug 11 05:31:44 PM PDT 24
Finished Aug 11 05:31:45 PM PDT 24
Peak memory 213664 kb
Host smart-51e663b2-c94f-4def-a945-9a5584023f48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836587113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3836587113
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2286943147
Short name T310
Test name
Test status
Simulation time 736755152 ps
CPU time 1.5 seconds
Started Aug 11 05:31:46 PM PDT 24
Finished Aug 11 05:31:47 PM PDT 24
Peak memory 205540 kb
Host smart-fa1dcb25-6c5e-4bb6-888a-8885c90c7008
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286943147 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2286943147
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.1791531805
Short name T1603
Test name
Test status
Simulation time 349075130 ps
CPU time 1.99 seconds
Started Aug 11 05:31:50 PM PDT 24
Finished Aug 11 05:31:52 PM PDT 24
Peak memory 205380 kb
Host smart-65d1a176-8606-49cf-8d08-f483236d8c5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791531805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.1791531805
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.3189983825
Short name T1006
Test name
Test status
Simulation time 1154737003 ps
CPU time 1.55 seconds
Started Aug 11 05:31:51 PM PDT 24
Finished Aug 11 05:31:52 PM PDT 24
Peak memory 205460 kb
Host smart-e922ea53-1168-4d1a-9444-d637cd4fde2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189983825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.3189983825
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.205506117
Short name T45
Test name
Test status
Simulation time 457787591 ps
CPU time 2.71 seconds
Started Aug 11 05:31:52 PM PDT 24
Finished Aug 11 05:31:55 PM PDT 24
Peak memory 213840 kb
Host smart-1aa6f3b0-1bff-44f6-82a1-715e6fd81613
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205506117 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.205506117
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2551799876
Short name T489
Test name
Test status
Simulation time 1033487218 ps
CPU time 6.02 seconds
Started Aug 11 05:31:51 PM PDT 24
Finished Aug 11 05:31:57 PM PDT 24
Peak memory 213720 kb
Host smart-eb26f4d4-b5a4-482e-8cce-e701da9e1fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551799876 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2551799876
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.4193713511
Short name T1677
Test name
Test status
Simulation time 8224243757 ps
CPU time 5.25 seconds
Started Aug 11 05:31:46 PM PDT 24
Finished Aug 11 05:31:51 PM PDT 24
Peak memory 294140 kb
Host smart-f283d776-80b9-4019-b6bd-2b9d39cca1aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193713511 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.4193713511
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull.3828288025
Short name T1138
Test name
Test status
Simulation time 575660075 ps
CPU time 3.3 seconds
Started Aug 11 05:31:53 PM PDT 24
Finished Aug 11 05:31:56 PM PDT 24
Peak memory 213772 kb
Host smart-51fdc087-3443-4f6b-90ae-b193e9d945f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828288025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_nack_acqfull.3828288025
Directory /workspace/35.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/35.i2c_target_nack_acqfull_addr.3662935871
Short name T1735
Test name
Test status
Simulation time 810612235 ps
CPU time 2.39 seconds
Started Aug 11 05:31:52 PM PDT 24
Finished Aug 11 05:31:55 PM PDT 24
Peak memory 205628 kb
Host smart-ddf90f20-51cf-43df-a499-5ac87ed0f16b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662935871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.3662935871
Directory /workspace/35.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/35.i2c_target_nack_txstretch.2515602009
Short name T1244
Test name
Test status
Simulation time 595338879 ps
CPU time 1.38 seconds
Started Aug 11 05:32:05 PM PDT 24
Finished Aug 11 05:32:06 PM PDT 24
Peak memory 222320 kb
Host smart-91970649-297a-4ae4-861c-54c6033d2174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515602009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_nack_txstretch.2515602009
Directory /workspace/35.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/35.i2c_target_perf.984046559
Short name T854
Test name
Test status
Simulation time 2724981908 ps
CPU time 4.5 seconds
Started Aug 11 05:31:49 PM PDT 24
Finished Aug 11 05:31:53 PM PDT 24
Peak memory 216604 kb
Host smart-d436b374-4c82-4d31-b580-402e857017c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984046559 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_perf.984046559
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smbus_maxlen.146280336
Short name T119
Test name
Test status
Simulation time 362466051 ps
CPU time 1.91 seconds
Started Aug 11 05:31:52 PM PDT 24
Finished Aug 11 05:31:54 PM PDT 24
Peak memory 205400 kb
Host smart-6a50ffd1-52ca-4f88-b41a-d0d4d08edfba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146280336 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_smbus_maxlen.146280336
Directory /workspace/35.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.4264166702
Short name T49
Test name
Test status
Simulation time 7854208997 ps
CPU time 12.89 seconds
Started Aug 11 05:31:38 PM PDT 24
Finished Aug 11 05:31:51 PM PDT 24
Peak memory 214228 kb
Host smart-96ee248b-54b3-4ee1-88e2-276ff0abc2b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264166702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.4264166702
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.1693320077
Short name T1034
Test name
Test status
Simulation time 44314863286 ps
CPU time 93.41 seconds
Started Aug 11 05:31:50 PM PDT 24
Finished Aug 11 05:33:23 PM PDT 24
Peak memory 925588 kb
Host smart-157a648c-11c8-420a-bd5f-57f815209c13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693320077 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_stress_all.1693320077
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1183004989
Short name T755
Test name
Test status
Simulation time 2586612109 ps
CPU time 12.66 seconds
Started Aug 11 05:31:42 PM PDT 24
Finished Aug 11 05:31:55 PM PDT 24
Peak memory 216360 kb
Host smart-448cc425-18cc-4039-9334-74df8e78b984
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183004989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1183004989
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2924435878
Short name T605
Test name
Test status
Simulation time 32517383121 ps
CPU time 46.42 seconds
Started Aug 11 05:31:45 PM PDT 24
Finished Aug 11 05:32:32 PM PDT 24
Peak memory 906972 kb
Host smart-4cadc808-4c78-488c-8e89-a9548a05db4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924435878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2924435878
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.194133251
Short name T1526
Test name
Test status
Simulation time 1614899507 ps
CPU time 66.9 seconds
Started Aug 11 05:31:44 PM PDT 24
Finished Aug 11 05:32:51 PM PDT 24
Peak memory 547220 kb
Host smart-1034d3f8-8669-492d-9183-23507faae05f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194133251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.194133251
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.211422845
Short name T1582
Test name
Test status
Simulation time 1216281323 ps
CPU time 7.08 seconds
Started Aug 11 05:31:44 PM PDT 24
Finished Aug 11 05:31:51 PM PDT 24
Peak memory 213760 kb
Host smart-e96d633e-6e97-405f-9076-63914825d103
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211422845 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.211422845
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.2476750938
Short name T447
Test name
Test status
Simulation time 161271136 ps
CPU time 2.9 seconds
Started Aug 11 05:31:49 PM PDT 24
Finished Aug 11 05:31:52 PM PDT 24
Peak memory 205636 kb
Host smart-dc884e7f-f151-40c0-880b-e61b134d7c48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476750938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2476750938
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.1265082930
Short name T1232
Test name
Test status
Simulation time 38530792 ps
CPU time 0.62 seconds
Started Aug 11 05:31:56 PM PDT 24
Finished Aug 11 05:31:57 PM PDT 24
Peak memory 204744 kb
Host smart-819a0781-8d14-408c-bf6a-1291241dc1d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265082930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1265082930
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.451790515
Short name T1584
Test name
Test status
Simulation time 358768858 ps
CPU time 1.45 seconds
Started Aug 11 05:31:50 PM PDT 24
Finished Aug 11 05:31:51 PM PDT 24
Peak memory 213780 kb
Host smart-6f7d50f4-c4f5-4380-a346-3d54afbb08a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451790515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.451790515
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1919079778
Short name T636
Test name
Test status
Simulation time 518643447 ps
CPU time 12.31 seconds
Started Aug 11 05:32:05 PM PDT 24
Finished Aug 11 05:32:17 PM PDT 24
Peak memory 324796 kb
Host smart-15e974db-caca-45a7-bf5a-a3e05843538a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919079778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.1919079778
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2554408663
Short name T992
Test name
Test status
Simulation time 31327176351 ps
CPU time 129.21 seconds
Started Aug 11 05:31:51 PM PDT 24
Finished Aug 11 05:34:01 PM PDT 24
Peak memory 471004 kb
Host smart-04e45817-da4a-463e-8b48-0b25cfd3a989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554408663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2554408663
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.2692819876
Short name T849
Test name
Test status
Simulation time 2499504557 ps
CPU time 185.73 seconds
Started Aug 11 05:32:05 PM PDT 24
Finished Aug 11 05:35:11 PM PDT 24
Peak memory 809796 kb
Host smart-d4f85f25-0eb6-4873-869d-8deb94b8e4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692819876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2692819876
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3058046718
Short name T871
Test name
Test status
Simulation time 92690279 ps
CPU time 0.99 seconds
Started Aug 11 05:31:53 PM PDT 24
Finished Aug 11 05:31:54 PM PDT 24
Peak memory 205160 kb
Host smart-c5288089-7e8d-4ee3-9a28-eb2c2a559304
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058046718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3058046718
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2404937474
Short name T41
Test name
Test status
Simulation time 200974595 ps
CPU time 5.03 seconds
Started Aug 11 05:32:05 PM PDT 24
Finished Aug 11 05:32:10 PM PDT 24
Peak memory 205556 kb
Host smart-92d5b1d2-178d-40ff-ad18-fabeb1d0bde0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404937474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2404937474
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1525255724
Short name T573
Test name
Test status
Simulation time 8327022818 ps
CPU time 293.3 seconds
Started Aug 11 05:31:48 PM PDT 24
Finished Aug 11 05:36:41 PM PDT 24
Peak memory 1244016 kb
Host smart-9fd03c2b-1d01-4229-a79c-c1cfc44da82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525255724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1525255724
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1336587600
Short name T259
Test name
Test status
Simulation time 1047251228 ps
CPU time 7.01 seconds
Started Aug 11 05:31:59 PM PDT 24
Finished Aug 11 05:32:06 PM PDT 24
Peak memory 205444 kb
Host smart-7d939621-c688-428b-b772-79345094ec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336587600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1336587600
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.2477017746
Short name T529
Test name
Test status
Simulation time 80212766 ps
CPU time 0.69 seconds
Started Aug 11 05:31:52 PM PDT 24
Finished Aug 11 05:31:53 PM PDT 24
Peak memory 205260 kb
Host smart-5b9a4cdf-6e34-4ec5-b3c1-8838dd7f4a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477017746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2477017746
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3639193299
Short name T494
Test name
Test status
Simulation time 24337093670 ps
CPU time 642.91 seconds
Started Aug 11 05:31:50 PM PDT 24
Finished Aug 11 05:42:34 PM PDT 24
Peak memory 2876604 kb
Host smart-87d093b4-f4bf-4816-9227-f4b0e28fa938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639193299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3639193299
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.46138554
Short name T761
Test name
Test status
Simulation time 23284458693 ps
CPU time 224.5 seconds
Started Aug 11 05:31:50 PM PDT 24
Finished Aug 11 05:35:34 PM PDT 24
Peak memory 205504 kb
Host smart-a608920e-198e-4251-97c7-0253b1c75c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46138554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.46138554
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1175337307
Short name T836
Test name
Test status
Simulation time 1463560929 ps
CPU time 25.21 seconds
Started Aug 11 05:31:50 PM PDT 24
Finished Aug 11 05:32:16 PM PDT 24
Peak memory 366224 kb
Host smart-3923119b-4316-4b26-83f5-39c85ab47230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175337307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1175337307
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.877722947
Short name T830
Test name
Test status
Simulation time 795089050 ps
CPU time 13.4 seconds
Started Aug 11 05:31:51 PM PDT 24
Finished Aug 11 05:32:04 PM PDT 24
Peak memory 218336 kb
Host smart-5c6c995d-095b-4418-abb0-c122d1f23153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877722947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.877722947
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1972042445
Short name T1165
Test name
Test status
Simulation time 9623005521 ps
CPU time 6 seconds
Started Aug 11 05:31:59 PM PDT 24
Finished Aug 11 05:32:05 PM PDT 24
Peak memory 213920 kb
Host smart-d70337b7-c6ac-4046-8eb8-935291e66e60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972042445 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1972042445
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2138592479
Short name T840
Test name
Test status
Simulation time 195896838 ps
CPU time 1.35 seconds
Started Aug 11 05:31:57 PM PDT 24
Finished Aug 11 05:31:59 PM PDT 24
Peak memory 205656 kb
Host smart-0203280c-56f4-43aa-9dd7-91c7d71dcecf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138592479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2138592479
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.751386688
Short name T794
Test name
Test status
Simulation time 218032331 ps
CPU time 1.34 seconds
Started Aug 11 05:31:57 PM PDT 24
Finished Aug 11 05:31:58 PM PDT 24
Peak memory 205464 kb
Host smart-dcef7580-fb1d-4edc-9380-850228a2bf85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751386688 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.751386688
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.916430780
Short name T1506
Test name
Test status
Simulation time 1161159899 ps
CPU time 1.5 seconds
Started Aug 11 05:31:55 PM PDT 24
Finished Aug 11 05:31:57 PM PDT 24
Peak memory 205396 kb
Host smart-4213a478-63d2-435e-8061-a522561fa321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916430780 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.916430780
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.2958571072
Short name T347
Test name
Test status
Simulation time 651923377 ps
CPU time 0.99 seconds
Started Aug 11 05:31:59 PM PDT 24
Finished Aug 11 05:32:00 PM PDT 24
Peak memory 205400 kb
Host smart-8d5a9609-c96c-4668-b8cd-cbc54dc9d633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958571072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.2958571072
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.376275647
Short name T1706
Test name
Test status
Simulation time 304378656 ps
CPU time 2.1 seconds
Started Aug 11 05:31:59 PM PDT 24
Finished Aug 11 05:32:01 PM PDT 24
Peak memory 213864 kb
Host smart-e2676454-7ddb-42a0-a078-438c10ba6304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376275647 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.376275647
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.1855350754
Short name T1701
Test name
Test status
Simulation time 4528723744 ps
CPU time 5.24 seconds
Started Aug 11 05:31:56 PM PDT 24
Finished Aug 11 05:32:01 PM PDT 24
Peak memory 213968 kb
Host smart-7a431000-5d85-46c7-891e-6b020c516fb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855350754 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.1855350754
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.1269708239
Short name T576
Test name
Test status
Simulation time 22608020512 ps
CPU time 138.76 seconds
Started Aug 11 05:31:55 PM PDT 24
Finished Aug 11 05:34:14 PM PDT 24
Peak memory 2162048 kb
Host smart-26951467-914e-4ada-aeed-937a33b74f01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269708239 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.1269708239
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull.2353596137
Short name T66
Test name
Test status
Simulation time 1755168922 ps
CPU time 2.68 seconds
Started Aug 11 05:31:59 PM PDT 24
Finished Aug 11 05:32:01 PM PDT 24
Peak memory 213860 kb
Host smart-1d018a0c-bd10-42f5-84fb-6a4160158875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353596137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_nack_acqfull.2353596137
Directory /workspace/36.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/36.i2c_target_nack_acqfull_addr.1352116523
Short name T643
Test name
Test status
Simulation time 1865280174 ps
CPU time 2.43 seconds
Started Aug 11 05:31:59 PM PDT 24
Finished Aug 11 05:32:01 PM PDT 24
Peak memory 205616 kb
Host smart-df25c0e9-bd9b-4787-a61f-828ae7002acd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352116523 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_nack_acqfull_addr.1352116523
Directory /workspace/36.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/36.i2c_target_nack_txstretch.466435789
Short name T1464
Test name
Test status
Simulation time 133433253 ps
CPU time 1.42 seconds
Started Aug 11 05:31:56 PM PDT 24
Finished Aug 11 05:31:58 PM PDT 24
Peak memory 222212 kb
Host smart-9b189663-5abd-48d0-958e-13efa2d0cb06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466435789 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_nack_txstretch.466435789
Directory /workspace/36.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/36.i2c_target_perf.2093108767
Short name T585
Test name
Test status
Simulation time 6893779593 ps
CPU time 5.31 seconds
Started Aug 11 05:31:57 PM PDT 24
Finished Aug 11 05:32:03 PM PDT 24
Peak memory 222048 kb
Host smart-410d3317-72b8-4c5d-97d8-7d5ce992b2d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093108767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.2093108767
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smbus_maxlen.345035233
Short name T314
Test name
Test status
Simulation time 429469951 ps
CPU time 2.26 seconds
Started Aug 11 05:31:58 PM PDT 24
Finished Aug 11 05:32:01 PM PDT 24
Peak memory 205484 kb
Host smart-b17db5ac-bce8-47a1-b825-dbb587ffd142
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345035233 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_smbus_maxlen.345035233
Directory /workspace/36.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3394865410
Short name T570
Test name
Test status
Simulation time 4070503084 ps
CPU time 33.57 seconds
Started Aug 11 05:31:51 PM PDT 24
Finished Aug 11 05:32:25 PM PDT 24
Peak memory 213928 kb
Host smart-796d6cb9-4138-4fe1-828b-1529fdda193e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394865410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3394865410
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.1462508846
Short name T1412
Test name
Test status
Simulation time 62780653514 ps
CPU time 2022.9 seconds
Started Aug 11 05:31:57 PM PDT 24
Finished Aug 11 06:05:41 PM PDT 24
Peak memory 10759712 kb
Host smart-82d7a77e-1269-4942-9558-2778c9877067
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462508846 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.1462508846
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2578009918
Short name T1467
Test name
Test status
Simulation time 5067666190 ps
CPU time 26.99 seconds
Started Aug 11 05:32:05 PM PDT 24
Finished Aug 11 05:32:32 PM PDT 24
Peak memory 234300 kb
Host smart-a959c948-60a7-45b7-bddb-2e931dd137a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578009918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2578009918
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2010335498
Short name T1675
Test name
Test status
Simulation time 47282474378 ps
CPU time 1021.82 seconds
Started Aug 11 05:31:51 PM PDT 24
Finished Aug 11 05:48:53 PM PDT 24
Peak memory 6848668 kb
Host smart-c6cc2778-5af9-450d-9a38-84daa99e4b0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010335498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2010335498
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2835824965
Short name T359
Test name
Test status
Simulation time 13753824223 ps
CPU time 7.27 seconds
Started Aug 11 05:31:56 PM PDT 24
Finished Aug 11 05:32:03 PM PDT 24
Peak memory 222056 kb
Host smart-16522534-91ad-4322-8752-6ed736632118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835824965 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2835824965
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.2637090539
Short name T1350
Test name
Test status
Simulation time 760607898 ps
CPU time 9.45 seconds
Started Aug 11 05:32:04 PM PDT 24
Finished Aug 11 05:32:13 PM PDT 24
Peak memory 205556 kb
Host smart-bd253eff-0580-4fc2-adc4-7ea1486f051b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637090539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.2637090539
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.1145312424
Short name T651
Test name
Test status
Simulation time 16209796 ps
CPU time 0.6 seconds
Started Aug 11 05:32:06 PM PDT 24
Finished Aug 11 05:32:07 PM PDT 24
Peak memory 204664 kb
Host smart-02bd0fe2-9ab8-4bea-b34e-880e930c818f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145312424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1145312424
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.618001241
Short name T901
Test name
Test status
Simulation time 482181508 ps
CPU time 2.11 seconds
Started Aug 11 05:32:01 PM PDT 24
Finished Aug 11 05:32:04 PM PDT 24
Peak memory 213796 kb
Host smart-b7c784cd-66f9-4c5b-ad66-230958b22aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618001241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.618001241
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3849840013
Short name T953
Test name
Test status
Simulation time 1271496374 ps
CPU time 15.21 seconds
Started Aug 11 05:32:02 PM PDT 24
Finished Aug 11 05:32:17 PM PDT 24
Peak memory 265132 kb
Host smart-9a1def02-5273-4a3c-8f66-0953ef97b9a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849840013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3849840013
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.4271176303
Short name T1188
Test name
Test status
Simulation time 3398113955 ps
CPU time 92.33 seconds
Started Aug 11 05:32:02 PM PDT 24
Finished Aug 11 05:33:35 PM PDT 24
Peak memory 537184 kb
Host smart-a8a3c375-3ba7-442d-b1d7-3337232dd8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271176303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.4271176303
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.586379282
Short name T1575
Test name
Test status
Simulation time 1541235309 ps
CPU time 43.84 seconds
Started Aug 11 05:32:03 PM PDT 24
Finished Aug 11 05:32:47 PM PDT 24
Peak memory 526072 kb
Host smart-46ec0f81-4666-45c9-ba4b-b6b55d4cf89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586379282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.586379282
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.340941023
Short name T1318
Test name
Test status
Simulation time 305862628 ps
CPU time 1 seconds
Started Aug 11 05:32:04 PM PDT 24
Finished Aug 11 05:32:05 PM PDT 24
Peak memory 205224 kb
Host smart-ace35846-a38a-4b79-8234-f51cb4a413af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340941023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.340941023
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3859739077
Short name T430
Test name
Test status
Simulation time 1435400125 ps
CPU time 4.48 seconds
Started Aug 11 05:32:01 PM PDT 24
Finished Aug 11 05:32:06 PM PDT 24
Peak memory 205496 kb
Host smart-00fe2a8b-e349-41ec-8efd-91f5c2d10cfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859739077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3859739077
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.786258910
Short name T106
Test name
Test status
Simulation time 5328299264 ps
CPU time 103.9 seconds
Started Aug 11 05:32:01 PM PDT 24
Finished Aug 11 05:33:45 PM PDT 24
Peak memory 1279416 kb
Host smart-7ecc1bf8-7a24-4f1a-b4e0-87cba649204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786258910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.786258910
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.4264060534
Short name T21
Test name
Test status
Simulation time 1172910133 ps
CPU time 12.8 seconds
Started Aug 11 05:32:07 PM PDT 24
Finished Aug 11 05:32:20 PM PDT 24
Peak memory 205548 kb
Host smart-79f3b4db-937d-4499-ae0b-9f107f66d968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264060534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.4264060534
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.2518745766
Short name T935
Test name
Test status
Simulation time 81381305 ps
CPU time 1.79 seconds
Started Aug 11 05:32:11 PM PDT 24
Finished Aug 11 05:32:13 PM PDT 24
Peak memory 221912 kb
Host smart-efe120dd-121c-40ef-9d5d-5e70d5423038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518745766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.2518745766
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.1618098666
Short name T924
Test name
Test status
Simulation time 92041207 ps
CPU time 0.68 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:32:18 PM PDT 24
Peak memory 205028 kb
Host smart-8ff28904-08ba-468a-bcf1-2e3b03a56b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618098666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1618098666
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.4039780166
Short name T850
Test name
Test status
Simulation time 29069535596 ps
CPU time 231.21 seconds
Started Aug 11 05:32:02 PM PDT 24
Finished Aug 11 05:35:54 PM PDT 24
Peak memory 1508820 kb
Host smart-97cef0e9-d11f-4860-8377-c4929e06d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039780166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.4039780166
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.2993683138
Short name T1438
Test name
Test status
Simulation time 87590945 ps
CPU time 0.9 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:32:18 PM PDT 24
Peak memory 205064 kb
Host smart-45592eae-d940-4e69-87aa-327bd77884c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993683138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.2993683138
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3684802905
Short name T1311
Test name
Test status
Simulation time 4762159343 ps
CPU time 25.59 seconds
Started Aug 11 05:31:56 PM PDT 24
Finished Aug 11 05:32:21 PM PDT 24
Peak memory 406756 kb
Host smart-77f253a5-63f6-49ce-95a6-d35a66ba7795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684802905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3684802905
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.459644318
Short name T926
Test name
Test status
Simulation time 1291000026 ps
CPU time 28.15 seconds
Started Aug 11 05:32:01 PM PDT 24
Finished Aug 11 05:32:29 PM PDT 24
Peak memory 213736 kb
Host smart-596aaa8c-9026-4f69-9068-4ad53cd9cf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459644318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.459644318
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2369359768
Short name T1346
Test name
Test status
Simulation time 2951181343 ps
CPU time 7.8 seconds
Started Aug 11 05:32:07 PM PDT 24
Finished Aug 11 05:32:15 PM PDT 24
Peak memory 213904 kb
Host smart-33cc270f-56a3-44a2-bc38-94e19425a9a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369359768 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2369359768
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2994304441
Short name T44
Test name
Test status
Simulation time 1447388801 ps
CPU time 1.55 seconds
Started Aug 11 05:32:03 PM PDT 24
Finished Aug 11 05:32:05 PM PDT 24
Peak memory 205688 kb
Host smart-eef81fd8-39a6-4fe1-af47-547d0352b92f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994304441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.2994304441
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3529043440
Short name T694
Test name
Test status
Simulation time 147927304 ps
CPU time 1.15 seconds
Started Aug 11 05:32:03 PM PDT 24
Finished Aug 11 05:32:04 PM PDT 24
Peak memory 205440 kb
Host smart-3f3b306e-df4d-4af2-86ec-fe77f41de01d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529043440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3529043440
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.428755115
Short name T427
Test name
Test status
Simulation time 1200427338 ps
CPU time 3.44 seconds
Started Aug 11 05:32:10 PM PDT 24
Finished Aug 11 05:32:14 PM PDT 24
Peak memory 205524 kb
Host smart-37f80c1f-f48a-4ab5-b3da-af14f46d41ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428755115 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.428755115
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.2576922296
Short name T1395
Test name
Test status
Simulation time 269712555 ps
CPU time 1.55 seconds
Started Aug 11 05:32:07 PM PDT 24
Finished Aug 11 05:32:09 PM PDT 24
Peak memory 205472 kb
Host smart-83f68d0f-ce2b-45c5-bdb1-79fa9a0a2612
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576922296 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.2576922296
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.4168694104
Short name T378
Test name
Test status
Simulation time 1933876940 ps
CPU time 3.53 seconds
Started Aug 11 05:32:04 PM PDT 24
Finished Aug 11 05:32:08 PM PDT 24
Peak memory 213804 kb
Host smart-a436a715-3035-483a-9b6b-323adb1ae9b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168694104 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.4168694104
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.4254588098
Short name T1409
Test name
Test status
Simulation time 13476879991 ps
CPU time 38.36 seconds
Started Aug 11 05:32:03 PM PDT 24
Finished Aug 11 05:32:41 PM PDT 24
Peak memory 1112660 kb
Host smart-49907b88-32f3-46dd-a465-0ab922982f1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254588098 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.4254588098
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull.1224473120
Short name T543
Test name
Test status
Simulation time 1164860919 ps
CPU time 3.07 seconds
Started Aug 11 05:32:21 PM PDT 24
Finished Aug 11 05:32:24 PM PDT 24
Peak memory 213716 kb
Host smart-3c7027c5-2ba2-4e18-aaaa-4108ab42ff31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224473120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_nack_acqfull.1224473120
Directory /workspace/37.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/37.i2c_target_nack_acqfull_addr.1153627117
Short name T62
Test name
Test status
Simulation time 1182983881 ps
CPU time 2.69 seconds
Started Aug 11 05:32:21 PM PDT 24
Finished Aug 11 05:32:24 PM PDT 24
Peak memory 205560 kb
Host smart-270e057d-88a5-4c11-9997-e133614d2797
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153627117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_nack_acqfull_addr.1153627117
Directory /workspace/37.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/37.i2c_target_nack_txstretch.162889776
Short name T664
Test name
Test status
Simulation time 244647588 ps
CPU time 1.56 seconds
Started Aug 11 05:32:09 PM PDT 24
Finished Aug 11 05:32:11 PM PDT 24
Peak memory 222172 kb
Host smart-ff75061c-3226-4a89-bf1a-de971c035352
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162889776 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_nack_txstretch.162889776
Directory /workspace/37.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/37.i2c_target_perf.830787279
Short name T415
Test name
Test status
Simulation time 6728833442 ps
CPU time 4.53 seconds
Started Aug 11 05:32:03 PM PDT 24
Finished Aug 11 05:32:07 PM PDT 24
Peak memory 211524 kb
Host smart-6460e0e5-5854-44fc-b5b0-2f58bd6f905b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830787279 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_perf.830787279
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smbus_maxlen.3399779412
Short name T344
Test name
Test status
Simulation time 448165377 ps
CPU time 2.5 seconds
Started Aug 11 05:32:08 PM PDT 24
Finished Aug 11 05:32:11 PM PDT 24
Peak memory 205332 kb
Host smart-6ca4f7c2-e65e-4524-97ad-f4bf2d093cec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399779412 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_smbus_maxlen.3399779412
Directory /workspace/37.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3458740805
Short name T78
Test name
Test status
Simulation time 2839584059 ps
CPU time 9.94 seconds
Started Aug 11 05:32:01 PM PDT 24
Finished Aug 11 05:32:11 PM PDT 24
Peak memory 213876 kb
Host smart-b5aecc09-276e-4b32-98ef-0487c36ad5a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458740805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3458740805
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.3496131915
Short name T1038
Test name
Test status
Simulation time 31909210665 ps
CPU time 44.51 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:33:02 PM PDT 24
Peak memory 295704 kb
Host smart-53ffcb00-5a64-4b44-b0f4-a924916e0d2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496131915 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.3496131915
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1924756512
Short name T1720
Test name
Test status
Simulation time 3128863172 ps
CPU time 15.77 seconds
Started Aug 11 05:32:01 PM PDT 24
Finished Aug 11 05:32:17 PM PDT 24
Peak memory 221972 kb
Host smart-e6a34394-8db0-4380-b7e6-0586a3048c55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924756512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1924756512
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.251027032
Short name T718
Test name
Test status
Simulation time 10360544602 ps
CPU time 20.51 seconds
Started Aug 11 05:32:05 PM PDT 24
Finished Aug 11 05:32:25 PM PDT 24
Peak memory 205620 kb
Host smart-2d25cac2-0a40-421e-bf4a-a62d52904b98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251027032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_wr.251027032
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.2696545952
Short name T403
Test name
Test status
Simulation time 2852168959 ps
CPU time 6.89 seconds
Started Aug 11 05:32:02 PM PDT 24
Finished Aug 11 05:32:09 PM PDT 24
Peak memory 213884 kb
Host smart-67b3ff5e-45c5-4bba-87b9-c92f658a9f28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696545952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.2696545952
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1321999662
Short name T1494
Test name
Test status
Simulation time 13331924867 ps
CPU time 6.84 seconds
Started Aug 11 05:32:01 PM PDT 24
Finished Aug 11 05:32:08 PM PDT 24
Peak memory 222128 kb
Host smart-c3a26ef4-b04a-42cf-bfbd-351d1030955f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321999662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1321999662
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3547099636
Short name T1482
Test name
Test status
Simulation time 49924863 ps
CPU time 0.63 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:32:18 PM PDT 24
Peak memory 204704 kb
Host smart-c45502af-fab3-4bf9-809c-a15746102c35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547099636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3547099636
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3989975366
Short name T1741
Test name
Test status
Simulation time 414235134 ps
CPU time 10.34 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:32:29 PM PDT 24
Peak memory 214792 kb
Host smart-62abd3f2-298b-40cc-b49c-f55ffd9d9cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989975366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3989975366
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2603679284
Short name T1493
Test name
Test status
Simulation time 2905216191 ps
CPU time 16.64 seconds
Started Aug 11 05:32:07 PM PDT 24
Finished Aug 11 05:32:24 PM PDT 24
Peak memory 270512 kb
Host smart-d8f4f681-db66-4605-b02f-b9afbdd549dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603679284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2603679284
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2506499811
Short name T189
Test name
Test status
Simulation time 3490583213 ps
CPU time 124.78 seconds
Started Aug 11 05:32:06 PM PDT 24
Finished Aug 11 05:34:11 PM PDT 24
Peak memory 732448 kb
Host smart-676a02eb-51a3-4b4e-96fe-68c5ae833c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506499811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2506499811
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.840958915
Short name T779
Test name
Test status
Simulation time 11957301062 ps
CPU time 117.52 seconds
Started Aug 11 05:32:11 PM PDT 24
Finished Aug 11 05:34:09 PM PDT 24
Peak memory 926008 kb
Host smart-82c4516e-8e34-4f88-ae70-d54ab9e1ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840958915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.840958915
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.135772645
Short name T1453
Test name
Test status
Simulation time 349597454 ps
CPU time 1.07 seconds
Started Aug 11 05:32:07 PM PDT 24
Finished Aug 11 05:32:08 PM PDT 24
Peak memory 205284 kb
Host smart-f28d41dc-4002-4845-818a-e2ebcc0b08fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135772645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fm
t.135772645
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.648630525
Short name T590
Test name
Test status
Simulation time 797938811 ps
CPU time 3.58 seconds
Started Aug 11 05:32:08 PM PDT 24
Finished Aug 11 05:32:11 PM PDT 24
Peak memory 222412 kb
Host smart-c9ba4b8b-a6fb-455f-9e87-b8c285215701
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648630525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.
648630525
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1036115395
Short name T1248
Test name
Test status
Simulation time 15581306268 ps
CPU time 242.45 seconds
Started Aug 11 05:32:21 PM PDT 24
Finished Aug 11 05:36:24 PM PDT 24
Peak memory 1105112 kb
Host smart-dd72372d-8d2c-4fde-abcc-f33f8fe50833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036115395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1036115395
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.4121650865
Short name T1641
Test name
Test status
Simulation time 1170080095 ps
CPU time 24.64 seconds
Started Aug 11 05:32:19 PM PDT 24
Finished Aug 11 05:32:44 PM PDT 24
Peak memory 205508 kb
Host smart-084c932a-2330-49f7-af69-e23ef02bde16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121650865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.4121650865
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_override.3398367815
Short name T481
Test name
Test status
Simulation time 16665112 ps
CPU time 0.68 seconds
Started Aug 11 05:32:09 PM PDT 24
Finished Aug 11 05:32:10 PM PDT 24
Peak memory 205180 kb
Host smart-2415719f-bbe5-46bc-a576-3e215a4003ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398367815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3398367815
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2440732241
Short name T1485
Test name
Test status
Simulation time 1285552151 ps
CPU time 23.78 seconds
Started Aug 11 05:32:21 PM PDT 24
Finished Aug 11 05:32:45 PM PDT 24
Peak memory 262324 kb
Host smart-a058c585-2910-456f-98a2-f4a9026e34df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440732241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2440732241
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.2880599377
Short name T1088
Test name
Test status
Simulation time 23143882914 ps
CPU time 1791.88 seconds
Started Aug 11 05:32:21 PM PDT 24
Finished Aug 11 06:02:13 PM PDT 24
Peak memory 2087016 kb
Host smart-7cbd59e9-3591-4909-bed9-260b3ec564f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880599377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.2880599377
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.4211732144
Short name T1372
Test name
Test status
Simulation time 4321079193 ps
CPU time 27.96 seconds
Started Aug 11 05:32:21 PM PDT 24
Finished Aug 11 05:32:49 PM PDT 24
Peak memory 301700 kb
Host smart-38072c9f-da47-467e-a9f0-9696dd36ef81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211732144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.4211732144
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1036202941
Short name T613
Test name
Test status
Simulation time 1178502930 ps
CPU time 27.48 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:32:46 PM PDT 24
Peak memory 213788 kb
Host smart-3a38d828-5c00-4665-b8f0-da0afebbb955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036202941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1036202941
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.563143732
Short name T1448
Test name
Test status
Simulation time 2238845732 ps
CPU time 6.18 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:32:23 PM PDT 24
Peak memory 222144 kb
Host smart-fccf494a-83fa-424f-b137-994bd94f94d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563143732 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.563143732
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.175975265
Short name T1698
Test name
Test status
Simulation time 456587833 ps
CPU time 1.06 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:32:18 PM PDT 24
Peak memory 205344 kb
Host smart-ede3a17d-489c-43eb-88d7-f00535f4014c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175975265 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.175975265
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.2778127828
Short name T306
Test name
Test status
Simulation time 152295031 ps
CPU time 1.05 seconds
Started Aug 11 05:32:16 PM PDT 24
Finished Aug 11 05:32:17 PM PDT 24
Peak memory 205380 kb
Host smart-b6cb5c8c-e849-479c-9b12-fac77ad4026c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778127828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.2778127828
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.2706337089
Short name T1217
Test name
Test status
Simulation time 519122769 ps
CPU time 1.8 seconds
Started Aug 11 05:32:16 PM PDT 24
Finished Aug 11 05:32:18 PM PDT 24
Peak memory 205412 kb
Host smart-07713ce4-e70f-4abc-b4ef-a316f72442b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706337089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.2706337089
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.4152739234
Short name T829
Test name
Test status
Simulation time 306022529 ps
CPU time 1.31 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:32:20 PM PDT 24
Peak memory 205416 kb
Host smart-f762d807-d55f-4339-ae6a-a7f6db890413
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152739234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.4152739234
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.4215274837
Short name T1054
Test name
Test status
Simulation time 226581145 ps
CPU time 1.92 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:32:21 PM PDT 24
Peak memory 214684 kb
Host smart-6855d1fa-b287-42d4-a7c0-6271c3b4987e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215274837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.4215274837
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.1445396385
Short name T1159
Test name
Test status
Simulation time 2803468589 ps
CPU time 6.22 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:32:23 PM PDT 24
Peak memory 218836 kb
Host smart-9c914128-f8bf-46f7-b48e-26b5f34b23c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445396385 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.1445396385
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.38144805
Short name T1314
Test name
Test status
Simulation time 9085791138 ps
CPU time 16.48 seconds
Started Aug 11 05:32:16 PM PDT 24
Finished Aug 11 05:32:33 PM PDT 24
Peak memory 358652 kb
Host smart-3188712b-2f87-4636-b06b-626f8432fc7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144805 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.38144805
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull.3692775992
Short name T192
Test name
Test status
Simulation time 3942058426 ps
CPU time 2.94 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:32:21 PM PDT 24
Peak memory 213896 kb
Host smart-f6583f14-a16e-42fc-bf40-af04b805e631
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692775992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_nack_acqfull.3692775992
Directory /workspace/38.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/38.i2c_target_nack_acqfull_addr.1352193270
Short name T54
Test name
Test status
Simulation time 487230902 ps
CPU time 2.71 seconds
Started Aug 11 05:32:25 PM PDT 24
Finished Aug 11 05:32:28 PM PDT 24
Peak memory 206416 kb
Host smart-8fe82fd8-f220-4448-a46b-973091d53283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352193270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.1352193270
Directory /workspace/38.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.1851833497
Short name T1043
Test name
Test status
Simulation time 2662279760 ps
CPU time 5.13 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:32:23 PM PDT 24
Peak memory 219260 kb
Host smart-a5c723e1-849f-4060-9e5c-707ec276ed49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851833497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_perf.1851833497
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smbus_maxlen.1471299760
Short name T473
Test name
Test status
Simulation time 515707016 ps
CPU time 2.36 seconds
Started Aug 11 05:32:16 PM PDT 24
Finished Aug 11 05:32:18 PM PDT 24
Peak memory 205388 kb
Host smart-fe760f62-1f94-4511-8a71-c8b70d2b7148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471299760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_smbus_maxlen.1471299760
Directory /workspace/38.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3752619415
Short name T342
Test name
Test status
Simulation time 1323832990 ps
CPU time 21.26 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:32:39 PM PDT 24
Peak memory 213868 kb
Host smart-5d8c1e38-88f2-45e6-8586-43cb7e5c1c4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752619415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3752619415
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.617553130
Short name T383
Test name
Test status
Simulation time 68883470141 ps
CPU time 250.83 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:36:28 PM PDT 24
Peak memory 2350508 kb
Host smart-5a0417d3-ef92-47ee-9f2b-fe5857fd8ad5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617553130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_target_stress_all.617553130
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.2363109228
Short name T42
Test name
Test status
Simulation time 1363778004 ps
CPU time 22.22 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:32:40 PM PDT 24
Peak memory 239176 kb
Host smart-450c63c2-4d39-491f-9f5e-4bda0840be65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363109228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.2363109228
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.807057776
Short name T981
Test name
Test status
Simulation time 14768444632 ps
CPU time 11.63 seconds
Started Aug 11 05:32:16 PM PDT 24
Finished Aug 11 05:32:27 PM PDT 24
Peak memory 205716 kb
Host smart-aa5a4274-5cb3-404b-a341-7b4035514a94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807057776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_wr.807057776
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.79762794
Short name T640
Test name
Test status
Simulation time 5091974911 ps
CPU time 102.65 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:34:00 PM PDT 24
Peak memory 681084 kb
Host smart-d133f49c-e36f-4cf6-801f-06e2f6485ea8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79762794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_stretch.79762794
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.300736749
Short name T410
Test name
Test status
Simulation time 2586778297 ps
CPU time 6.86 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:32:25 PM PDT 24
Peak memory 213940 kb
Host smart-6e3db72a-adde-4108-9b60-d7274eb3ae5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300736749 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.300736749
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.246424137
Short name T515
Test name
Test status
Simulation time 69134990 ps
CPU time 1.64 seconds
Started Aug 11 05:32:16 PM PDT 24
Finished Aug 11 05:32:18 PM PDT 24
Peak memory 205616 kb
Host smart-a3899246-118e-4b3f-aa71-7aa717caee30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246424137 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.246424137
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.2452119091
Short name T1102
Test name
Test status
Simulation time 26114315 ps
CPU time 0.62 seconds
Started Aug 11 05:32:29 PM PDT 24
Finished Aug 11 05:32:29 PM PDT 24
Peak memory 204748 kb
Host smart-801f8831-b2bf-46ac-84ca-4856a70ab652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452119091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2452119091
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.1851416926
Short name T1308
Test name
Test status
Simulation time 388182447 ps
CPU time 2.64 seconds
Started Aug 11 05:32:26 PM PDT 24
Finished Aug 11 05:32:29 PM PDT 24
Peak memory 221308 kb
Host smart-93139fe7-54d3-420b-87dc-0e2471d6a6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851416926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1851416926
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.369675909
Short name T1497
Test name
Test status
Simulation time 327889880 ps
CPU time 17.04 seconds
Started Aug 11 05:32:17 PM PDT 24
Finished Aug 11 05:32:34 PM PDT 24
Peak memory 273784 kb
Host smart-1a6ceb2f-e7eb-4916-ac54-8e383c4524c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369675909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.369675909
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.302000052
Short name T382
Test name
Test status
Simulation time 3604480387 ps
CPU time 54.66 seconds
Started Aug 11 05:32:24 PM PDT 24
Finished Aug 11 05:33:19 PM PDT 24
Peak memory 240496 kb
Host smart-12edf927-23a2-40a6-b5f2-3f3fc132fb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302000052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.302000052
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.469851751
Short name T1377
Test name
Test status
Simulation time 3312790872 ps
CPU time 116.69 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:34:15 PM PDT 24
Peak memory 600176 kb
Host smart-35faddab-66c3-40cf-a95d-bad9bde048b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469851751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.469851751
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3960136648
Short name T480
Test name
Test status
Simulation time 117487864 ps
CPU time 0.88 seconds
Started Aug 11 05:32:19 PM PDT 24
Finished Aug 11 05:32:20 PM PDT 24
Peak memory 205208 kb
Host smart-c2d58d70-dd47-4963-8258-7947b0f8abb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960136648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3960136648
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2956585812
Short name T944
Test name
Test status
Simulation time 201198837 ps
CPU time 4.56 seconds
Started Aug 11 05:32:16 PM PDT 24
Finished Aug 11 05:32:21 PM PDT 24
Peak memory 242372 kb
Host smart-dd18b5f1-477f-4981-b550-ed32630b2ad7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956585812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2956585812
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3012711264
Short name T960
Test name
Test status
Simulation time 2592843529 ps
CPU time 144.22 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:34:42 PM PDT 24
Peak memory 817160 kb
Host smart-ec78bac1-88f7-4345-9b34-52b3e4383461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012711264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3012711264
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.1577867851
Short name T1122
Test name
Test status
Simulation time 495577665 ps
CPU time 5.46 seconds
Started Aug 11 05:32:23 PM PDT 24
Finished Aug 11 05:32:29 PM PDT 24
Peak memory 205512 kb
Host smart-09330b0d-ad5d-4f83-997a-b5b4f5615fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577867851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1577867851
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3779534357
Short name T1676
Test name
Test status
Simulation time 207275749 ps
CPU time 3.11 seconds
Started Aug 11 05:32:23 PM PDT 24
Finished Aug 11 05:32:26 PM PDT 24
Peak memory 213652 kb
Host smart-4708525f-466c-41f2-9da0-9ffc45925fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779534357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3779534357
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.986395056
Short name T139
Test name
Test status
Simulation time 109633287 ps
CPU time 0.66 seconds
Started Aug 11 05:32:18 PM PDT 24
Finished Aug 11 05:32:18 PM PDT 24
Peak memory 205288 kb
Host smart-76ae83d3-38a3-444f-ba7a-f89ee07b6d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986395056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.986395056
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2906171005
Short name T1655
Test name
Test status
Simulation time 1008783530 ps
CPU time 25.22 seconds
Started Aug 11 05:32:24 PM PDT 24
Finished Aug 11 05:32:50 PM PDT 24
Peak memory 213732 kb
Host smart-ca645cdd-d088-40ba-8c96-ec58bfc9f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906171005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2906171005
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.4115733426
Short name T451
Test name
Test status
Simulation time 41188483 ps
CPU time 1.32 seconds
Started Aug 11 05:32:26 PM PDT 24
Finished Aug 11 05:32:28 PM PDT 24
Peak memory 214368 kb
Host smart-fe50e527-e9d2-4273-9570-3925e70da279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115733426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.4115733426
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.3328579295
Short name T633
Test name
Test status
Simulation time 2656730982 ps
CPU time 26.97 seconds
Started Aug 11 05:32:20 PM PDT 24
Finished Aug 11 05:32:47 PM PDT 24
Peak memory 286768 kb
Host smart-74322453-f62b-4122-9ac5-bc40e67c9c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328579295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.3328579295
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.1747668301
Short name T534
Test name
Test status
Simulation time 1016680348 ps
CPU time 46.23 seconds
Started Aug 11 05:32:22 PM PDT 24
Finished Aug 11 05:33:08 PM PDT 24
Peak memory 221924 kb
Host smart-5ff06645-3407-4639-9129-f683a010ee58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747668301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1747668301
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.918835783
Short name T1664
Test name
Test status
Simulation time 866088269 ps
CPU time 4.16 seconds
Started Aug 11 05:32:27 PM PDT 24
Finished Aug 11 05:32:32 PM PDT 24
Peak memory 217728 kb
Host smart-548f1c5b-0d41-43e1-b3a9-b248e9abb9d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918835783 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.918835783
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1173610768
Short name T333
Test name
Test status
Simulation time 894506178 ps
CPU time 1.44 seconds
Started Aug 11 05:32:22 PM PDT 24
Finished Aug 11 05:32:24 PM PDT 24
Peak memory 205560 kb
Host smart-e19d10be-4462-4ca7-9b1c-dbc1800c15d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173610768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1173610768
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.2646383571
Short name T324
Test name
Test status
Simulation time 678980601 ps
CPU time 1.58 seconds
Started Aug 11 05:32:22 PM PDT 24
Finished Aug 11 05:32:24 PM PDT 24
Peak memory 205548 kb
Host smart-324a3aae-5ff6-41fc-94b8-c0047bdbeae4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646383571 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.2646383571
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.4116969933
Short name T545
Test name
Test status
Simulation time 439158797 ps
CPU time 2.3 seconds
Started Aug 11 05:32:26 PM PDT 24
Finished Aug 11 05:32:29 PM PDT 24
Peak memory 205632 kb
Host smart-8037a0e6-22f2-4ed5-b7a6-2b1038ddc762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116969933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.4116969933
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.2372864674
Short name T474
Test name
Test status
Simulation time 157714595 ps
CPU time 1.38 seconds
Started Aug 11 05:32:23 PM PDT 24
Finished Aug 11 05:32:25 PM PDT 24
Peak memory 205332 kb
Host smart-295777ed-a264-403b-8748-801bf8acf946
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372864674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.2372864674
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.4205574456
Short name T990
Test name
Test status
Simulation time 4350550928 ps
CPU time 6.24 seconds
Started Aug 11 05:32:26 PM PDT 24
Finished Aug 11 05:32:32 PM PDT 24
Peak memory 219668 kb
Host smart-165bb1ce-2fe5-404d-b3c9-91dc73571c2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205574456 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.4205574456
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.4119789641
Short name T952
Test name
Test status
Simulation time 5836629723 ps
CPU time 3.81 seconds
Started Aug 11 05:32:23 PM PDT 24
Finished Aug 11 05:32:27 PM PDT 24
Peak memory 205692 kb
Host smart-e86bcfa3-60e5-4b9a-9274-c68452ddec86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119789641 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.4119789641
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull.2546868498
Short name T1542
Test name
Test status
Simulation time 645813125 ps
CPU time 3.07 seconds
Started Aug 11 05:32:31 PM PDT 24
Finished Aug 11 05:32:34 PM PDT 24
Peak memory 213792 kb
Host smart-dcf2d577-7fb5-4b2a-a733-0f6a656344bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546868498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_nack_acqfull.2546868498
Directory /workspace/39.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/39.i2c_target_nack_acqfull_addr.3386904805
Short name T443
Test name
Test status
Simulation time 445694253 ps
CPU time 2.39 seconds
Started Aug 11 05:32:31 PM PDT 24
Finished Aug 11 05:32:34 PM PDT 24
Peak memory 206096 kb
Host smart-e4a18e94-602f-4490-aa2d-3bdb85ef4324
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386904805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.3386904805
Directory /workspace/39.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.3806079820
Short name T1666
Test name
Test status
Simulation time 1143288143 ps
CPU time 4.41 seconds
Started Aug 11 05:32:27 PM PDT 24
Finished Aug 11 05:32:32 PM PDT 24
Peak memory 221980 kb
Host smart-6d655b13-f11c-4af2-be78-304f594bff36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806079820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.3806079820
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smbus_maxlen.3113147915
Short name T1079
Test name
Test status
Simulation time 1864738922 ps
CPU time 2.16 seconds
Started Aug 11 05:32:32 PM PDT 24
Finished Aug 11 05:32:34 PM PDT 24
Peak memory 205668 kb
Host smart-3bbec606-3327-4187-bc9f-f73a262f8e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113147915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_smbus_maxlen.3113147915
Directory /workspace/39.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1418409033
Short name T955
Test name
Test status
Simulation time 738967287 ps
CPU time 8.38 seconds
Started Aug 11 05:32:22 PM PDT 24
Finished Aug 11 05:32:30 PM PDT 24
Peak memory 215072 kb
Host smart-cc4aeb87-ad88-4d50-a4e4-c169b33f9c9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418409033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1418409033
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.1748705953
Short name T274
Test name
Test status
Simulation time 38049182407 ps
CPU time 828.11 seconds
Started Aug 11 05:32:26 PM PDT 24
Finished Aug 11 05:46:15 PM PDT 24
Peak memory 5817284 kb
Host smart-2d053fd1-ad9d-4ce0-8029-8511098cbee5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748705953 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.1748705953
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.2291061406
Short name T697
Test name
Test status
Simulation time 1437129565 ps
CPU time 64.06 seconds
Started Aug 11 05:32:27 PM PDT 24
Finished Aug 11 05:33:31 PM PDT 24
Peak memory 214400 kb
Host smart-2026a38f-9500-415e-890d-ba170d301b26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291061406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.2291061406
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.4222824339
Short name T1042
Test name
Test status
Simulation time 21026034224 ps
CPU time 11.72 seconds
Started Aug 11 05:32:26 PM PDT 24
Finished Aug 11 05:32:38 PM PDT 24
Peak memory 206448 kb
Host smart-c09f34e2-f783-4af8-8978-47dd719aee17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222824339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.4222824339
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2582133050
Short name T1253
Test name
Test status
Simulation time 4318564084 ps
CPU time 5.87 seconds
Started Aug 11 05:32:23 PM PDT 24
Finished Aug 11 05:32:30 PM PDT 24
Peak memory 213852 kb
Host smart-9013b65a-0e8b-4cea-99e4-1fdb963c03ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582133050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2582133050
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.4163413627
Short name T846
Test name
Test status
Simulation time 83825441 ps
CPU time 1.83 seconds
Started Aug 11 05:32:32 PM PDT 24
Finished Aug 11 05:32:34 PM PDT 24
Peak memory 205648 kb
Host smart-0b42fe7f-7dc7-482e-a7a3-88372c721738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163413627 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.4163413627
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.1426693169
Short name T1302
Test name
Test status
Simulation time 34253973 ps
CPU time 0.61 seconds
Started Aug 11 05:26:19 PM PDT 24
Finished Aug 11 05:26:20 PM PDT 24
Peak memory 204728 kb
Host smart-705454e4-91e8-4520-a920-947d9a443461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426693169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.1426693169
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.3809395823
Short name T705
Test name
Test status
Simulation time 108866505 ps
CPU time 1.61 seconds
Started Aug 11 05:26:06 PM PDT 24
Finished Aug 11 05:26:08 PM PDT 24
Peak memory 213756 kb
Host smart-2f99f124-0d69-42aa-9c10-4883318c1f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809395823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3809395823
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2528818469
Short name T852
Test name
Test status
Simulation time 1362414409 ps
CPU time 11.54 seconds
Started Aug 11 05:26:07 PM PDT 24
Finished Aug 11 05:26:19 PM PDT 24
Peak memory 248716 kb
Host smart-ebb68f8c-80d9-4c77-97b8-659f6cbcc4b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528818469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2528818469
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2463244146
Short name T353
Test name
Test status
Simulation time 3512505747 ps
CPU time 89.62 seconds
Started Aug 11 05:26:05 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 362352 kb
Host smart-18dc1df3-c5a4-40ad-ab94-00146aaf3002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463244146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2463244146
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.4183117715
Short name T1551
Test name
Test status
Simulation time 2417133861 ps
CPU time 79.89 seconds
Started Aug 11 05:26:09 PM PDT 24
Finished Aug 11 05:27:29 PM PDT 24
Peak memory 739428 kb
Host smart-22e47f1e-dd77-4c3c-ac2c-b2cc535cf581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183117715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.4183117715
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2555510447
Short name T1265
Test name
Test status
Simulation time 271137557 ps
CPU time 1.27 seconds
Started Aug 11 05:26:07 PM PDT 24
Finished Aug 11 05:26:08 PM PDT 24
Peak memory 205448 kb
Host smart-d8e48a1b-f0a4-438d-85b4-ab64237e99e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555510447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2555510447
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3916278502
Short name T1389
Test name
Test status
Simulation time 178776709 ps
CPU time 9.29 seconds
Started Aug 11 05:26:09 PM PDT 24
Finished Aug 11 05:26:18 PM PDT 24
Peak memory 204484 kb
Host smart-371ed3f2-62ec-41bd-bbbf-9d3a9f4eac2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916278502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3916278502
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.210290517
Short name T420
Test name
Test status
Simulation time 16308379068 ps
CPU time 273.8 seconds
Started Aug 11 05:26:05 PM PDT 24
Finished Aug 11 05:30:39 PM PDT 24
Peak memory 1151988 kb
Host smart-1529ab53-5516-4b3b-9926-9193cb84a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210290517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.210290517
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3259012850
Short name T1621
Test name
Test status
Simulation time 5370047701 ps
CPU time 5.46 seconds
Started Aug 11 05:26:14 PM PDT 24
Finished Aug 11 05:26:19 PM PDT 24
Peak memory 205596 kb
Host smart-751a9444-567c-48d4-8d20-9325279e1201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259012850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3259012850
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_override.848128430
Short name T92
Test name
Test status
Simulation time 26602123 ps
CPU time 0.71 seconds
Started Aug 11 05:26:09 PM PDT 24
Finished Aug 11 05:26:09 PM PDT 24
Peak memory 204180 kb
Host smart-a4dbca1f-714f-40ea-9e86-72dc1e081a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848128430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.848128430
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3617317004
Short name T14
Test name
Test status
Simulation time 48974231927 ps
CPU time 270.68 seconds
Started Aug 11 05:26:06 PM PDT 24
Finished Aug 11 05:30:37 PM PDT 24
Peak memory 1688228 kb
Host smart-0d3b98fd-8e20-49db-b706-ffc078ca4a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617317004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3617317004
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.3406024938
Short name T1033
Test name
Test status
Simulation time 142034461 ps
CPU time 1.64 seconds
Started Aug 11 05:26:06 PM PDT 24
Finished Aug 11 05:26:08 PM PDT 24
Peak memory 213676 kb
Host smart-400fd4d1-0c26-44e1-871b-d679961c3fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406024938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.3406024938
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.99008967
Short name T307
Test name
Test status
Simulation time 4065427775 ps
CPU time 45.37 seconds
Started Aug 11 05:26:05 PM PDT 24
Finished Aug 11 05:26:51 PM PDT 24
Peak memory 294960 kb
Host smart-8695adce-c8e5-4567-945a-72ee83b31a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99008967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.99008967
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.5077367
Short name T279
Test name
Test status
Simulation time 19613826411 ps
CPU time 974.03 seconds
Started Aug 11 05:26:04 PM PDT 24
Finished Aug 11 05:42:19 PM PDT 24
Peak memory 1926596 kb
Host smart-7500997b-9b73-4edb-97e4-95a1302e683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5077367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.5077367
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.1290057165
Short name T724
Test name
Test status
Simulation time 492517633 ps
CPU time 8.2 seconds
Started Aug 11 05:26:07 PM PDT 24
Finished Aug 11 05:26:15 PM PDT 24
Peak memory 215704 kb
Host smart-301e3747-f56f-48e7-b3b0-7abb063df1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290057165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1290057165
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2465515241
Short name T184
Test name
Test status
Simulation time 241769148 ps
CPU time 0.96 seconds
Started Aug 11 05:26:19 PM PDT 24
Finished Aug 11 05:26:20 PM PDT 24
Peak memory 223840 kb
Host smart-f6fb3ddb-db69-4e74-99e3-8befdabc368b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465515241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2465515241
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.4033119907
Short name T842
Test name
Test status
Simulation time 1287129502 ps
CPU time 4.03 seconds
Started Aug 11 05:26:10 PM PDT 24
Finished Aug 11 05:26:14 PM PDT 24
Peak memory 216784 kb
Host smart-f44990a8-93b3-42e5-a359-70592cb1dd17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033119907 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.4033119907
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.1372953595
Short name T43
Test name
Test status
Simulation time 256156323 ps
CPU time 1.08 seconds
Started Aug 11 05:26:16 PM PDT 24
Finished Aug 11 05:26:17 PM PDT 24
Peak memory 205380 kb
Host smart-7bc578e1-4c50-4a60-837a-c598b0525849
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372953595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.1372953595
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3712643738
Short name T1401
Test name
Test status
Simulation time 261465905 ps
CPU time 1.17 seconds
Started Aug 11 05:26:13 PM PDT 24
Finished Aug 11 05:26:15 PM PDT 24
Peak memory 205608 kb
Host smart-72b96626-14f8-4d7a-9b77-1bbc3d95e7bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712643738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3712643738
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.513505821
Short name T884
Test name
Test status
Simulation time 1883666961 ps
CPU time 2.75 seconds
Started Aug 11 05:26:14 PM PDT 24
Finished Aug 11 05:26:17 PM PDT 24
Peak memory 205592 kb
Host smart-16e2c0b5-d5da-4cc2-bf1c-5846aaf9dc76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513505821 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.513505821
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.273871867
Short name T325
Test name
Test status
Simulation time 220118268 ps
CPU time 1.05 seconds
Started Aug 11 05:26:14 PM PDT 24
Finished Aug 11 05:26:15 PM PDT 24
Peak memory 205380 kb
Host smart-93fed804-f28e-4045-a120-bfeb73f403f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273871867 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.273871867
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.1765813757
Short name T758
Test name
Test status
Simulation time 1373547765 ps
CPU time 7.9 seconds
Started Aug 11 05:26:09 PM PDT 24
Finished Aug 11 05:26:17 PM PDT 24
Peak memory 221940 kb
Host smart-1616dd12-5fe9-4ff6-9197-e81336e9a06d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765813757 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.1765813757
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.4287646986
Short name T414
Test name
Test status
Simulation time 9902188533 ps
CPU time 90.04 seconds
Started Aug 11 05:26:13 PM PDT 24
Finished Aug 11 05:27:43 PM PDT 24
Peak memory 2029760 kb
Host smart-74f5ffee-1fe6-4fff-bcdf-67d466777bb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287646986 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.4287646986
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull.2772728533
Short name T1027
Test name
Test status
Simulation time 552007990 ps
CPU time 2.97 seconds
Started Aug 11 05:26:12 PM PDT 24
Finished Aug 11 05:26:15 PM PDT 24
Peak memory 213716 kb
Host smart-53c5eaba-2c03-467f-88f1-e36fb713ff01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772728533 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_nack_acqfull.2772728533
Directory /workspace/4.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/4.i2c_target_nack_acqfull_addr.3176378014
Short name T503
Test name
Test status
Simulation time 492438709 ps
CPU time 2.84 seconds
Started Aug 11 05:26:14 PM PDT 24
Finished Aug 11 05:26:16 PM PDT 24
Peak memory 205656 kb
Host smart-d8a4370e-3320-42a6-9da6-f775c3572732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176378014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.3176378014
Directory /workspace/4.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/4.i2c_target_nack_txstretch.1573356184
Short name T917
Test name
Test status
Simulation time 581447625 ps
CPU time 1.34 seconds
Started Aug 11 05:26:12 PM PDT 24
Finished Aug 11 05:26:13 PM PDT 24
Peak memory 222540 kb
Host smart-e0f9929d-1d39-4496-acd7-941425ba98cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573356184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_nack_txstretch.1573356184
Directory /workspace/4.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/4.i2c_target_perf.560524743
Short name T693
Test name
Test status
Simulation time 3102397801 ps
CPU time 5.88 seconds
Started Aug 11 05:26:11 PM PDT 24
Finished Aug 11 05:26:17 PM PDT 24
Peak memory 219316 kb
Host smart-0411ac61-c868-4313-8d5a-e7064c9743f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560524743 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_perf.560524743
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smbus_maxlen.620284396
Short name T1078
Test name
Test status
Simulation time 525873125 ps
CPU time 2.3 seconds
Started Aug 11 05:26:14 PM PDT 24
Finished Aug 11 05:26:17 PM PDT 24
Peak memory 205384 kb
Host smart-0f59c070-a053-403e-b33b-5d25c08bb7ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620284396 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_smbus_maxlen.620284396
Directory /workspace/4.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.4111197149
Short name T1045
Test name
Test status
Simulation time 3996309891 ps
CPU time 22.18 seconds
Started Aug 11 05:26:08 PM PDT 24
Finished Aug 11 05:26:30 PM PDT 24
Peak memory 213892 kb
Host smart-91ef0a5a-0c9c-43a4-90df-b6b84a37fda4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111197149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.4111197149
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.367989336
Short name T679
Test name
Test status
Simulation time 40813308845 ps
CPU time 99.59 seconds
Started Aug 11 05:26:13 PM PDT 24
Finished Aug 11 05:27:52 PM PDT 24
Peak memory 1190860 kb
Host smart-9f02d7b8-e339-496e-a981-fb3c2c7f7787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367989336 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.i2c_target_stress_all.367989336
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.899299644
Short name T1690
Test name
Test status
Simulation time 3034080982 ps
CPU time 12.77 seconds
Started Aug 11 05:26:06 PM PDT 24
Finished Aug 11 05:26:19 PM PDT 24
Peak memory 212216 kb
Host smart-80607f63-4678-4882-a3e4-58cb99b86887
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899299644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_rd.899299644
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3412490814
Short name T655
Test name
Test status
Simulation time 68762398190 ps
CPU time 2768.31 seconds
Started Aug 11 05:26:07 PM PDT 24
Finished Aug 11 06:12:16 PM PDT 24
Peak memory 12392144 kb
Host smart-e470b3b9-a447-461a-9bcb-9924c0eea9bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412490814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3412490814
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.720767359
Short name T374
Test name
Test status
Simulation time 2686752810 ps
CPU time 55.33 seconds
Started Aug 11 05:26:07 PM PDT 24
Finished Aug 11 05:27:02 PM PDT 24
Peak memory 478712 kb
Host smart-2778df03-0b01-4ff9-ad4f-8cc539d3dfc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720767359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.720767359
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2880737606
Short name T1651
Test name
Test status
Simulation time 1341613755 ps
CPU time 6.95 seconds
Started Aug 11 05:26:13 PM PDT 24
Finished Aug 11 05:26:20 PM PDT 24
Peak memory 213832 kb
Host smart-3a0950c6-79de-4629-a3e9-15d8f8320f00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880737606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2880737606
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.841190392
Short name T317
Test name
Test status
Simulation time 92474377 ps
CPU time 2.06 seconds
Started Aug 11 05:26:13 PM PDT 24
Finished Aug 11 05:26:15 PM PDT 24
Peak memory 205600 kb
Host smart-fe5896d1-731b-4991-92f7-9d9164dbccec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841190392 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.841190392
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1451222605
Short name T1697
Test name
Test status
Simulation time 161768720 ps
CPU time 0.61 seconds
Started Aug 11 05:32:37 PM PDT 24
Finished Aug 11 05:32:38 PM PDT 24
Peak memory 204744 kb
Host smart-6b355b23-4308-4a61-9363-6295ada5ed80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451222605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1451222605
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1194924459
Short name T486
Test name
Test status
Simulation time 268697373 ps
CPU time 1.14 seconds
Started Aug 11 05:32:32 PM PDT 24
Finished Aug 11 05:32:33 PM PDT 24
Peak memory 216056 kb
Host smart-d28dae02-6129-40d0-9cea-78df985ae0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194924459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1194924459
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1710695175
Short name T939
Test name
Test status
Simulation time 730971627 ps
CPU time 8.19 seconds
Started Aug 11 05:32:37 PM PDT 24
Finished Aug 11 05:32:46 PM PDT 24
Peak memory 282176 kb
Host smart-5f8f7e14-5455-4400-a7c9-20eecee97582
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710695175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1710695175
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1168504122
Short name T1433
Test name
Test status
Simulation time 3641663813 ps
CPU time 79.87 seconds
Started Aug 11 05:32:30 PM PDT 24
Finished Aug 11 05:33:50 PM PDT 24
Peak memory 333492 kb
Host smart-f6fa03e3-b7f1-4bc4-a138-d5b1d5a2f9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168504122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1168504122
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2902356049
Short name T821
Test name
Test status
Simulation time 7239626903 ps
CPU time 42.49 seconds
Started Aug 11 05:32:30 PM PDT 24
Finished Aug 11 05:33:13 PM PDT 24
Peak memory 497260 kb
Host smart-6982b2b9-f2a1-4a92-ba4c-093759866ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902356049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2902356049
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.423872357
Short name T1113
Test name
Test status
Simulation time 491008838 ps
CPU time 1.16 seconds
Started Aug 11 05:32:32 PM PDT 24
Finished Aug 11 05:32:33 PM PDT 24
Peak memory 205284 kb
Host smart-5ddd1034-349f-44b1-be05-8691954ae308
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423872357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fm
t.423872357
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1118013298
Short name T1180
Test name
Test status
Simulation time 698395166 ps
CPU time 9.26 seconds
Started Aug 11 05:32:31 PM PDT 24
Finished Aug 11 05:32:41 PM PDT 24
Peak memory 205440 kb
Host smart-c974dff4-cb6e-409a-892b-1c2e8fef0334
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118013298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1118013298
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.549984539
Short name T109
Test name
Test status
Simulation time 3138209834 ps
CPU time 60.11 seconds
Started Aug 11 05:32:29 PM PDT 24
Finished Aug 11 05:33:29 PM PDT 24
Peak memory 884216 kb
Host smart-afa4a025-ecbd-4090-845a-8c8543537398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549984539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.549984539
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.3113713072
Short name T260
Test name
Test status
Simulation time 2020651851 ps
CPU time 7.72 seconds
Started Aug 11 05:32:39 PM PDT 24
Finished Aug 11 05:32:47 PM PDT 24
Peak memory 205496 kb
Host smart-b0f56feb-1935-4893-8218-e02689f2cfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113713072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.3113713072
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3430791416
Short name T6
Test name
Test status
Simulation time 359366504 ps
CPU time 1.73 seconds
Started Aug 11 05:32:40 PM PDT 24
Finished Aug 11 05:32:42 PM PDT 24
Peak memory 213680 kb
Host smart-9fd68285-2101-4acf-96a3-aa1db29901f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430791416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3430791416
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.2772893366
Short name T457
Test name
Test status
Simulation time 18036249 ps
CPU time 0.69 seconds
Started Aug 11 05:32:31 PM PDT 24
Finished Aug 11 05:32:32 PM PDT 24
Peak memory 205232 kb
Host smart-2200fae4-df87-4a1b-9141-bd77e6713d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772893366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2772893366
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1707623740
Short name T1011
Test name
Test status
Simulation time 2962652494 ps
CPU time 122.1 seconds
Started Aug 11 05:32:31 PM PDT 24
Finished Aug 11 05:34:34 PM PDT 24
Peak memory 223596 kb
Host smart-9bec6fd2-8dec-4251-8a70-2604a91aba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707623740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1707623740
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.923024278
Short name T495
Test name
Test status
Simulation time 162430119 ps
CPU time 1.94 seconds
Started Aug 11 05:32:32 PM PDT 24
Finished Aug 11 05:32:34 PM PDT 24
Peak memory 205424 kb
Host smart-c350d0f0-e25e-4c90-9284-1cb3cd410e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923024278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.923024278
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2216054264
Short name T597
Test name
Test status
Simulation time 1961746134 ps
CPU time 40.85 seconds
Started Aug 11 05:32:30 PM PDT 24
Finished Aug 11 05:33:11 PM PDT 24
Peak memory 419712 kb
Host smart-ae339553-8066-4f44-9882-763574d42ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216054264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2216054264
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.444266143
Short name T513
Test name
Test status
Simulation time 724205187 ps
CPU time 32.72 seconds
Started Aug 11 05:32:33 PM PDT 24
Finished Aug 11 05:33:06 PM PDT 24
Peak memory 213620 kb
Host smart-0499c198-4710-442f-a2f2-f00662bde52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444266143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.444266143
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2100084071
Short name T1366
Test name
Test status
Simulation time 6560168940 ps
CPU time 5.06 seconds
Started Aug 11 05:32:37 PM PDT 24
Finished Aug 11 05:32:42 PM PDT 24
Peak memory 213936 kb
Host smart-f3c905a2-c151-4d8a-88f0-622611dce8ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100084071 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2100084071
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.1477611713
Short name T1565
Test name
Test status
Simulation time 263602870 ps
CPU time 1.54 seconds
Started Aug 11 05:32:37 PM PDT 24
Finished Aug 11 05:32:39 PM PDT 24
Peak memory 205652 kb
Host smart-f34a2c72-cf3d-4b5d-a6ce-93cff57b15c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477611713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.1477611713
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2939996002
Short name T730
Test name
Test status
Simulation time 158282638 ps
CPU time 1.01 seconds
Started Aug 11 05:32:37 PM PDT 24
Finished Aug 11 05:32:39 PM PDT 24
Peak memory 205444 kb
Host smart-215cb842-2cad-438b-a258-7f90804a5b9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939996002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2939996002
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.3994754417
Short name T1221
Test name
Test status
Simulation time 2065836628 ps
CPU time 2.7 seconds
Started Aug 11 05:32:38 PM PDT 24
Finished Aug 11 05:32:41 PM PDT 24
Peak memory 205816 kb
Host smart-1b62b11a-5165-468b-abe6-e1d07acac4fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994754417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.3994754417
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.3678383489
Short name T1046
Test name
Test status
Simulation time 335400618 ps
CPU time 1.01 seconds
Started Aug 11 05:32:37 PM PDT 24
Finished Aug 11 05:32:39 PM PDT 24
Peak memory 205404 kb
Host smart-6ad47c68-41dd-42e1-b0d2-fadddfb482a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678383489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.3678383489
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.292637765
Short name T908
Test name
Test status
Simulation time 289019559 ps
CPU time 1.91 seconds
Started Aug 11 05:32:37 PM PDT 24
Finished Aug 11 05:32:40 PM PDT 24
Peak memory 205620 kb
Host smart-8e9d8620-f34e-4d7d-9487-6b14fc4bd11b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292637765 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.292637765
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1899342466
Short name T1586
Test name
Test status
Simulation time 832701907 ps
CPU time 4.7 seconds
Started Aug 11 05:32:32 PM PDT 24
Finished Aug 11 05:32:37 PM PDT 24
Peak memory 214552 kb
Host smart-b989895b-bc07-41e8-a2c4-fd548c345391
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899342466 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1899342466
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.220829116
Short name T563
Test name
Test status
Simulation time 15408153727 ps
CPU time 410.2 seconds
Started Aug 11 05:32:39 PM PDT 24
Finished Aug 11 05:39:29 PM PDT 24
Peak memory 3709396 kb
Host smart-37e0997f-624c-44e2-b1a7-ba6fd69115ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220829116 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.220829116
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull.1549017950
Short name T1543
Test name
Test status
Simulation time 1356817570 ps
CPU time 2.29 seconds
Started Aug 11 05:32:40 PM PDT 24
Finished Aug 11 05:32:42 PM PDT 24
Peak memory 213848 kb
Host smart-e894d3ce-6358-4dc8-b6fd-e626fffacaea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549017950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_nack_acqfull.1549017950
Directory /workspace/40.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/40.i2c_target_nack_acqfull_addr.2322147071
Short name T1597
Test name
Test status
Simulation time 483336086 ps
CPU time 2.5 seconds
Started Aug 11 05:32:38 PM PDT 24
Finished Aug 11 05:32:41 PM PDT 24
Peak memory 205596 kb
Host smart-a84de142-e41e-4305-8942-2d2a5d91a61b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322147071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_nack_acqfull_addr.2322147071
Directory /workspace/40.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.3456337827
Short name T785
Test name
Test status
Simulation time 3489254633 ps
CPU time 5.12 seconds
Started Aug 11 05:32:39 PM PDT 24
Finished Aug 11 05:32:45 PM PDT 24
Peak memory 221372 kb
Host smart-81e9383c-df44-433b-95da-ba524ee229fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456337827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.3456337827
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smbus_maxlen.3954572531
Short name T565
Test name
Test status
Simulation time 587922889 ps
CPU time 2.6 seconds
Started Aug 11 05:32:40 PM PDT 24
Finished Aug 11 05:32:43 PM PDT 24
Peak memory 205420 kb
Host smart-a3d87e5d-1e65-4311-8ca4-725f4740b089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954572531 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_smbus_maxlen.3954572531
Directory /workspace/40.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.2471279888
Short name T435
Test name
Test status
Simulation time 1168653294 ps
CPU time 15.56 seconds
Started Aug 11 05:32:29 PM PDT 24
Finished Aug 11 05:32:45 PM PDT 24
Peak memory 213784 kb
Host smart-437cf7b7-52a0-49b1-b825-7e464fc10bfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471279888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.2471279888
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.3570808738
Short name T1470
Test name
Test status
Simulation time 61303308406 ps
CPU time 97.87 seconds
Started Aug 11 05:32:40 PM PDT 24
Finished Aug 11 05:34:18 PM PDT 24
Peak memory 978756 kb
Host smart-c9c0648d-ab4c-49cf-bf87-3cd290c1a533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570808738 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.3570808738
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.1795831010
Short name T1284
Test name
Test status
Simulation time 2566697749 ps
CPU time 22.43 seconds
Started Aug 11 05:32:33 PM PDT 24
Finished Aug 11 05:32:55 PM PDT 24
Peak memory 221972 kb
Host smart-8aaa3249-0fc4-47f5-be19-ec6b6ae6602a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795831010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.1795831010
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.2383716849
Short name T1048
Test name
Test status
Simulation time 43195610452 ps
CPU time 764.14 seconds
Started Aug 11 05:32:32 PM PDT 24
Finished Aug 11 05:45:17 PM PDT 24
Peak memory 5880440 kb
Host smart-81701acf-42f8-47be-9ee5-cfd724c4c56e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383716849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.2383716849
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.317587747
Short name T1234
Test name
Test status
Simulation time 1454383248 ps
CPU time 15.49 seconds
Started Aug 11 05:32:29 PM PDT 24
Finished Aug 11 05:32:45 PM PDT 24
Peak memory 276896 kb
Host smart-53774fe6-f42a-420d-a500-de70cf54c057
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317587747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_t
arget_stretch.317587747
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1058973433
Short name T417
Test name
Test status
Simulation time 1368711571 ps
CPU time 7.83 seconds
Started Aug 11 05:32:40 PM PDT 24
Finished Aug 11 05:32:48 PM PDT 24
Peak memory 231440 kb
Host smart-16fdc71c-5345-4b99-ad40-7ac97e895d88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058973433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1058973433
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.442854079
Short name T418
Test name
Test status
Simulation time 80863048 ps
CPU time 1.87 seconds
Started Aug 11 05:32:38 PM PDT 24
Finished Aug 11 05:32:40 PM PDT 24
Peak memory 205628 kb
Host smart-42c2ba4e-6f4c-4ca6-a3c9-9b9d0c3230fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442854079 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.442854079
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.1954955139
Short name T1162
Test name
Test status
Simulation time 26260713 ps
CPU time 0.63 seconds
Started Aug 11 05:32:49 PM PDT 24
Finished Aug 11 05:32:50 PM PDT 24
Peak memory 204888 kb
Host smart-5a0d9763-6972-44b9-9c57-e68def4ead55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954955139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1954955139
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3850293495
Short name T406
Test name
Test status
Simulation time 146125195 ps
CPU time 3.38 seconds
Started Aug 11 05:32:43 PM PDT 24
Finished Aug 11 05:32:47 PM PDT 24
Peak memory 213744 kb
Host smart-8d3c9b0a-0321-48f8-adff-f13f08f126d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850293495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3850293495
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.2483725301
Short name T631
Test name
Test status
Simulation time 252357493 ps
CPU time 5.53 seconds
Started Aug 11 05:32:42 PM PDT 24
Finished Aug 11 05:32:48 PM PDT 24
Peak memory 255964 kb
Host smart-1cf40413-112c-43ed-92d5-3b776ebfb73e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483725301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.2483725301
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.1679540861
Short name T1052
Test name
Test status
Simulation time 13932742777 ps
CPU time 79.01 seconds
Started Aug 11 05:32:44 PM PDT 24
Finished Aug 11 05:34:03 PM PDT 24
Peak memory 246852 kb
Host smart-31ae2322-a2f2-4ce5-95e1-addf480b2c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679540861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.1679540861
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1101867442
Short name T1722
Test name
Test status
Simulation time 5385491571 ps
CPU time 67.94 seconds
Started Aug 11 05:32:44 PM PDT 24
Finished Aug 11 05:33:52 PM PDT 24
Peak memory 752400 kb
Host smart-dd486b78-b8b3-4eee-9844-dd8faa897804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101867442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1101867442
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3364646245
Short name T542
Test name
Test status
Simulation time 193459414 ps
CPU time 10.38 seconds
Started Aug 11 05:32:42 PM PDT 24
Finished Aug 11 05:32:52 PM PDT 24
Peak memory 205464 kb
Host smart-e8cac7c8-3696-4bda-8233-0f6140dc1b8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364646245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3364646245
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.3242622657
Short name T1431
Test name
Test status
Simulation time 10338535135 ps
CPU time 138.68 seconds
Started Aug 11 05:32:36 PM PDT 24
Finished Aug 11 05:34:55 PM PDT 24
Peak memory 1490148 kb
Host smart-4b43d2ea-8d60-4392-8fbe-b94d2dc96638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242622657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.3242622657
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.4294922335
Short name T1716
Test name
Test status
Simulation time 2053641286 ps
CPU time 6.37 seconds
Started Aug 11 05:32:45 PM PDT 24
Finished Aug 11 05:32:52 PM PDT 24
Peak memory 205204 kb
Host smart-0537b612-69ee-4409-a119-f6d24ab4a808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294922335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.4294922335
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_override.3014249789
Short name T74
Test name
Test status
Simulation time 19188086 ps
CPU time 0.67 seconds
Started Aug 11 05:32:40 PM PDT 24
Finished Aug 11 05:32:41 PM PDT 24
Peak memory 205196 kb
Host smart-a33505a1-692f-481f-8b0c-6a34d0871a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014249789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3014249789
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.4130172825
Short name T153
Test name
Test status
Simulation time 74772555810 ps
CPU time 1438.47 seconds
Started Aug 11 05:32:47 PM PDT 24
Finished Aug 11 05:56:45 PM PDT 24
Peak memory 3762516 kb
Host smart-99b6e664-795f-4609-bf0e-7cf831b1c1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130172825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.4130172825
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.3683107279
Short name T996
Test name
Test status
Simulation time 232700941 ps
CPU time 10.19 seconds
Started Aug 11 05:32:43 PM PDT 24
Finished Aug 11 05:32:54 PM PDT 24
Peak memory 235376 kb
Host smart-f3fa66ab-66ff-4dfa-907b-072d25c6d42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683107279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.3683107279
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2630149896
Short name T1639
Test name
Test status
Simulation time 3802374392 ps
CPU time 27.26 seconds
Started Aug 11 05:32:39 PM PDT 24
Finished Aug 11 05:33:06 PM PDT 24
Peak memory 369164 kb
Host smart-f9aab806-1f48-4190-a3b3-fe321548637b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630149896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2630149896
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3445667647
Short name T1729
Test name
Test status
Simulation time 883902069 ps
CPU time 16.11 seconds
Started Aug 11 05:32:46 PM PDT 24
Finished Aug 11 05:33:02 PM PDT 24
Peak memory 213676 kb
Host smart-00ca2533-d7b3-4592-8433-d01afd277059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445667647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3445667647
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.1794710244
Short name T961
Test name
Test status
Simulation time 1970506975 ps
CPU time 5.22 seconds
Started Aug 11 05:32:43 PM PDT 24
Finished Aug 11 05:32:49 PM PDT 24
Peak memory 221920 kb
Host smart-f985e01d-7def-4ded-b650-f6353e63e24d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794710244 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.1794710244
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1173452176
Short name T424
Test name
Test status
Simulation time 162535096 ps
CPU time 0.9 seconds
Started Aug 11 05:32:45 PM PDT 24
Finished Aug 11 05:32:46 PM PDT 24
Peak memory 205128 kb
Host smart-dfbd0b0d-9c57-4958-bf27-b102db22b4fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173452176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1173452176
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3381136661
Short name T10
Test name
Test status
Simulation time 463476596 ps
CPU time 1.52 seconds
Started Aug 11 05:32:45 PM PDT 24
Finished Aug 11 05:32:46 PM PDT 24
Peak memory 217636 kb
Host smart-ca107542-b2f6-4f26-baa7-254b1cc2fb09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381136661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3381136661
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.182900936
Short name T1201
Test name
Test status
Simulation time 706051210 ps
CPU time 2.33 seconds
Started Aug 11 05:32:43 PM PDT 24
Finished Aug 11 05:32:45 PM PDT 24
Peak memory 205580 kb
Host smart-88ecd88f-cbf2-4cbd-8e92-d12ec8ae4ab2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182900936 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.182900936
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.1827563585
Short name T915
Test name
Test status
Simulation time 152089832 ps
CPU time 1.2 seconds
Started Aug 11 05:32:43 PM PDT 24
Finished Aug 11 05:32:45 PM PDT 24
Peak memory 205428 kb
Host smart-64835d45-1773-4ae2-ae29-c9f18d25e545
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827563585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.1827563585
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3205597771
Short name T1166
Test name
Test status
Simulation time 521266048 ps
CPU time 2.07 seconds
Started Aug 11 05:32:45 PM PDT 24
Finished Aug 11 05:32:48 PM PDT 24
Peak memory 214740 kb
Host smart-a3fc9b40-ca68-43f4-ac8f-fa693830120f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205597771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3205597771
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1556620671
Short name T1271
Test name
Test status
Simulation time 4020431938 ps
CPU time 6 seconds
Started Aug 11 05:32:46 PM PDT 24
Finished Aug 11 05:32:52 PM PDT 24
Peak memory 230288 kb
Host smart-88a7bff8-f0d7-4881-97af-d75f461375fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556620671 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1556620671
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.992101935
Short name T617
Test name
Test status
Simulation time 14617904390 ps
CPU time 151.17 seconds
Started Aug 11 05:32:42 PM PDT 24
Finished Aug 11 05:35:14 PM PDT 24
Peak memory 2082712 kb
Host smart-d26e6dfe-8f61-4335-93ac-429a0e135307
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992101935 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.992101935
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull.3041083345
Short name T1524
Test name
Test status
Simulation time 541850546 ps
CPU time 3 seconds
Started Aug 11 05:32:49 PM PDT 24
Finished Aug 11 05:32:52 PM PDT 24
Peak memory 213796 kb
Host smart-66b9f3dc-cf42-4fae-81a1-fe9ced6195b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041083345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_nack_acqfull.3041083345
Directory /workspace/41.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/41.i2c_target_nack_acqfull_addr.3475872515
Short name T162
Test name
Test status
Simulation time 4481120984 ps
CPU time 2.64 seconds
Started Aug 11 05:32:49 PM PDT 24
Finished Aug 11 05:32:51 PM PDT 24
Peak memory 205792 kb
Host smart-e6d832b1-74c9-4c7a-aaa7-cad2659953aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475872515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.3475872515
Directory /workspace/41.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/41.i2c_target_nack_txstretch.2097304568
Short name T1589
Test name
Test status
Simulation time 687467049 ps
CPU time 1.6 seconds
Started Aug 11 05:32:53 PM PDT 24
Finished Aug 11 05:32:55 PM PDT 24
Peak memory 222284 kb
Host smart-5a9ebbd0-5054-4319-aabf-3ce88bcde636
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097304568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_nack_txstretch.2097304568
Directory /workspace/41.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/41.i2c_target_perf.3232698508
Short name T722
Test name
Test status
Simulation time 687749358 ps
CPU time 5.21 seconds
Started Aug 11 05:32:44 PM PDT 24
Finished Aug 11 05:32:49 PM PDT 24
Peak memory 221968 kb
Host smart-4a76358a-ace3-4938-adfb-1b772811993c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232698508 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.3232698508
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smbus_maxlen.1188384444
Short name T1648
Test name
Test status
Simulation time 6590824032 ps
CPU time 2.03 seconds
Started Aug 11 05:32:49 PM PDT 24
Finished Aug 11 05:32:51 PM PDT 24
Peak memory 205508 kb
Host smart-8d97e772-649d-4aa9-ad53-4f6226683587
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188384444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_smbus_maxlen.1188384444
Directory /workspace/41.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.4253009331
Short name T341
Test name
Test status
Simulation time 1456664030 ps
CPU time 46.55 seconds
Started Aug 11 05:32:46 PM PDT 24
Finished Aug 11 05:33:33 PM PDT 24
Peak memory 213852 kb
Host smart-5ef109b2-8b9a-4de1-8b4b-e943131dd4a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253009331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.4253009331
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.412199606
Short name T521
Test name
Test status
Simulation time 1656040697 ps
CPU time 23.13 seconds
Started Aug 11 05:32:44 PM PDT 24
Finished Aug 11 05:33:08 PM PDT 24
Peak memory 229980 kb
Host smart-efac980a-60e7-4604-ac08-6ff76932dea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412199606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_rd.412199606
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.1329160392
Short name T720
Test name
Test status
Simulation time 42210010072 ps
CPU time 245.54 seconds
Started Aug 11 05:32:44 PM PDT 24
Finished Aug 11 05:36:50 PM PDT 24
Peak memory 2802728 kb
Host smart-d9720feb-abd5-4445-9dc7-a51a9bf64146
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329160392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.1329160392
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3510359652
Short name T1495
Test name
Test status
Simulation time 1831407095 ps
CPU time 17.86 seconds
Started Aug 11 05:32:45 PM PDT 24
Finished Aug 11 05:33:03 PM PDT 24
Peak memory 287676 kb
Host smart-46ac6c83-dd50-4ec2-ac1c-5e4235544e9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510359652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3510359652
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1272448337
Short name T1726
Test name
Test status
Simulation time 1309894029 ps
CPU time 7.25 seconds
Started Aug 11 05:32:45 PM PDT 24
Finished Aug 11 05:32:52 PM PDT 24
Peak memory 230232 kb
Host smart-6c70b91c-bc61-4645-87b0-2b546ba97ddb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272448337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1272448337
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.1016356374
Short name T1667
Test name
Test status
Simulation time 137037379 ps
CPU time 2.37 seconds
Started Aug 11 05:32:52 PM PDT 24
Finished Aug 11 05:32:54 PM PDT 24
Peak memory 214908 kb
Host smart-a7086cb4-2f9f-4777-868c-450ff563adcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016356374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.1016356374
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.1633114754
Short name T1146
Test name
Test status
Simulation time 21135279 ps
CPU time 0.69 seconds
Started Aug 11 05:32:57 PM PDT 24
Finished Aug 11 05:32:58 PM PDT 24
Peak memory 204744 kb
Host smart-62adf9ad-3aa6-4d90-bd9b-7ccd954444b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633114754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.1633114754
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.4050938547
Short name T1324
Test name
Test status
Simulation time 1267686915 ps
CPU time 4.08 seconds
Started Aug 11 05:32:49 PM PDT 24
Finished Aug 11 05:32:53 PM PDT 24
Peak memory 233256 kb
Host smart-328b6322-37ea-46ad-9a02-e983b9c72898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050938547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.4050938547
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.4116161479
Short name T1196
Test name
Test status
Simulation time 5642417297 ps
CPU time 7.05 seconds
Started Aug 11 05:32:49 PM PDT 24
Finished Aug 11 05:32:57 PM PDT 24
Peak memory 279036 kb
Host smart-110925b0-2a79-4529-bd6c-46465a2c4d11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116161479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.4116161479
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2949342198
Short name T1184
Test name
Test status
Simulation time 3104753267 ps
CPU time 127.62 seconds
Started Aug 11 05:32:51 PM PDT 24
Finished Aug 11 05:34:59 PM PDT 24
Peak memory 741488 kb
Host smart-7538df30-0d51-48e9-b237-066d2dd97503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949342198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2949342198
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.4291537085
Short name T1269
Test name
Test status
Simulation time 1853009587 ps
CPU time 138.5 seconds
Started Aug 11 05:32:49 PM PDT 24
Finished Aug 11 05:35:08 PM PDT 24
Peak memory 664652 kb
Host smart-d2bbf1e6-8326-4b9b-85db-8d16d1c592b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291537085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.4291537085
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.591853623
Short name T539
Test name
Test status
Simulation time 160143080 ps
CPU time 1.23 seconds
Started Aug 11 05:32:51 PM PDT 24
Finished Aug 11 05:32:53 PM PDT 24
Peak memory 205252 kb
Host smart-92744885-af69-4ab8-81fb-f51751286e57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591853623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fm
t.591853623
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.917414810
Short name T630
Test name
Test status
Simulation time 730501461 ps
CPU time 8.42 seconds
Started Aug 11 05:32:51 PM PDT 24
Finished Aug 11 05:33:00 PM PDT 24
Peak memory 229860 kb
Host smart-23c11b83-9016-4d32-bb80-14fa0b692fd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917414810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.
917414810
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2769853811
Short name T977
Test name
Test status
Simulation time 4125550000 ps
CPU time 99.36 seconds
Started Aug 11 05:32:52 PM PDT 24
Finished Aug 11 05:34:32 PM PDT 24
Peak memory 1215060 kb
Host smart-881fbc38-1d56-48a5-91b6-f9d4b98da5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769853811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2769853811
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3833853296
Short name T1547
Test name
Test status
Simulation time 1493909536 ps
CPU time 9.92 seconds
Started Aug 11 05:33:00 PM PDT 24
Finished Aug 11 05:33:10 PM PDT 24
Peak memory 205416 kb
Host smart-cc7c5427-662f-4c96-bc0e-6d5baed108ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833853296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3833853296
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.1086687768
Short name T1256
Test name
Test status
Simulation time 184549669 ps
CPU time 3.14 seconds
Started Aug 11 05:32:58 PM PDT 24
Finished Aug 11 05:33:01 PM PDT 24
Peak memory 213684 kb
Host smart-9ed158c9-4727-4bc1-8aa6-5d504ee6e7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086687768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.1086687768
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2196312933
Short name T681
Test name
Test status
Simulation time 99551824 ps
CPU time 0.66 seconds
Started Aug 11 05:32:50 PM PDT 24
Finished Aug 11 05:32:51 PM PDT 24
Peak memory 205252 kb
Host smart-7d82ef22-d86a-4630-8f82-e073b2f3239b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196312933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2196312933
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.687063109
Short name T1215
Test name
Test status
Simulation time 49618743024 ps
CPU time 3574.05 seconds
Started Aug 11 05:32:50 PM PDT 24
Finished Aug 11 06:32:25 PM PDT 24
Peak memory 6648732 kb
Host smart-4e47f412-7c09-47cc-aa00-2b794f40488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687063109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.687063109
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.352679465
Short name T619
Test name
Test status
Simulation time 73549302 ps
CPU time 1.64 seconds
Started Aug 11 05:32:49 PM PDT 24
Finished Aug 11 05:32:51 PM PDT 24
Peak memory 213644 kb
Host smart-7e4754da-cb2a-4003-86e0-fda4bc31fa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352679465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.352679465
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.2704265985
Short name T182
Test name
Test status
Simulation time 19938466483 ps
CPU time 36.24 seconds
Started Aug 11 05:32:51 PM PDT 24
Finished Aug 11 05:33:27 PM PDT 24
Peak memory 409060 kb
Host smart-ba71278c-7374-47c4-b46b-2b74bb4b0609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704265985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.2704265985
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1952313169
Short name T805
Test name
Test status
Simulation time 707348465 ps
CPU time 30.19 seconds
Started Aug 11 05:32:48 PM PDT 24
Finished Aug 11 05:33:18 PM PDT 24
Peak memory 213580 kb
Host smart-804784e8-6cd0-4b86-8b83-ea50ec7227db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952313169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1952313169
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.4171382183
Short name T1104
Test name
Test status
Simulation time 976395549 ps
CPU time 6.13 seconds
Started Aug 11 05:32:59 PM PDT 24
Finished Aug 11 05:33:06 PM PDT 24
Peak memory 216112 kb
Host smart-abb398cc-8c03-47fe-8197-dd25fe8862be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171382183 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.4171382183
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1925136836
Short name T1399
Test name
Test status
Simulation time 131538566 ps
CPU time 1.1 seconds
Started Aug 11 05:32:57 PM PDT 24
Finished Aug 11 05:32:58 PM PDT 24
Peak memory 205488 kb
Host smart-6a840d8c-4325-4efe-87e5-5da946563851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925136836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1925136836
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.411707209
Short name T419
Test name
Test status
Simulation time 413374255 ps
CPU time 1.24 seconds
Started Aug 11 05:32:58 PM PDT 24
Finished Aug 11 05:32:59 PM PDT 24
Peak memory 205372 kb
Host smart-b113fb8f-4c22-4387-8b5b-9ffd41f95d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411707209 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.411707209
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.1314118059
Short name T1534
Test name
Test status
Simulation time 2663007963 ps
CPU time 3.37 seconds
Started Aug 11 05:32:56 PM PDT 24
Finished Aug 11 05:33:00 PM PDT 24
Peak memory 205768 kb
Host smart-80801eb4-0b64-440e-b659-ec12a3c94e10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314118059 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.1314118059
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.1889020298
Short name T1460
Test name
Test status
Simulation time 164828133 ps
CPU time 1.55 seconds
Started Aug 11 05:32:57 PM PDT 24
Finished Aug 11 05:32:58 PM PDT 24
Peak memory 205444 kb
Host smart-b3aefb2e-bcec-440e-9dc8-7344f69fb7e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889020298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.1889020298
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1566700449
Short name T297
Test name
Test status
Simulation time 4800540987 ps
CPU time 6.29 seconds
Started Aug 11 05:32:56 PM PDT 24
Finished Aug 11 05:33:02 PM PDT 24
Peak memory 222164 kb
Host smart-00eca2fc-00db-4ea7-a0f5-90e077e94b73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566700449 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1566700449
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.15298352
Short name T1396
Test name
Test status
Simulation time 1273519021 ps
CPU time 1.48 seconds
Started Aug 11 05:32:58 PM PDT 24
Finished Aug 11 05:33:00 PM PDT 24
Peak memory 205356 kb
Host smart-2d52b1ea-31c6-4917-ac2b-b87bc8265516
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15298352 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.15298352
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull.4279583274
Short name T807
Test name
Test status
Simulation time 540403018 ps
CPU time 3.32 seconds
Started Aug 11 05:32:58 PM PDT 24
Finished Aug 11 05:33:01 PM PDT 24
Peak memory 213800 kb
Host smart-97ce79ed-12d6-4b74-a769-080d6935854f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279583274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_nack_acqfull.4279583274
Directory /workspace/42.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/42.i2c_target_nack_acqfull_addr.564326538
Short name T1000
Test name
Test status
Simulation time 4499005908 ps
CPU time 2.72 seconds
Started Aug 11 05:32:57 PM PDT 24
Finished Aug 11 05:32:59 PM PDT 24
Peak memory 205736 kb
Host smart-1c587a80-d03d-47f1-aee5-006e16e966f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564326538 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.564326538
Directory /workspace/42.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/42.i2c_target_nack_txstretch.2796668163
Short name T1076
Test name
Test status
Simulation time 366755773 ps
CPU time 1.79 seconds
Started Aug 11 05:33:00 PM PDT 24
Finished Aug 11 05:33:02 PM PDT 24
Peak memory 222356 kb
Host smart-1357c878-7267-47f6-847f-de5222154440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796668163 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_nack_txstretch.2796668163
Directory /workspace/42.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/42.i2c_target_perf.4221452330
Short name T632
Test name
Test status
Simulation time 1330105601 ps
CPU time 4.95 seconds
Started Aug 11 05:32:56 PM PDT 24
Finished Aug 11 05:33:01 PM PDT 24
Peak memory 221952 kb
Host smart-ed577233-53ac-4063-b96d-7ff6c2fd09d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221452330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.4221452330
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smbus_maxlen.165740886
Short name T1091
Test name
Test status
Simulation time 528914371 ps
CPU time 2.35 seconds
Started Aug 11 05:32:58 PM PDT 24
Finished Aug 11 05:33:01 PM PDT 24
Peak memory 205412 kb
Host smart-68c309e5-ee40-43d8-ab8a-7215b6b3703b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165740886 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_smbus_maxlen.165740886
Directory /workspace/42.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.577265084
Short name T586
Test name
Test status
Simulation time 1741954288 ps
CPU time 47.72 seconds
Started Aug 11 05:32:56 PM PDT 24
Finished Aug 11 05:33:44 PM PDT 24
Peak memory 213852 kb
Host smart-0e734543-6577-4d00-8e5d-9adaeef388aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577265084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.577265084
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.1840860702
Short name T384
Test name
Test status
Simulation time 35708255713 ps
CPU time 85.25 seconds
Started Aug 11 05:32:56 PM PDT 24
Finished Aug 11 05:34:22 PM PDT 24
Peak memory 968888 kb
Host smart-4d73c1ab-b5c7-461f-8f10-cf4a946d274e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840860702 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.1840860702
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2680824223
Short name T666
Test name
Test status
Simulation time 519791187 ps
CPU time 23.46 seconds
Started Aug 11 05:32:59 PM PDT 24
Finished Aug 11 05:33:23 PM PDT 24
Peak memory 213848 kb
Host smart-c7457c27-1d4f-4f36-9d85-e2d392fe155f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680824223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2680824223
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.614121875
Short name T896
Test name
Test status
Simulation time 64162107182 ps
CPU time 284.65 seconds
Started Aug 11 05:32:56 PM PDT 24
Finished Aug 11 05:37:40 PM PDT 24
Peak memory 2653468 kb
Host smart-66a6cdee-d1ec-44d7-b7a4-f61a493ec22f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614121875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.614121875
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.3546523632
Short name T275
Test name
Test status
Simulation time 1290039982 ps
CPU time 6.27 seconds
Started Aug 11 05:32:56 PM PDT 24
Finished Aug 11 05:33:03 PM PDT 24
Peak memory 280112 kb
Host smart-f80ba5b0-2898-438a-ad62-09db09518741
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546523632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.3546523632
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1104398539
Short name T1687
Test name
Test status
Simulation time 5553221801 ps
CPU time 7.76 seconds
Started Aug 11 05:32:58 PM PDT 24
Finished Aug 11 05:33:06 PM PDT 24
Peak memory 230248 kb
Host smart-97a83b85-4ad9-49d4-9dc3-30efd48d6ac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104398539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1104398539
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.702066876
Short name T1096
Test name
Test status
Simulation time 130784915 ps
CPU time 2.56 seconds
Started Aug 11 05:33:00 PM PDT 24
Finished Aug 11 05:33:03 PM PDT 24
Peak memory 205592 kb
Host smart-da41f238-26b0-4a98-a574-cd5b9f46684c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702066876 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.702066876
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.799724263
Short name T609
Test name
Test status
Simulation time 21911378 ps
CPU time 0.63 seconds
Started Aug 11 05:33:09 PM PDT 24
Finished Aug 11 05:33:10 PM PDT 24
Peak memory 204620 kb
Host smart-98fef7dd-cc26-42c4-ba2a-0df17ae1f98c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799724263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.799724263
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1042141378
Short name T672
Test name
Test status
Simulation time 125068252 ps
CPU time 1.81 seconds
Started Aug 11 05:33:06 PM PDT 24
Finished Aug 11 05:33:08 PM PDT 24
Peak memory 221988 kb
Host smart-a53de794-cb60-4340-8d2a-b207dd3fef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042141378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1042141378
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.791467023
Short name T1245
Test name
Test status
Simulation time 707775775 ps
CPU time 7.48 seconds
Started Aug 11 05:33:04 PM PDT 24
Finished Aug 11 05:33:11 PM PDT 24
Peak memory 278020 kb
Host smart-7e6f517a-a420-4d39-95e0-64f4ad4b7775
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791467023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empt
y.791467023
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1213989273
Short name T749
Test name
Test status
Simulation time 14522497891 ps
CPU time 186.12 seconds
Started Aug 11 05:33:03 PM PDT 24
Finished Aug 11 05:36:09 PM PDT 24
Peak memory 459148 kb
Host smart-3f555b6f-8570-4c02-927c-0ecefa8233ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213989273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1213989273
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2775012963
Short name T918
Test name
Test status
Simulation time 116921327 ps
CPU time 1.19 seconds
Started Aug 11 05:33:05 PM PDT 24
Finished Aug 11 05:33:06 PM PDT 24
Peak memory 205232 kb
Host smart-fc0ec96a-9018-4814-ac9b-5f9efd51b4bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775012963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2775012963
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2344359646
Short name T538
Test name
Test status
Simulation time 237030830 ps
CPU time 5.83 seconds
Started Aug 11 05:33:02 PM PDT 24
Finished Aug 11 05:33:08 PM PDT 24
Peak memory 205424 kb
Host smart-039f7e8e-53ee-4458-a88c-6ee678549887
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344359646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.2344359646
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2380703820
Short name T1530
Test name
Test status
Simulation time 7934131295 ps
CPU time 111.67 seconds
Started Aug 11 05:33:07 PM PDT 24
Finished Aug 11 05:34:59 PM PDT 24
Peak memory 1141640 kb
Host smart-d565b821-8734-493b-bd51-1951b6fecc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380703820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2380703820
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.3925215362
Short name T248
Test name
Test status
Simulation time 691585330 ps
CPU time 30.01 seconds
Started Aug 11 05:33:03 PM PDT 24
Finished Aug 11 05:33:33 PM PDT 24
Peak memory 205408 kb
Host smart-0ee3ace2-dc4a-4efb-944f-e2ab07487615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925215362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.3925215362
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_override.1794451119
Short name T604
Test name
Test status
Simulation time 17257672 ps
CPU time 0.66 seconds
Started Aug 11 05:33:05 PM PDT 24
Finished Aug 11 05:33:06 PM PDT 24
Peak memory 205200 kb
Host smart-07240da8-68c8-4e38-9661-baca9a672299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794451119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1794451119
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.3122146620
Short name T1029
Test name
Test status
Simulation time 4970670426 ps
CPU time 385.24 seconds
Started Aug 11 05:33:06 PM PDT 24
Finished Aug 11 05:39:32 PM PDT 24
Peak memory 1387708 kb
Host smart-ad5b417a-9102-4b90-84d8-8a331fd527aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122146620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.3122146620
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.1686406921
Short name T1177
Test name
Test status
Simulation time 135405538 ps
CPU time 0.96 seconds
Started Aug 11 05:33:06 PM PDT 24
Finished Aug 11 05:33:07 PM PDT 24
Peak memory 205208 kb
Host smart-47574f1d-e8c3-4fda-bd4b-da13bab75507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686406921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.1686406921
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2012253353
Short name T788
Test name
Test status
Simulation time 15072609634 ps
CPU time 39.97 seconds
Started Aug 11 05:33:09 PM PDT 24
Finished Aug 11 05:33:49 PM PDT 24
Peak memory 387448 kb
Host smart-e20fbbf4-5dc9-484d-b374-d68db1c4ac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012253353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2012253353
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.2302584908
Short name T32
Test name
Test status
Simulation time 79796508490 ps
CPU time 3484.11 seconds
Started Aug 11 05:33:02 PM PDT 24
Finished Aug 11 06:31:07 PM PDT 24
Peak memory 2974520 kb
Host smart-f3dfbb13-482d-46f9-b005-3746e117f92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302584908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.2302584908
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2770789530
Short name T1005
Test name
Test status
Simulation time 1128411857 ps
CPU time 20.54 seconds
Started Aug 11 05:33:03 PM PDT 24
Finished Aug 11 05:33:24 PM PDT 24
Peak memory 229992 kb
Host smart-06377747-87f8-4ac6-9baf-0545bc53efdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770789530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2770789530
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2682045346
Short name T1592
Test name
Test status
Simulation time 4786519021 ps
CPU time 5.16 seconds
Started Aug 11 05:33:07 PM PDT 24
Finished Aug 11 05:33:12 PM PDT 24
Peak memory 221104 kb
Host smart-222d89c5-3170-4d9c-9617-8d0e3e4f18d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682045346 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2682045346
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1103387812
Short name T995
Test name
Test status
Simulation time 177214267 ps
CPU time 1.09 seconds
Started Aug 11 05:33:04 PM PDT 24
Finished Aug 11 05:33:05 PM PDT 24
Peak memory 205404 kb
Host smart-3633abf0-f6d1-4aef-8e0d-cbbc13968895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103387812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1103387812
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.2708494833
Short name T151
Test name
Test status
Simulation time 455509044 ps
CPU time 0.96 seconds
Started Aug 11 05:33:05 PM PDT 24
Finished Aug 11 05:33:06 PM PDT 24
Peak memory 205408 kb
Host smart-ad4e8298-dd46-4c20-9d08-493ff3ff7de2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708494833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.2708494833
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.2588288195
Short name T798
Test name
Test status
Simulation time 1117864504 ps
CPU time 3.06 seconds
Started Aug 11 05:33:09 PM PDT 24
Finished Aug 11 05:33:12 PM PDT 24
Peak memory 205616 kb
Host smart-b2190582-f846-4c51-a0a0-b046fbbda3d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588288195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.2588288195
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.936965343
Short name T1649
Test name
Test status
Simulation time 1049537817 ps
CPU time 1.4 seconds
Started Aug 11 05:33:09 PM PDT 24
Finished Aug 11 05:33:11 PM PDT 24
Peak memory 205456 kb
Host smart-b17c8d7b-a3ca-4c93-87a6-1735e5ecf65b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936965343 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.936965343
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.2833897414
Short name T1035
Test name
Test status
Simulation time 3655121246 ps
CPU time 3.71 seconds
Started Aug 11 05:33:03 PM PDT 24
Finished Aug 11 05:33:07 PM PDT 24
Peak memory 209276 kb
Host smart-af7673b2-3a2c-423f-a77b-e5c64b8cb409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833897414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.2833897414
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.127658280
Short name T557
Test name
Test status
Simulation time 1967193007 ps
CPU time 6.33 seconds
Started Aug 11 05:33:06 PM PDT 24
Finished Aug 11 05:33:13 PM PDT 24
Peak memory 210808 kb
Host smart-9ccf349e-35df-41e6-b857-9cc36460a11e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127658280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_intr_smoke.127658280
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.515480939
Short name T1585
Test name
Test status
Simulation time 8203051181 ps
CPU time 89.14 seconds
Started Aug 11 05:33:04 PM PDT 24
Finished Aug 11 05:34:33 PM PDT 24
Peak memory 2048936 kb
Host smart-93bd1436-2500-4f00-9230-0fe79704a565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515480939 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.515480939
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull.1161659287
Short name T1644
Test name
Test status
Simulation time 547593402 ps
CPU time 3.01 seconds
Started Aug 11 05:33:03 PM PDT 24
Finished Aug 11 05:33:06 PM PDT 24
Peak memory 213772 kb
Host smart-011aa97d-b7bf-482c-a284-1acb2dd3d3c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161659287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_acqfull.1161659287
Directory /workspace/43.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/43.i2c_target_nack_acqfull_addr.1539605605
Short name T934
Test name
Test status
Simulation time 504621102 ps
CPU time 2.87 seconds
Started Aug 11 05:33:11 PM PDT 24
Finished Aug 11 05:33:14 PM PDT 24
Peak memory 206284 kb
Host smart-9bd7a181-21f9-498b-8fe0-486f53f04a26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539605605 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.1539605605
Directory /workspace/43.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/43.i2c_target_perf.1296699993
Short name T1137
Test name
Test status
Simulation time 2614943442 ps
CPU time 4.76 seconds
Started Aug 11 05:33:06 PM PDT 24
Finished Aug 11 05:33:11 PM PDT 24
Peak memory 217680 kb
Host smart-a0a0e9fb-f31c-454f-8aa3-4ad2ec400a5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296699993 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.1296699993
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smbus_maxlen.2097285212
Short name T346
Test name
Test status
Simulation time 518944211 ps
CPU time 2.47 seconds
Started Aug 11 05:33:04 PM PDT 24
Finished Aug 11 05:33:06 PM PDT 24
Peak memory 205332 kb
Host smart-4837a09e-50eb-4992-85ee-0fc28db05470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097285212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_smbus_maxlen.2097285212
Directory /workspace/43.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2592500283
Short name T668
Test name
Test status
Simulation time 2197798067 ps
CPU time 14.04 seconds
Started Aug 11 05:33:05 PM PDT 24
Finished Aug 11 05:33:19 PM PDT 24
Peak memory 213972 kb
Host smart-69a91514-03f0-496a-a15e-76eddf5fa4ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592500283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2592500283
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.816501707
Short name T845
Test name
Test status
Simulation time 57196926634 ps
CPU time 84.9 seconds
Started Aug 11 05:33:02 PM PDT 24
Finished Aug 11 05:34:27 PM PDT 24
Peak memory 895484 kb
Host smart-22a67c38-656a-4385-9a37-a2207d9b2603
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816501707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_target_stress_all.816501707
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2703390568
Short name T831
Test name
Test status
Simulation time 1330481787 ps
CPU time 3.57 seconds
Started Aug 11 05:33:02 PM PDT 24
Finished Aug 11 05:33:06 PM PDT 24
Peak memory 205624 kb
Host smart-95b88cc8-4d54-4bb0-889a-db611a1b9d21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703390568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2703390568
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.1094898932
Short name T592
Test name
Test status
Simulation time 55211347790 ps
CPU time 103.3 seconds
Started Aug 11 05:33:04 PM PDT 24
Finished Aug 11 05:34:48 PM PDT 24
Peak memory 1292376 kb
Host smart-92dbe830-9cb3-4b30-9cbc-890cec3798cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094898932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.1094898932
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.3462105703
Short name T84
Test name
Test status
Simulation time 1711084115 ps
CPU time 9.11 seconds
Started Aug 11 05:33:05 PM PDT 24
Finished Aug 11 05:33:14 PM PDT 24
Peak memory 242180 kb
Host smart-8b47df26-aaa8-4ce6-a135-51cc86a6bca8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462105703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.3462105703
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.565878768
Short name T1237
Test name
Test status
Simulation time 2609581109 ps
CPU time 7.17 seconds
Started Aug 11 05:33:05 PM PDT 24
Finished Aug 11 05:33:12 PM PDT 24
Peak memory 222076 kb
Host smart-6e2dff8d-2232-4cc9-b0b0-aeb9b292b844
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565878768 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.565878768
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.3327887635
Short name T583
Test name
Test status
Simulation time 70048700 ps
CPU time 1.64 seconds
Started Aug 11 05:33:03 PM PDT 24
Finished Aug 11 05:33:05 PM PDT 24
Peak memory 205668 kb
Host smart-b0b2a63d-dc31-484a-9eae-cbffe7730611
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327887635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.3327887635
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2405035869
Short name T397
Test name
Test status
Simulation time 133512307 ps
CPU time 0.65 seconds
Started Aug 11 05:33:18 PM PDT 24
Finished Aug 11 05:33:19 PM PDT 24
Peak memory 204680 kb
Host smart-1790951f-ac1f-41bd-9ca7-7f4f2e0053a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405035869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2405035869
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2994504540
Short name T1523
Test name
Test status
Simulation time 1571555283 ps
CPU time 2.23 seconds
Started Aug 11 05:33:14 PM PDT 24
Finished Aug 11 05:33:16 PM PDT 24
Peak memory 213804 kb
Host smart-fd6c7f0a-f29c-4fa5-8dd0-8615d16a47bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994504540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2994504540
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2351360569
Short name T329
Test name
Test status
Simulation time 639622763 ps
CPU time 13.41 seconds
Started Aug 11 05:33:13 PM PDT 24
Finished Aug 11 05:33:26 PM PDT 24
Peak memory 346756 kb
Host smart-5197102e-33cf-43f5-ac21-3dc5562c246a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351360569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2351360569
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1024595063
Short name T1060
Test name
Test status
Simulation time 3604244822 ps
CPU time 248.76 seconds
Started Aug 11 05:33:13 PM PDT 24
Finished Aug 11 05:37:22 PM PDT 24
Peak memory 805452 kb
Host smart-1470df21-5053-45e0-8d3f-b6a4eabf77ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024595063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1024595063
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3091289951
Short name T1236
Test name
Test status
Simulation time 2292171526 ps
CPU time 165.22 seconds
Started Aug 11 05:33:12 PM PDT 24
Finished Aug 11 05:35:57 PM PDT 24
Peak memory 731872 kb
Host smart-9770ffc4-84b1-455c-b65b-39577a0f9ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091289951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3091289951
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3200766228
Short name T1223
Test name
Test status
Simulation time 645606780 ps
CPU time 1.02 seconds
Started Aug 11 05:33:11 PM PDT 24
Finished Aug 11 05:33:12 PM PDT 24
Peak memory 205212 kb
Host smart-3b8b54e2-c7f9-480b-9140-4128c3cd9427
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200766228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3200766228
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1915991724
Short name T1023
Test name
Test status
Simulation time 154524296 ps
CPU time 7.68 seconds
Started Aug 11 05:33:14 PM PDT 24
Finished Aug 11 05:33:22 PM PDT 24
Peak memory 205540 kb
Host smart-d83aeae0-f2d3-471a-abf2-45d2325b3a7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915991724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1915991724
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.1414558109
Short name T147
Test name
Test status
Simulation time 2629920632 ps
CPU time 141.28 seconds
Started Aug 11 05:33:11 PM PDT 24
Finished Aug 11 05:35:32 PM PDT 24
Peak memory 701276 kb
Host smart-b29060f2-3f42-4c76-bc2d-2edfa60399d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414558109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.1414558109
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_override.3264319911
Short name T1362
Test name
Test status
Simulation time 44544253 ps
CPU time 0.71 seconds
Started Aug 11 05:33:11 PM PDT 24
Finished Aug 11 05:33:12 PM PDT 24
Peak memory 205196 kb
Host smart-b477a1f0-ce25-4c89-bbb8-109d4e706200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264319911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3264319911
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.52014151
Short name T448
Test name
Test status
Simulation time 631390331 ps
CPU time 7.46 seconds
Started Aug 11 05:33:13 PM PDT 24
Finished Aug 11 05:33:20 PM PDT 24
Peak memory 230072 kb
Host smart-fe58429f-e69e-4b01-a7db-1713955e75d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52014151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.52014151
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.2083021862
Short name T554
Test name
Test status
Simulation time 1914819971 ps
CPU time 23.3 seconds
Started Aug 11 05:33:13 PM PDT 24
Finished Aug 11 05:33:36 PM PDT 24
Peak memory 205456 kb
Host smart-951c14ad-e332-443a-84f4-926878fe86c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083021862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.2083021862
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.618730154
Short name T196
Test name
Test status
Simulation time 2572123301 ps
CPU time 61.45 seconds
Started Aug 11 05:33:11 PM PDT 24
Finished Aug 11 05:34:12 PM PDT 24
Peak memory 327512 kb
Host smart-3508c4fc-aaa6-4b6e-83da-d8d0e3b021ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618730154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.618730154
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.2364039096
Short name T1339
Test name
Test status
Simulation time 16958527225 ps
CPU time 1837.81 seconds
Started Aug 11 05:33:08 PM PDT 24
Finished Aug 11 06:03:46 PM PDT 24
Peak memory 2413416 kb
Host smart-3292c2a4-84cf-497b-aa86-a5045be20b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364039096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.2364039096
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.3588749008
Short name T1281
Test name
Test status
Simulation time 551205796 ps
CPU time 26.74 seconds
Started Aug 11 05:33:13 PM PDT 24
Finished Aug 11 05:33:40 PM PDT 24
Peak memory 213688 kb
Host smart-a9ae0b86-25ea-4bea-b651-4f9931e8b510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588749008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.3588749008
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.744366384
Short name T1425
Test name
Test status
Simulation time 1613204209 ps
CPU time 3.87 seconds
Started Aug 11 05:33:18 PM PDT 24
Finished Aug 11 05:33:22 PM PDT 24
Peak memory 213820 kb
Host smart-3f74fda3-58ce-4a32-9082-7ca74bbd2814
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744366384 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.744366384
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1225175504
Short name T46
Test name
Test status
Simulation time 252672403 ps
CPU time 0.86 seconds
Started Aug 11 05:33:17 PM PDT 24
Finished Aug 11 05:33:18 PM PDT 24
Peak memory 205428 kb
Host smart-ffaafaf4-9080-42cb-841e-20097aef959a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225175504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1225175504
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.4265592331
Short name T348
Test name
Test status
Simulation time 587076695 ps
CPU time 1.1 seconds
Started Aug 11 05:33:20 PM PDT 24
Finished Aug 11 05:33:21 PM PDT 24
Peak memory 205692 kb
Host smart-d77f3736-c762-41e3-807c-cab8fdd8707a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265592331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.4265592331
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.2876924087
Short name T1522
Test name
Test status
Simulation time 1340203271 ps
CPU time 2.17 seconds
Started Aug 11 05:33:18 PM PDT 24
Finished Aug 11 05:33:20 PM PDT 24
Peak memory 205416 kb
Host smart-dc74ccb5-e93e-43af-8c99-5e9717eca009
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876924087 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.2876924087
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.4163097385
Short name T1004
Test name
Test status
Simulation time 171421510 ps
CPU time 1.27 seconds
Started Aug 11 05:33:19 PM PDT 24
Finished Aug 11 05:33:20 PM PDT 24
Peak memory 205440 kb
Host smart-a4351d8b-8699-437e-a08b-0c7eb779b40f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163097385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.4163097385
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1577651472
Short name T1402
Test name
Test status
Simulation time 379773856 ps
CPU time 1.67 seconds
Started Aug 11 05:33:19 PM PDT 24
Finished Aug 11 05:33:21 PM PDT 24
Peak memory 213872 kb
Host smart-e2cbf836-2514-4a34-8497-afe214f156de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577651472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1577651472
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.4216229531
Short name T750
Test name
Test status
Simulation time 4094877443 ps
CPU time 5.38 seconds
Started Aug 11 05:33:12 PM PDT 24
Finished Aug 11 05:33:17 PM PDT 24
Peak memory 220624 kb
Host smart-c0bcda08-a454-443b-bc7f-c149e1936f84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216229531 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.4216229531
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1513134928
Short name T1085
Test name
Test status
Simulation time 4791268689 ps
CPU time 20.03 seconds
Started Aug 11 05:33:10 PM PDT 24
Finished Aug 11 05:33:30 PM PDT 24
Peak memory 705408 kb
Host smart-91a5203f-b34e-498c-9739-7b69aa43eab4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513134928 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1513134928
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull.3541514635
Short name T508
Test name
Test status
Simulation time 520381295 ps
CPU time 2.7 seconds
Started Aug 11 05:33:19 PM PDT 24
Finished Aug 11 05:33:22 PM PDT 24
Peak memory 213844 kb
Host smart-8b89b528-bfe9-4724-ac5e-52080041f950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541514635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_nack_acqfull.3541514635
Directory /workspace/44.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/44.i2c_target_nack_acqfull_addr.351243059
Short name T1426
Test name
Test status
Simulation time 4903611938 ps
CPU time 2.48 seconds
Started Aug 11 05:33:21 PM PDT 24
Finished Aug 11 05:33:23 PM PDT 24
Peak memory 205756 kb
Host smart-127f2e0c-a18e-40aa-8daf-9197a4fc719b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351243059 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.351243059
Directory /workspace/44.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/44.i2c_target_nack_txstretch.2307474238
Short name T1025
Test name
Test status
Simulation time 1663658827 ps
CPU time 1.63 seconds
Started Aug 11 05:33:21 PM PDT 24
Finished Aug 11 05:33:22 PM PDT 24
Peak memory 222448 kb
Host smart-2c5745b5-09ab-4ae3-a2f1-782919773ec0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307474238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_nack_txstretch.2307474238
Directory /workspace/44.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/44.i2c_target_perf.578809743
Short name T572
Test name
Test status
Simulation time 8441623174 ps
CPU time 4.4 seconds
Started Aug 11 05:33:18 PM PDT 24
Finished Aug 11 05:33:22 PM PDT 24
Peak memory 214008 kb
Host smart-c9ecb82b-e2ac-4966-b5d0-680323f25525
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578809743 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_perf.578809743
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smbus_maxlen.2567318652
Short name T1665
Test name
Test status
Simulation time 489691216 ps
CPU time 2.13 seconds
Started Aug 11 05:33:22 PM PDT 24
Finished Aug 11 05:33:24 PM PDT 24
Peak memory 205700 kb
Host smart-a12c63c4-1e2a-4c59-bb83-94a78bbf8c45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567318652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_smbus_maxlen.2567318652
Directory /workspace/44.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.1978228078
Short name T475
Test name
Test status
Simulation time 11387879925 ps
CPU time 12.7 seconds
Started Aug 11 05:33:13 PM PDT 24
Finished Aug 11 05:33:26 PM PDT 24
Peak memory 213912 kb
Host smart-d5c1021e-1f47-42e5-9b37-1104fe1a5fb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978228078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.1978228078
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.3192595162
Short name T1469
Test name
Test status
Simulation time 175212204360 ps
CPU time 117.93 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:35:22 PM PDT 24
Peak memory 774140 kb
Host smart-06238b6b-1402-45b2-a54d-b74560cae1dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192595162 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_stress_all.3192595162
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1213320898
Short name T1563
Test name
Test status
Simulation time 963271806 ps
CPU time 35.56 seconds
Started Aug 11 05:33:13 PM PDT 24
Finished Aug 11 05:33:49 PM PDT 24
Peak memory 213816 kb
Host smart-908aa65a-2ee8-44bf-8a0d-9128cce35397
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213320898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1213320898
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.309971367
Short name T1479
Test name
Test status
Simulation time 26189899518 ps
CPU time 121.2 seconds
Started Aug 11 05:33:10 PM PDT 24
Finished Aug 11 05:35:12 PM PDT 24
Peak memory 1735536 kb
Host smart-de041ed4-cb31-444f-a494-9e2b6ed4b980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309971367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.309971367
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3670731297
Short name T133
Test name
Test status
Simulation time 2894060218 ps
CPU time 17.84 seconds
Started Aug 11 05:33:12 PM PDT 24
Finished Aug 11 05:33:30 PM PDT 24
Peak memory 280724 kb
Host smart-2304b9ac-87ab-4a1d-9409-90247f5d9117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670731297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3670731297
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2386847946
Short name T1611
Test name
Test status
Simulation time 5381091603 ps
CPU time 7.23 seconds
Started Aug 11 05:33:11 PM PDT 24
Finished Aug 11 05:33:18 PM PDT 24
Peak memory 214148 kb
Host smart-2e4ba9ff-e58b-4122-a949-759fa394fe93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386847946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2386847946
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.1586968090
Short name T57
Test name
Test status
Simulation time 83645757 ps
CPU time 1.6 seconds
Started Aug 11 05:33:21 PM PDT 24
Finished Aug 11 05:33:23 PM PDT 24
Peak memory 214516 kb
Host smart-998bac0b-cfe0-479b-870b-cee559cb2b4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586968090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.1586968090
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1430177388
Short name T326
Test name
Test status
Simulation time 18812596 ps
CPU time 0.64 seconds
Started Aug 11 05:33:28 PM PDT 24
Finished Aug 11 05:33:29 PM PDT 24
Peak memory 204704 kb
Host smart-1e4b4f12-6fce-41c9-8196-6691e2462741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430177388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1430177388
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3405582356
Short name T386
Test name
Test status
Simulation time 469117290 ps
CPU time 2.67 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:33:26 PM PDT 24
Peak memory 219852 kb
Host smart-2d7ef11c-2d11-4c80-aff4-f42b26808c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405582356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3405582356
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2271277744
Short name T1695
Test name
Test status
Simulation time 464638473 ps
CPU time 5.86 seconds
Started Aug 11 05:33:20 PM PDT 24
Finished Aug 11 05:33:26 PM PDT 24
Peak memory 254996 kb
Host smart-0b0df344-8562-4f19-a951-db0a955d32aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271277744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2271277744
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3138663154
Short name T432
Test name
Test status
Simulation time 6125992764 ps
CPU time 143.07 seconds
Started Aug 11 05:33:21 PM PDT 24
Finished Aug 11 05:35:44 PM PDT 24
Peak memory 493448 kb
Host smart-651aa7ed-6c5b-4d03-9a41-513475022d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138663154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3138663154
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2857195433
Short name T635
Test name
Test status
Simulation time 2109010237 ps
CPU time 51.6 seconds
Started Aug 11 05:33:16 PM PDT 24
Finished Aug 11 05:34:08 PM PDT 24
Peak memory 585380 kb
Host smart-9a726d7b-7a8b-4d83-b93c-c6b36da107e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857195433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2857195433
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.4111532795
Short name T1120
Test name
Test status
Simulation time 370344333 ps
CPU time 0.97 seconds
Started Aug 11 05:33:18 PM PDT 24
Finished Aug 11 05:33:19 PM PDT 24
Peak memory 205268 kb
Host smart-0c453913-b031-4ef5-88ea-84d71252b621
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111532795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.4111532795
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1021484450
Short name T1739
Test name
Test status
Simulation time 753753316 ps
CPU time 4.47 seconds
Started Aug 11 05:33:17 PM PDT 24
Finished Aug 11 05:33:21 PM PDT 24
Peak memory 205556 kb
Host smart-fd399611-eee0-4079-89b7-95aceec3c353
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021484450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1021484450
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2142018719
Short name T113
Test name
Test status
Simulation time 5035371869 ps
CPU time 134.87 seconds
Started Aug 11 05:33:22 PM PDT 24
Finished Aug 11 05:35:37 PM PDT 24
Peak memory 1476536 kb
Host smart-5ba99708-0923-4603-821c-30c23073a2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142018719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2142018719
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2996493779
Short name T1127
Test name
Test status
Simulation time 485782959 ps
CPU time 5.33 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:33:31 PM PDT 24
Peak memory 205408 kb
Host smart-367b4da4-ecb1-4f72-9df5-2d6b4ecb3e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996493779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2996493779
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.638276135
Short name T1415
Test name
Test status
Simulation time 159717625 ps
CPU time 2.16 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:33:27 PM PDT 24
Peak memory 213652 kb
Host smart-aeedc710-d50b-4dd8-a15c-125e80143d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638276135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.638276135
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.2379968119
Short name T1630
Test name
Test status
Simulation time 18019661 ps
CPU time 0.65 seconds
Started Aug 11 05:33:19 PM PDT 24
Finished Aug 11 05:33:20 PM PDT 24
Peak memory 205268 kb
Host smart-128aa691-0b0a-4204-bfdb-5e11f28eaca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379968119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2379968119
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.1472857007
Short name T1519
Test name
Test status
Simulation time 5425116206 ps
CPU time 22.9 seconds
Started Aug 11 05:33:19 PM PDT 24
Finished Aug 11 05:33:42 PM PDT 24
Peak memory 365060 kb
Host smart-2b6903d9-fbb5-4f5a-8ec3-64197585e3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472857007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1472857007
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.1501843871
Short name T1089
Test name
Test status
Simulation time 71098980 ps
CPU time 2.35 seconds
Started Aug 11 05:33:21 PM PDT 24
Finished Aug 11 05:33:24 PM PDT 24
Peak memory 215452 kb
Host smart-ab862687-edde-4d46-a0c7-8e6ba7f3eace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501843871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1501843871
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2775131823
Short name T1390
Test name
Test status
Simulation time 12302459326 ps
CPU time 22.33 seconds
Started Aug 11 05:33:18 PM PDT 24
Finished Aug 11 05:33:40 PM PDT 24
Peak memory 298916 kb
Host smart-e893d0ec-8325-4fd2-95b6-b6b4fed39cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775131823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2775131823
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.1959594934
Short name T195
Test name
Test status
Simulation time 3463367988 ps
CPU time 41.38 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:34:06 PM PDT 24
Peak memory 213900 kb
Host smart-baed235b-dfaa-4127-ac26-afbdfb67f7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959594934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.1959594934
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.24344643
Short name T1370
Test name
Test status
Simulation time 4524493842 ps
CPU time 6.66 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:33:32 PM PDT 24
Peak memory 217224 kb
Host smart-83dd2e6a-731a-48a5-a407-b49fda2636bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24344643 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.24344643
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.3241004067
Short name T1692
Test name
Test status
Simulation time 256475845 ps
CPU time 1.88 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:33:26 PM PDT 24
Peak memory 208480 kb
Host smart-94a23095-74bd-4caf-bbf9-a6a0e2aedb05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241004067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.3241004067
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1820136312
Short name T1309
Test name
Test status
Simulation time 254992243 ps
CPU time 0.88 seconds
Started Aug 11 05:33:26 PM PDT 24
Finished Aug 11 05:33:27 PM PDT 24
Peak memory 205388 kb
Host smart-d78638a9-6e3a-4100-becd-c3bc29d8a90b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820136312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1820136312
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.4273638333
Short name T743
Test name
Test status
Simulation time 1296808489 ps
CPU time 2.08 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:33:28 PM PDT 24
Peak memory 205444 kb
Host smart-829ceb96-76b4-4b0a-9727-b05a86401797
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273638333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.4273638333
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.4152378091
Short name T1478
Test name
Test status
Simulation time 168213977 ps
CPU time 1.56 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:33:26 PM PDT 24
Peak memory 205468 kb
Host smart-69b0315a-6d3c-4005-9152-c94234178821
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152378091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.4152378091
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2545587391
Short name T376
Test name
Test status
Simulation time 920934234 ps
CPU time 5.13 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:33:30 PM PDT 24
Peak memory 221356 kb
Host smart-d96727c3-af36-40d7-a1fe-6a6d8ec381e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545587391 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2545587391
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2279147505
Short name T984
Test name
Test status
Simulation time 18332485785 ps
CPU time 129.63 seconds
Started Aug 11 05:33:22 PM PDT 24
Finished Aug 11 05:35:32 PM PDT 24
Peak memory 2260656 kb
Host smart-dc7f2d09-ad35-442d-9aa2-4abda3bf4e4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279147505 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2279147505
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull.233961448
Short name T1214
Test name
Test status
Simulation time 3175515876 ps
CPU time 3.02 seconds
Started Aug 11 05:33:28 PM PDT 24
Finished Aug 11 05:33:31 PM PDT 24
Peak memory 214012 kb
Host smart-d29e5bce-beb9-4dda-9787-fd31ab582d23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233961448 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_nack_acqfull.233961448
Directory /workspace/45.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/45.i2c_target_nack_acqfull_addr.1956381888
Short name T1393
Test name
Test status
Simulation time 2196365872 ps
CPU time 2.91 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:33:28 PM PDT 24
Peak memory 205748 kb
Host smart-f5141e4c-860f-46c7-9ca7-c11f70c971c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956381888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.i2c_target_nack_acqfull_addr.1956381888
Directory /workspace/45.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.13466811
Short name T1662
Test name
Test status
Simulation time 2788828851 ps
CPU time 5.15 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:33:31 PM PDT 24
Peak memory 222128 kb
Host smart-4ebac565-6c76-4d23-a3ea-3b37d03b8ffe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13466811 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.i2c_target_perf.13466811
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smbus_maxlen.93456438
Short name T1132
Test name
Test status
Simulation time 2180723345 ps
CPU time 2.24 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:33:27 PM PDT 24
Peak memory 205400 kb
Host smart-116ea1ff-51fd-48a5-a326-2c3602861e52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93456438 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.i2c_target_smbus_maxlen.93456438
Directory /workspace/45.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2603643477
Short name T1699
Test name
Test status
Simulation time 843277920 ps
CPU time 9.72 seconds
Started Aug 11 05:33:23 PM PDT 24
Finished Aug 11 05:33:32 PM PDT 24
Peak memory 221964 kb
Host smart-d95d5f9d-6619-4bec-8ae0-aa5fbde05586
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603643477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2603643477
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.1510862631
Short name T928
Test name
Test status
Simulation time 54609858621 ps
CPU time 590.34 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:43:16 PM PDT 24
Peak memory 4439528 kb
Host smart-f0da6409-7b09-4d2b-a260-401ebac757e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510862631 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.1510862631
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3786038902
Short name T1668
Test name
Test status
Simulation time 1634011449 ps
CPU time 25.69 seconds
Started Aug 11 05:33:28 PM PDT 24
Finished Aug 11 05:33:54 PM PDT 24
Peak memory 237824 kb
Host smart-16463fd8-3cd5-4589-9b52-c6004368fb9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786038902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3786038902
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.454373210
Short name T1001
Test name
Test status
Simulation time 14817491524 ps
CPU time 8.63 seconds
Started Aug 11 05:33:26 PM PDT 24
Finished Aug 11 05:33:34 PM PDT 24
Peak memory 205760 kb
Host smart-a93da490-b04f-455c-8652-e092d0875268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454373210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.454373210
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1886673769
Short name T1119
Test name
Test status
Simulation time 4587435497 ps
CPU time 112.7 seconds
Started Aug 11 05:33:21 PM PDT 24
Finished Aug 11 05:35:14 PM PDT 24
Peak memory 770512 kb
Host smart-894266df-2476-45e1-a7de-aaeb6d1891ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886673769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1886673769
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2316757064
Short name T1263
Test name
Test status
Simulation time 1030231394 ps
CPU time 6.19 seconds
Started Aug 11 05:33:26 PM PDT 24
Finished Aug 11 05:33:33 PM PDT 24
Peak memory 230216 kb
Host smart-c0d338dc-614e-427d-bf09-04fff45512a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316757064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2316757064
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.2897985510
Short name T867
Test name
Test status
Simulation time 293222571 ps
CPU time 3.8 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:33:28 PM PDT 24
Peak memory 205600 kb
Host smart-5856e169-4e51-4bdc-a71a-4c51a797a31f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897985510 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.2897985510
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1796198337
Short name T400
Test name
Test status
Simulation time 24550474 ps
CPU time 0.62 seconds
Started Aug 11 05:33:37 PM PDT 24
Finished Aug 11 05:33:37 PM PDT 24
Peak memory 204636 kb
Host smart-a3057ea1-57c6-4902-a9a2-0719dfb582f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796198337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1796198337
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1066926131
Short name T35
Test name
Test status
Simulation time 353728550 ps
CPU time 7.14 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:33:33 PM PDT 24
Peak memory 251548 kb
Host smart-8982b0f5-870d-4fd4-b42e-6d9e132e9c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066926131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1066926131
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3226988823
Short name T682
Test name
Test status
Simulation time 845727961 ps
CPU time 4.91 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:33:29 PM PDT 24
Peak memory 254280 kb
Host smart-94eb1794-c1a8-4eac-8cb4-2a2e463519e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226988823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3226988823
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.2409103575
Short name T844
Test name
Test status
Simulation time 3289696727 ps
CPU time 205.71 seconds
Started Aug 11 05:33:28 PM PDT 24
Finished Aug 11 05:36:53 PM PDT 24
Peak memory 470604 kb
Host smart-71943a87-8307-463f-a6aa-04b58f87dd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409103575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.2409103575
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.952628240
Short name T759
Test name
Test status
Simulation time 5265518048 ps
CPU time 72.81 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:34:38 PM PDT 24
Peak memory 735588 kb
Host smart-0ae99541-de38-4e22-a3df-23ae3184c8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952628240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.952628240
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2602102917
Short name T1044
Test name
Test status
Simulation time 138091445 ps
CPU time 1.25 seconds
Started Aug 11 05:33:29 PM PDT 24
Finished Aug 11 05:33:31 PM PDT 24
Peak memory 205308 kb
Host smart-27b781e3-2393-49e1-94cf-1952f38c8b23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602102917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2602102917
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.3725494712
Short name T1391
Test name
Test status
Simulation time 153829064 ps
CPU time 3.72 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:33:29 PM PDT 24
Peak memory 205540 kb
Host smart-11da1ccc-1451-4310-b7a0-fdbb2e3645d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725494712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.3725494712
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.2149405318
Short name T1187
Test name
Test status
Simulation time 5387321534 ps
CPU time 179.87 seconds
Started Aug 11 05:33:26 PM PDT 24
Finished Aug 11 05:36:26 PM PDT 24
Peak memory 1536996 kb
Host smart-8197c75a-3ed4-450b-b134-ff22b2a9a504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149405318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.2149405318
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1005428428
Short name T270
Test name
Test status
Simulation time 502741915 ps
CPU time 20.36 seconds
Started Aug 11 05:33:35 PM PDT 24
Finished Aug 11 05:33:56 PM PDT 24
Peak memory 205512 kb
Host smart-826fffe6-03e2-4dd8-92a9-136daacc1245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005428428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1005428428
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_override.3830715062
Short name T1211
Test name
Test status
Simulation time 168861869 ps
CPU time 0.65 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:33:25 PM PDT 24
Peak memory 205068 kb
Host smart-8114f47e-6bb8-4af8-8d91-8a5132ba01ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830715062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3830715062
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.416807822
Short name T734
Test name
Test status
Simulation time 5510964479 ps
CPU time 55.8 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:34:20 PM PDT 24
Peak memory 445712 kb
Host smart-7d901c82-967f-40a0-a142-5ada5f19d35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416807822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.416807822
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.2262693501
Short name T1539
Test name
Test status
Simulation time 2715682733 ps
CPU time 13.99 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:33:39 PM PDT 24
Peak memory 224168 kb
Host smart-b243f679-54dc-441b-8ac1-f916d28ff86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262693501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.2262693501
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.4018698617
Short name T1126
Test name
Test status
Simulation time 1591035949 ps
CPU time 26.91 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:33:51 PM PDT 24
Peak memory 327968 kb
Host smart-73fc3117-f422-491b-8233-4943273fef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018698617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.4018698617
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2975974025
Short name T1015
Test name
Test status
Simulation time 32874841932 ps
CPU time 591.41 seconds
Started Aug 11 05:33:27 PM PDT 24
Finished Aug 11 05:43:18 PM PDT 24
Peak memory 1111228 kb
Host smart-eaee9733-12bc-4899-b0d8-b2c1f892349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975974025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2975974025
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2134951746
Short name T889
Test name
Test status
Simulation time 531054989 ps
CPU time 23.18 seconds
Started Aug 11 05:33:24 PM PDT 24
Finished Aug 11 05:33:48 PM PDT 24
Peak memory 213648 kb
Host smart-209da90e-beea-4536-9fc2-fa81ca0d3659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134951746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2134951746
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.3366542079
Short name T1405
Test name
Test status
Simulation time 5513523051 ps
CPU time 6.56 seconds
Started Aug 11 05:33:31 PM PDT 24
Finished Aug 11 05:33:38 PM PDT 24
Peak memory 222100 kb
Host smart-6d4e324e-8b83-443a-bff6-645b72a8ee25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366542079 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.3366542079
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.163347523
Short name T1192
Test name
Test status
Simulation time 788466871 ps
CPU time 0.89 seconds
Started Aug 11 05:33:30 PM PDT 24
Finished Aug 11 05:33:32 PM PDT 24
Peak memory 205484 kb
Host smart-d08bb3fe-ac02-458d-bf85-0905c6336f66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163347523 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.163347523
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2157892725
Short name T1403
Test name
Test status
Simulation time 180335198 ps
CPU time 1.03 seconds
Started Aug 11 05:33:30 PM PDT 24
Finished Aug 11 05:33:31 PM PDT 24
Peak memory 205384 kb
Host smart-a8d16220-9918-4711-a6b2-cf44f52c7cc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157892725 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2157892725
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.103468013
Short name T1708
Test name
Test status
Simulation time 631202146 ps
CPU time 3.23 seconds
Started Aug 11 05:33:30 PM PDT 24
Finished Aug 11 05:33:34 PM PDT 24
Peak memory 205556 kb
Host smart-35c4f8a4-8ed9-403d-884f-9700a424615e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103468013 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.103468013
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.2171255104
Short name T1151
Test name
Test status
Simulation time 467936862 ps
CPU time 1.14 seconds
Started Aug 11 05:33:37 PM PDT 24
Finished Aug 11 05:33:38 PM PDT 24
Peak memory 205412 kb
Host smart-cf42f61c-766a-47d3-953e-879aaa40d41a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171255104 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.2171255104
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.4217728125
Short name T135
Test name
Test status
Simulation time 4143345350 ps
CPU time 4.06 seconds
Started Aug 11 05:33:29 PM PDT 24
Finished Aug 11 05:33:34 PM PDT 24
Peak memory 214024 kb
Host smart-9bc7c14c-eb90-4e11-9df8-24a25225efed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217728125 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.4217728125
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.730963937
Short name T857
Test name
Test status
Simulation time 23675490228 ps
CPU time 493.3 seconds
Started Aug 11 05:33:40 PM PDT 24
Finished Aug 11 05:41:53 PM PDT 24
Peak memory 3927408 kb
Host smart-1c87de98-1847-4507-a45c-837bfb5d3171
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730963937 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.730963937
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull.2773899856
Short name T782
Test name
Test status
Simulation time 483273322 ps
CPU time 2.76 seconds
Started Aug 11 05:33:37 PM PDT 24
Finished Aug 11 05:33:40 PM PDT 24
Peak memory 213780 kb
Host smart-a70d6504-b3cc-4382-8d62-7a5534d6e70d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773899856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_acqfull.2773899856
Directory /workspace/46.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/46.i2c_target_nack_acqfull_addr.3417827915
Short name T786
Test name
Test status
Simulation time 776466053 ps
CPU time 2.43 seconds
Started Aug 11 05:33:29 PM PDT 24
Finished Aug 11 05:33:32 PM PDT 24
Peak memory 205516 kb
Host smart-afc2dc8c-3aff-4db1-93fe-68ce875aeb9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417827915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.3417827915
Directory /workspace/46.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/46.i2c_target_nack_txstretch.1765386096
Short name T90
Test name
Test status
Simulation time 586780026 ps
CPU time 1.62 seconds
Started Aug 11 05:33:32 PM PDT 24
Finished Aug 11 05:33:34 PM PDT 24
Peak memory 222232 kb
Host smart-ce785768-8a59-48d8-acd6-68c7a008fb6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765386096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_nack_txstretch.1765386096
Directory /workspace/46.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/46.i2c_target_perf.1128798223
Short name T1607
Test name
Test status
Simulation time 865470202 ps
CPU time 5.82 seconds
Started Aug 11 05:33:31 PM PDT 24
Finished Aug 11 05:33:37 PM PDT 24
Peak memory 221736 kb
Host smart-74fc3f0d-be78-499d-82f9-b535aff1f603
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128798223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.1128798223
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smbus_maxlen.3698770248
Short name T1178
Test name
Test status
Simulation time 728515422 ps
CPU time 2.07 seconds
Started Aug 11 05:33:35 PM PDT 24
Finished Aug 11 05:33:38 PM PDT 24
Peak memory 205376 kb
Host smart-0d1f04f6-4275-4cd0-8a23-06ad0a1b5451
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698770248 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_smbus_maxlen.3698770248
Directory /workspace/46.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.921145685
Short name T81
Test name
Test status
Simulation time 1814263025 ps
CPU time 27.96 seconds
Started Aug 11 05:33:23 PM PDT 24
Finished Aug 11 05:33:51 PM PDT 24
Peak memory 213760 kb
Host smart-e7de831e-5776-4b20-ba23-0ee34eef8d60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921145685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.921145685
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.824483657
Short name T1411
Test name
Test status
Simulation time 26554373853 ps
CPU time 617.31 seconds
Started Aug 11 05:33:30 PM PDT 24
Finished Aug 11 05:43:48 PM PDT 24
Peak memory 4435412 kb
Host smart-5f0a2122-016f-41a2-ab77-187c05e330a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824483657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.i2c_target_stress_all.824483657
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1947673532
Short name T1429
Test name
Test status
Simulation time 1734104532 ps
CPU time 28.2 seconds
Started Aug 11 05:33:35 PM PDT 24
Finished Aug 11 05:34:04 PM PDT 24
Peak memory 222464 kb
Host smart-3e78e38d-c72b-4b23-ba7d-f620395efcc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947673532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1947673532
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.713600206
Short name T1070
Test name
Test status
Simulation time 38479275516 ps
CPU time 73.67 seconds
Started Aug 11 05:33:25 PM PDT 24
Finished Aug 11 05:34:39 PM PDT 24
Peak memory 1199884 kb
Host smart-a23e8722-5301-48d1-82e2-8a23e94ad811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713600206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_wr.713600206
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1979849972
Short name T1325
Test name
Test status
Simulation time 4672929250 ps
CPU time 130.72 seconds
Started Aug 11 05:33:32 PM PDT 24
Finished Aug 11 05:35:42 PM PDT 24
Peak memory 1145420 kb
Host smart-efd27c9a-ad73-45b1-a800-ca83b7f23d95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979849972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1979849972
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.379005049
Short name T951
Test name
Test status
Simulation time 1165005086 ps
CPU time 6.7 seconds
Started Aug 11 05:33:31 PM PDT 24
Finished Aug 11 05:33:38 PM PDT 24
Peak memory 213876 kb
Host smart-47c9ea71-fb2e-43df-864a-8f862054225d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379005049 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_timeout.379005049
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.747155010
Short name T886
Test name
Test status
Simulation time 173221321 ps
CPU time 3.71 seconds
Started Aug 11 05:33:28 PM PDT 24
Finished Aug 11 05:33:32 PM PDT 24
Peak memory 206780 kb
Host smart-aa3340f9-d26d-4f21-8bd3-f19c22c74f73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747155010 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.747155010
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2626038694
Short name T1191
Test name
Test status
Simulation time 39165918 ps
CPU time 0.64 seconds
Started Aug 11 05:33:45 PM PDT 24
Finished Aug 11 05:33:46 PM PDT 24
Peak memory 204664 kb
Host smart-487cea32-7707-401e-83b0-9f9ec0d62b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626038694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2626038694
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2005760906
Short name T25
Test name
Test status
Simulation time 4003485879 ps
CPU time 4.66 seconds
Started Aug 11 05:33:40 PM PDT 24
Finished Aug 11 05:33:44 PM PDT 24
Peak memory 231668 kb
Host smart-72747a63-b349-4cb0-9301-2d04d8e578d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005760906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2005760906
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3802346926
Short name T658
Test name
Test status
Simulation time 316099907 ps
CPU time 5.31 seconds
Started Aug 11 05:33:39 PM PDT 24
Finished Aug 11 05:33:45 PM PDT 24
Peak memory 263852 kb
Host smart-2046be72-1a62-49c5-98e9-9091121bf1da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802346926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3802346926
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2759460683
Short name T1682
Test name
Test status
Simulation time 5660725177 ps
CPU time 68.93 seconds
Started Aug 11 05:33:40 PM PDT 24
Finished Aug 11 05:34:50 PM PDT 24
Peak memory 331476 kb
Host smart-0504a1bc-4925-4bb0-a75a-441eef720f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759460683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2759460683
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2650939224
Short name T1153
Test name
Test status
Simulation time 1926880958 ps
CPU time 49.99 seconds
Started Aug 11 05:33:36 PM PDT 24
Finished Aug 11 05:34:26 PM PDT 24
Peak memory 601464 kb
Host smart-abb430c9-bd79-439f-b035-8108c50f7daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650939224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2650939224
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2463094464
Short name T409
Test name
Test status
Simulation time 103400559 ps
CPU time 1.09 seconds
Started Aug 11 05:33:39 PM PDT 24
Finished Aug 11 05:33:40 PM PDT 24
Peak memory 205300 kb
Host smart-85581647-28d7-4309-9723-a30794280816
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463094464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2463094464
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.868462680
Short name T753
Test name
Test status
Simulation time 619615449 ps
CPU time 3.69 seconds
Started Aug 11 05:33:44 PM PDT 24
Finished Aug 11 05:33:48 PM PDT 24
Peak memory 205420 kb
Host smart-bb2017cb-bc40-4037-a13c-1c0ef548454c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868462680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
868462680
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1345825112
Short name T1323
Test name
Test status
Simulation time 4034485889 ps
CPU time 113.8 seconds
Started Aug 11 05:33:40 PM PDT 24
Finished Aug 11 05:35:34 PM PDT 24
Peak memory 1172368 kb
Host smart-dbceacbb-43bb-498d-8926-5ff4a65aee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345825112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1345825112
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.2652768157
Short name T1583
Test name
Test status
Simulation time 718845091 ps
CPU time 5.86 seconds
Started Aug 11 05:33:53 PM PDT 24
Finished Aug 11 05:33:59 PM PDT 24
Peak memory 205464 kb
Host smart-fb8f39ef-9ff4-42a4-aba7-d859b089eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652768157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2652768157
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_override.3939619162
Short name T93
Test name
Test status
Simulation time 17459852 ps
CPU time 0.66 seconds
Started Aug 11 05:33:40 PM PDT 24
Finished Aug 11 05:33:41 PM PDT 24
Peak memory 205196 kb
Host smart-3de8274f-688d-48c0-82c3-2efe7e353e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939619162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.3939619162
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.3508222042
Short name T1361
Test name
Test status
Simulation time 300724335 ps
CPU time 5.47 seconds
Started Aug 11 05:33:40 PM PDT 24
Finished Aug 11 05:33:46 PM PDT 24
Peak memory 234700 kb
Host smart-f8faaae6-d5f6-4c62-ad47-9b5699f57002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508222042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3508222042
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.1319749116
Short name T949
Test name
Test status
Simulation time 81787884 ps
CPU time 1.27 seconds
Started Aug 11 05:33:43 PM PDT 24
Finished Aug 11 05:33:44 PM PDT 24
Peak memory 213572 kb
Host smart-32832965-6f22-4674-9357-9387c1d55eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319749116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.1319749116
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3637287998
Short name T261
Test name
Test status
Simulation time 21982506565 ps
CPU time 33.33 seconds
Started Aug 11 05:33:42 PM PDT 24
Finished Aug 11 05:34:15 PM PDT 24
Peak memory 374352 kb
Host smart-b1e8cdb3-7124-4561-b30a-da22e409385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637287998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3637287998
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.630569475
Short name T1627
Test name
Test status
Simulation time 1016694992 ps
CPU time 18.89 seconds
Started Aug 11 05:33:39 PM PDT 24
Finished Aug 11 05:33:58 PM PDT 24
Peak memory 230796 kb
Host smart-3a530e40-bade-4134-bd3e-1186899a0826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630569475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.630569475
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.4110929290
Short name T1488
Test name
Test status
Simulation time 2082082697 ps
CPU time 5.94 seconds
Started Aug 11 05:33:45 PM PDT 24
Finished Aug 11 05:33:51 PM PDT 24
Peak memory 213840 kb
Host smart-8eae72c7-1f8b-45be-b289-958aee2f81d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110929290 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.4110929290
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.317692118
Short name T1631
Test name
Test status
Simulation time 477419109 ps
CPU time 1.08 seconds
Started Aug 11 05:33:45 PM PDT 24
Finished Aug 11 05:33:46 PM PDT 24
Peak memory 205388 kb
Host smart-8beabf66-6fb9-4232-9a32-33c83e2c6503
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317692118 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.317692118
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2689512443
Short name T1406
Test name
Test status
Simulation time 1019937272 ps
CPU time 1.63 seconds
Started Aug 11 05:33:45 PM PDT 24
Finished Aug 11 05:33:47 PM PDT 24
Peak memory 205588 kb
Host smart-34131acc-8361-490e-9b36-496d7a18b3fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689512443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2689512443
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.2836273126
Short name T699
Test name
Test status
Simulation time 715699247 ps
CPU time 3.21 seconds
Started Aug 11 05:33:44 PM PDT 24
Finished Aug 11 05:33:47 PM PDT 24
Peak memory 205556 kb
Host smart-295ce1c3-4c1a-4a3a-b40d-59d255783092
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836273126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.2836273126
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.1882515824
Short name T804
Test name
Test status
Simulation time 669009514 ps
CPU time 1.52 seconds
Started Aug 11 05:33:46 PM PDT 24
Finished Aug 11 05:33:48 PM PDT 24
Peak memory 205484 kb
Host smart-6336f77f-cebb-466f-a3da-ff2bf85492f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882515824 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.1882515824
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.4191743882
Short name T1049
Test name
Test status
Simulation time 1691592555 ps
CPU time 2.92 seconds
Started Aug 11 05:33:45 PM PDT 24
Finished Aug 11 05:33:48 PM PDT 24
Peak memory 213872 kb
Host smart-fb1b8eda-b4f0-4e58-88ca-241fb64b6c10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191743882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.4191743882
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1709264199
Short name T502
Test name
Test status
Simulation time 1598415845 ps
CPU time 8.36 seconds
Started Aug 11 05:33:44 PM PDT 24
Finished Aug 11 05:33:52 PM PDT 24
Peak memory 213812 kb
Host smart-625625f9-c5b7-4469-b885-713c5baa9845
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709264199 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1709264199
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2002129375
Short name T1056
Test name
Test status
Simulation time 10986450788 ps
CPU time 11.24 seconds
Started Aug 11 05:33:38 PM PDT 24
Finished Aug 11 05:33:49 PM PDT 24
Peak memory 314688 kb
Host smart-b1ac35fc-3dc8-4240-83a6-53764e9f5df1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002129375 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2002129375
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull.2445244441
Short name T159
Test name
Test status
Simulation time 614573196 ps
CPU time 3.35 seconds
Started Aug 11 05:33:46 PM PDT 24
Finished Aug 11 05:33:50 PM PDT 24
Peak memory 213776 kb
Host smart-50ad3e58-81b8-497f-90a3-f6fb67ffca3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445244441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_nack_acqfull.2445244441
Directory /workspace/47.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/47.i2c_target_nack_acqfull_addr.3714371491
Short name T1016
Test name
Test status
Simulation time 458386476 ps
CPU time 2.79 seconds
Started Aug 11 05:33:51 PM PDT 24
Finished Aug 11 05:33:54 PM PDT 24
Peak memory 206900 kb
Host smart-885ee93c-62fb-4f0a-936a-894029522aea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714371491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_nack_acqfull_addr.3714371491
Directory /workspace/47.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/47.i2c_target_perf.416645725
Short name T1276
Test name
Test status
Simulation time 1542866572 ps
CPU time 6.16 seconds
Started Aug 11 05:33:44 PM PDT 24
Finished Aug 11 05:33:50 PM PDT 24
Peak memory 219072 kb
Host smart-99e6deef-137e-4bd1-a7db-be24cf02683d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416645725 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_perf.416645725
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smbus_maxlen.3824947436
Short name T1190
Test name
Test status
Simulation time 511967073 ps
CPU time 2.46 seconds
Started Aug 11 05:33:46 PM PDT 24
Finished Aug 11 05:33:48 PM PDT 24
Peak memory 205440 kb
Host smart-7e9e9816-9aab-451c-b454-ddd9998be6ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824947436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_smbus_maxlen.3824947436
Directory /workspace/47.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2818063806
Short name T50
Test name
Test status
Simulation time 702731538 ps
CPU time 9.48 seconds
Started Aug 11 05:33:39 PM PDT 24
Finished Aug 11 05:33:49 PM PDT 24
Peak memory 222052 kb
Host smart-606100a6-f35f-4473-bda9-af47895ec5b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818063806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2818063806
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.3804549950
Short name T1610
Test name
Test status
Simulation time 11675803263 ps
CPU time 47.22 seconds
Started Aug 11 05:33:45 PM PDT 24
Finished Aug 11 05:34:32 PM PDT 24
Peak memory 268056 kb
Host smart-d2fd411f-0386-4f0c-a456-4c0cc28aa959
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804549950 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.3804549950
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1217956484
Short name T1130
Test name
Test status
Simulation time 4007481680 ps
CPU time 18.18 seconds
Started Aug 11 05:33:42 PM PDT 24
Finished Aug 11 05:34:00 PM PDT 24
Peak memory 222068 kb
Host smart-0b9deea6-7841-485f-884f-2041fb36e309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217956484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1217956484
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.804639733
Short name T735
Test name
Test status
Simulation time 37033820777 ps
CPU time 24.56 seconds
Started Aug 11 05:33:37 PM PDT 24
Finished Aug 11 05:34:02 PM PDT 24
Peak memory 564136 kb
Host smart-c2d192e0-bf1c-4aff-933e-89a5d69fe39e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804639733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.804639733
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3142861202
Short name T1600
Test name
Test status
Simulation time 3257454352 ps
CPU time 61.46 seconds
Started Aug 11 05:33:40 PM PDT 24
Finished Aug 11 05:34:42 PM PDT 24
Peak memory 516968 kb
Host smart-0d4664c0-5520-443c-bf31-ba8308a9fe70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142861202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3142861202
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1384233379
Short name T948
Test name
Test status
Simulation time 1307064261 ps
CPU time 6.56 seconds
Started Aug 11 05:33:44 PM PDT 24
Finished Aug 11 05:33:51 PM PDT 24
Peak memory 213748 kb
Host smart-54e1f88b-0e70-42f8-bbb9-2ec55ac365bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384233379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1384233379
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.1874836031
Short name T1614
Test name
Test status
Simulation time 225605554 ps
CPU time 3.99 seconds
Started Aug 11 05:33:50 PM PDT 24
Finished Aug 11 05:33:54 PM PDT 24
Peak memory 205580 kb
Host smart-096f682c-6e9e-4cbc-a62f-7f4fd1cb394a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874836031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.1874836031
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.4276144808
Short name T1121
Test name
Test status
Simulation time 16023579 ps
CPU time 0.72 seconds
Started Aug 11 05:34:00 PM PDT 24
Finished Aug 11 05:34:01 PM PDT 24
Peak memory 204720 kb
Host smart-34c544ee-f3d2-4a2d-b941-581e3ebc71a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276144808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.4276144808
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.191371664
Short name T1647
Test name
Test status
Simulation time 732375676 ps
CPU time 8.96 seconds
Started Aug 11 05:33:45 PM PDT 24
Finished Aug 11 05:33:54 PM PDT 24
Peak memory 234124 kb
Host smart-94bd6066-200c-4df0-b810-0a5ad86a3f0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191371664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.191371664
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.337394166
Short name T719
Test name
Test status
Simulation time 28110227277 ps
CPU time 79.53 seconds
Started Aug 11 05:33:52 PM PDT 24
Finished Aug 11 05:35:11 PM PDT 24
Peak memory 551452 kb
Host smart-07aecceb-40cd-44fb-813b-a03d9f949b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337394166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.337394166
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2532570194
Short name T618
Test name
Test status
Simulation time 2081722165 ps
CPU time 58.7 seconds
Started Aug 11 05:33:45 PM PDT 24
Finished Aug 11 05:34:44 PM PDT 24
Peak memory 696956 kb
Host smart-b007073b-cbe8-4693-902b-e32eae8508d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532570194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2532570194
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1370539209
Short name T1569
Test name
Test status
Simulation time 644014144 ps
CPU time 1.4 seconds
Started Aug 11 05:33:49 PM PDT 24
Finished Aug 11 05:33:51 PM PDT 24
Peak memory 205340 kb
Host smart-e9bee16b-c4d7-4eed-9828-7332a5a1f272
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370539209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1370539209
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.2597805670
Short name T1014
Test name
Test status
Simulation time 579046295 ps
CPU time 3.4 seconds
Started Aug 11 05:33:45 PM PDT 24
Finished Aug 11 05:33:48 PM PDT 24
Peak memory 205560 kb
Host smart-decb6298-339d-4d1e-a94d-a2c0bcf31a58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597805670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.2597805670
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2589200784
Short name T1331
Test name
Test status
Simulation time 26739246346 ps
CPU time 385.37 seconds
Started Aug 11 05:33:45 PM PDT 24
Finished Aug 11 05:40:11 PM PDT 24
Peak memory 1502208 kb
Host smart-95f2bd8a-497b-4dbe-9286-d703617804c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589200784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2589200784
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.218186024
Short name T1213
Test name
Test status
Simulation time 465831529 ps
CPU time 7.03 seconds
Started Aug 11 05:34:00 PM PDT 24
Finished Aug 11 05:34:08 PM PDT 24
Peak memory 205472 kb
Host smart-015c3fa8-169c-4dbd-91fc-1817078657d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218186024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.218186024
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.2425919245
Short name T265
Test name
Test status
Simulation time 93453509 ps
CPU time 1.85 seconds
Started Aug 11 05:33:57 PM PDT 24
Finished Aug 11 05:33:59 PM PDT 24
Peak memory 205520 kb
Host smart-6548132d-dd1b-484d-9af0-25e4c7df6a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425919245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2425919245
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.2631705532
Short name T144
Test name
Test status
Simulation time 19638617 ps
CPU time 0.69 seconds
Started Aug 11 05:33:46 PM PDT 24
Finished Aug 11 05:33:47 PM PDT 24
Peak memory 205168 kb
Host smart-cef15b85-90ee-4261-a901-cc476bc0c458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631705532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2631705532
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.384612798
Short name T774
Test name
Test status
Simulation time 5874775979 ps
CPU time 82.05 seconds
Started Aug 11 05:33:48 PM PDT 24
Finished Aug 11 05:35:10 PM PDT 24
Peak memory 213780 kb
Host smart-afd0e88f-9245-41b6-b086-56b9794d6ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384612798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.384612798
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.1795108926
Short name T801
Test name
Test status
Simulation time 6742735453 ps
CPU time 32.46 seconds
Started Aug 11 05:33:47 PM PDT 24
Finished Aug 11 05:34:20 PM PDT 24
Peak memory 481028 kb
Host smart-a7c29710-5653-4ae2-b865-1d02cbee67da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795108926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1795108926
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.391209007
Short name T124
Test name
Test status
Simulation time 70893478569 ps
CPU time 943.26 seconds
Started Aug 11 05:33:52 PM PDT 24
Finished Aug 11 05:49:36 PM PDT 24
Peak memory 3824228 kb
Host smart-4a3a1c51-3498-4afa-8c53-278c11155685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391209007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.391209007
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3558350804
Short name T662
Test name
Test status
Simulation time 604183530 ps
CPU time 26.01 seconds
Started Aug 11 05:33:47 PM PDT 24
Finished Aug 11 05:34:13 PM PDT 24
Peak memory 213680 kb
Host smart-afa11e36-b02c-4ddd-b2eb-1433a15edb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558350804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3558350804
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2191076079
Short name T667
Test name
Test status
Simulation time 1499952417 ps
CPU time 6.92 seconds
Started Aug 11 05:33:54 PM PDT 24
Finished Aug 11 05:34:01 PM PDT 24
Peak memory 210196 kb
Host smart-3c7ea5de-6556-4042-b464-ed3b939e97c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191076079 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2191076079
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.59773580
Short name T765
Test name
Test status
Simulation time 274216336 ps
CPU time 0.78 seconds
Started Aug 11 05:33:55 PM PDT 24
Finished Aug 11 05:33:55 PM PDT 24
Peak memory 205416 kb
Host smart-e91a9092-e936-440c-a9f6-d9c64f99e266
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59773580 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_fifo_reset_acq.59773580
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.4194707370
Short name T1321
Test name
Test status
Simulation time 253231613 ps
CPU time 1.61 seconds
Started Aug 11 05:33:52 PM PDT 24
Finished Aug 11 05:33:53 PM PDT 24
Peak memory 205628 kb
Host smart-13bfd44b-d6f8-4986-adf0-4ed28d6fa646
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194707370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.4194707370
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.2060604322
Short name T278
Test name
Test status
Simulation time 289664382 ps
CPU time 1.16 seconds
Started Aug 11 05:34:00 PM PDT 24
Finished Aug 11 05:34:01 PM PDT 24
Peak memory 205348 kb
Host smart-7c319314-762a-4050-b3f6-4bf721766439
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060604322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.2060604322
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.408937346
Short name T72
Test name
Test status
Simulation time 153541474 ps
CPU time 1.52 seconds
Started Aug 11 05:34:04 PM PDT 24
Finished Aug 11 05:34:06 PM PDT 24
Peak memory 205420 kb
Host smart-83796eb5-d3c6-45d0-b652-1a92001110c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408937346 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.408937346
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1644489180
Short name T1532
Test name
Test status
Simulation time 1350256762 ps
CPU time 3.85 seconds
Started Aug 11 05:33:53 PM PDT 24
Finished Aug 11 05:33:57 PM PDT 24
Peak memory 213824 kb
Host smart-f1abe33d-e961-42b5-b30c-65df68a7fb58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644489180 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1644489180
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.3626866439
Short name T1481
Test name
Test status
Simulation time 16646591044 ps
CPU time 86.45 seconds
Started Aug 11 05:33:53 PM PDT 24
Finished Aug 11 05:35:19 PM PDT 24
Peak memory 1249268 kb
Host smart-dd46ac05-c1f6-46df-b083-a929b0da9e4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626866439 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.3626866439
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull.188896681
Short name T567
Test name
Test status
Simulation time 1887102653 ps
CPU time 3.18 seconds
Started Aug 11 05:33:59 PM PDT 24
Finished Aug 11 05:34:02 PM PDT 24
Peak memory 213828 kb
Host smart-c858ca60-f386-43e0-87ad-c232a7c55488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188896681 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_nack_acqfull.188896681
Directory /workspace/48.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/48.i2c_target_nack_acqfull_addr.3034541212
Short name T549
Test name
Test status
Simulation time 2249133041 ps
CPU time 2.98 seconds
Started Aug 11 05:34:01 PM PDT 24
Finished Aug 11 05:34:04 PM PDT 24
Peak memory 205724 kb
Host smart-f658a750-4960-4dd1-9777-86f97ffd877f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034541212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_nack_acqfull_addr.3034541212
Directory /workspace/48.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.1235899568
Short name T1527
Test name
Test status
Simulation time 2991508878 ps
CPU time 5.16 seconds
Started Aug 11 05:33:53 PM PDT 24
Finished Aug 11 05:33:58 PM PDT 24
Peak memory 220584 kb
Host smart-ab74115d-cd5d-4f38-88b5-9b7d1352b40c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235899568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.1235899568
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smbus_maxlen.3127518256
Short name T769
Test name
Test status
Simulation time 2002497945 ps
CPU time 2.47 seconds
Started Aug 11 05:34:01 PM PDT 24
Finished Aug 11 05:34:04 PM PDT 24
Peak memory 205388 kb
Host smart-401e9870-b3a9-4462-8a0c-37e63c875693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127518256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_smbus_maxlen.3127518256
Directory /workspace/48.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2679536224
Short name T1008
Test name
Test status
Simulation time 1210388240 ps
CPU time 18.66 seconds
Started Aug 11 05:33:56 PM PDT 24
Finished Aug 11 05:34:15 PM PDT 24
Peak memory 213864 kb
Host smart-b923f4dc-ae87-4d41-b56a-5b257a19dc9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679536224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2679536224
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.3960962592
Short name T1374
Test name
Test status
Simulation time 27338604214 ps
CPU time 135.81 seconds
Started Aug 11 05:33:52 PM PDT 24
Finished Aug 11 05:36:08 PM PDT 24
Peak memory 1060448 kb
Host smart-ec2bbe35-4720-4c37-bb94-d1c2ba95efe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960962592 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_stress_all.3960962592
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2385383299
Short name T272
Test name
Test status
Simulation time 4630832944 ps
CPU time 19.06 seconds
Started Aug 11 05:33:55 PM PDT 24
Finished Aug 11 05:34:14 PM PDT 24
Peak memory 230260 kb
Host smart-191e36c8-9fa6-49b1-bef6-e195c76bbddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385383299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2385383299
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.2657809048
Short name T751
Test name
Test status
Simulation time 49843288505 ps
CPU time 157.52 seconds
Started Aug 11 05:33:52 PM PDT 24
Finished Aug 11 05:36:30 PM PDT 24
Peak memory 1951904 kb
Host smart-c333dd04-7c3d-4bf1-a025-576f07e26ef5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657809048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.2657809048
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.3748695556
Short name T1074
Test name
Test status
Simulation time 2137070657 ps
CPU time 4.32 seconds
Started Aug 11 05:33:52 PM PDT 24
Finished Aug 11 05:33:56 PM PDT 24
Peak memory 236724 kb
Host smart-931e1501-c90b-46bb-886b-1d227b737c97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748695556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.3748695556
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.2088934641
Short name T646
Test name
Test status
Simulation time 2158305127 ps
CPU time 6.35 seconds
Started Aug 11 05:33:52 PM PDT 24
Finished Aug 11 05:33:59 PM PDT 24
Peak memory 222184 kb
Host smart-50f1ef9e-7bcd-4fa6-9ae2-861ea4230b86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088934641 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.2088934641
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.447956621
Short name T1287
Test name
Test status
Simulation time 26493190 ps
CPU time 0.63 seconds
Started Aug 11 05:34:08 PM PDT 24
Finished Aug 11 05:34:08 PM PDT 24
Peak memory 205204 kb
Host smart-de651f8f-69eb-468f-bded-c68c2620dd9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447956621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.447956621
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.286653200
Short name T483
Test name
Test status
Simulation time 160801666 ps
CPU time 2.95 seconds
Started Aug 11 05:34:00 PM PDT 24
Finished Aug 11 05:34:03 PM PDT 24
Peak memory 230196 kb
Host smart-aa15b345-8db2-419f-a571-feccea124cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286653200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.286653200
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.22660679
Short name T706
Test name
Test status
Simulation time 655178373 ps
CPU time 6.69 seconds
Started Aug 11 05:34:00 PM PDT 24
Finished Aug 11 05:34:07 PM PDT 24
Peak memory 279932 kb
Host smart-584d918a-f783-487b-8a62-38b6a67cc7fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22660679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty
.22660679
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3248469427
Short name T368
Test name
Test status
Simulation time 2165112105 ps
CPU time 119 seconds
Started Aug 11 05:33:59 PM PDT 24
Finished Aug 11 05:35:58 PM PDT 24
Peak memory 373852 kb
Host smart-8e2d764e-daeb-41f8-81d1-89bc9bb3fa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248469427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3248469427
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.23305558
Short name T94
Test name
Test status
Simulation time 9997267972 ps
CPU time 190.28 seconds
Started Aug 11 05:34:01 PM PDT 24
Finished Aug 11 05:37:11 PM PDT 24
Peak memory 762848 kb
Host smart-7c22f217-badc-4f5b-a928-fdead204505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23305558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.23305558
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.670932746
Short name T1371
Test name
Test status
Simulation time 519083003 ps
CPU time 1 seconds
Started Aug 11 05:33:57 PM PDT 24
Finished Aug 11 05:33:58 PM PDT 24
Peak memory 205196 kb
Host smart-fba569c4-8af1-48e5-8b9b-e4d0112b7d1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670932746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fm
t.670932746
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.622742715
Short name T860
Test name
Test status
Simulation time 558932330 ps
CPU time 4.3 seconds
Started Aug 11 05:34:04 PM PDT 24
Finished Aug 11 05:34:08 PM PDT 24
Peak memory 233604 kb
Host smart-c5865068-d8ad-4fa1-8497-9ee503563390
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622742715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
622742715
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2075510306
Short name T747
Test name
Test status
Simulation time 18777142792 ps
CPU time 373.61 seconds
Started Aug 11 05:34:00 PM PDT 24
Finished Aug 11 05:40:14 PM PDT 24
Peak memory 1466908 kb
Host smart-46227c71-35c0-4938-9470-b47bd3668e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075510306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2075510306
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.785748853
Short name T1632
Test name
Test status
Simulation time 612269078 ps
CPU time 23.71 seconds
Started Aug 11 05:34:07 PM PDT 24
Finished Aug 11 05:34:31 PM PDT 24
Peak memory 205480 kb
Host smart-5edd5127-9947-4117-a47c-7250d78bc595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785748853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.785748853
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3821425615
Short name T266
Test name
Test status
Simulation time 608238483 ps
CPU time 2.13 seconds
Started Aug 11 05:34:07 PM PDT 24
Finished Aug 11 05:34:09 PM PDT 24
Peak memory 213704 kb
Host smart-7209ab73-5b52-4a95-b515-5b78c24d3e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821425615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3821425615
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.2362660185
Short name T1353
Test name
Test status
Simulation time 74250392 ps
CPU time 0.66 seconds
Started Aug 11 05:34:01 PM PDT 24
Finished Aug 11 05:34:01 PM PDT 24
Peak memory 205456 kb
Host smart-c893691f-59d7-4da1-b38d-5ac52d9198b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362660185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.2362660185
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.904912390
Short name T1294
Test name
Test status
Simulation time 1325693217 ps
CPU time 5.07 seconds
Started Aug 11 05:34:01 PM PDT 24
Finished Aug 11 05:34:06 PM PDT 24
Peak memory 220108 kb
Host smart-373f042c-f3de-4a29-8c9f-3fcea8f54278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904912390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.904912390
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.3898643064
Short name T129
Test name
Test status
Simulation time 5882845205 ps
CPU time 31.27 seconds
Started Aug 11 05:34:00 PM PDT 24
Finished Aug 11 05:34:31 PM PDT 24
Peak memory 205572 kb
Host smart-edfa7651-11c6-4ebd-bf20-a9920b988d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898643064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.3898643064
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.2869991280
Short name T894
Test name
Test status
Simulation time 15752436564 ps
CPU time 15.87 seconds
Started Aug 11 05:34:02 PM PDT 24
Finished Aug 11 05:34:18 PM PDT 24
Peak memory 303120 kb
Host smart-ce8b7dc9-8ba0-417c-bc5c-3c0ee99eaf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869991280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2869991280
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.1607048884
Short name T131
Test name
Test status
Simulation time 1864916238 ps
CPU time 40.88 seconds
Started Aug 11 05:33:59 PM PDT 24
Finished Aug 11 05:34:40 PM PDT 24
Peak memory 213736 kb
Host smart-aea0cd04-665e-4b1f-b56c-621cbd8afa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607048884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.1607048884
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.604810608
Short name T1480
Test name
Test status
Simulation time 1270331870 ps
CPU time 6.56 seconds
Started Aug 11 05:34:07 PM PDT 24
Finished Aug 11 05:34:14 PM PDT 24
Peak memory 214796 kb
Host smart-1b90dc43-a5eb-40e3-9a72-e94ea7d56eb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604810608 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.604810608
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.4116288357
Short name T853
Test name
Test status
Simulation time 224660622 ps
CPU time 1.48 seconds
Started Aug 11 05:34:02 PM PDT 24
Finished Aug 11 05:34:04 PM PDT 24
Peak memory 205824 kb
Host smart-20769996-90ba-4448-bb9e-73d454c2c012
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116288357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.4116288357
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3087443538
Short name T1326
Test name
Test status
Simulation time 117918603 ps
CPU time 0.93 seconds
Started Aug 11 05:34:00 PM PDT 24
Finished Aug 11 05:34:02 PM PDT 24
Peak memory 205468 kb
Host smart-10122519-ae40-4b15-8119-6c8bdea5ba27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087443538 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3087443538
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.2288566429
Short name T171
Test name
Test status
Simulation time 1238252776 ps
CPU time 3.56 seconds
Started Aug 11 05:34:07 PM PDT 24
Finished Aug 11 05:34:10 PM PDT 24
Peak memory 205580 kb
Host smart-2867f026-a49d-45b4-b2a0-2b9477b656e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288566429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.2288566429
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.834369865
Short name T1421
Test name
Test status
Simulation time 163305031 ps
CPU time 1.22 seconds
Started Aug 11 05:34:11 PM PDT 24
Finished Aug 11 05:34:13 PM PDT 24
Peak memory 205480 kb
Host smart-ac5df6f5-8685-4c67-8fe7-3452ff1aaf91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834369865 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.834369865
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.472234790
Short name T175
Test name
Test status
Simulation time 318005489 ps
CPU time 2.17 seconds
Started Aug 11 05:34:07 PM PDT 24
Finished Aug 11 05:34:09 PM PDT 24
Peak memory 213856 kb
Host smart-8a7e6dec-5b20-412f-a0c9-1f69e80add7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472234790 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.472234790
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2316033599
Short name T428
Test name
Test status
Simulation time 1497342711 ps
CPU time 8.11 seconds
Started Aug 11 05:34:01 PM PDT 24
Finished Aug 11 05:34:10 PM PDT 24
Peak memory 218396 kb
Host smart-ed7cfc49-44f1-459a-95bb-bf1757715d4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316033599 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2316033599
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.4040242347
Short name T637
Test name
Test status
Simulation time 5584050932 ps
CPU time 24.47 seconds
Started Aug 11 05:34:01 PM PDT 24
Finished Aug 11 05:34:26 PM PDT 24
Peak memory 795012 kb
Host smart-ed964d78-8992-466f-b6f5-43e39dcf098f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040242347 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.4040242347
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull.4153713690
Short name T67
Test name
Test status
Simulation time 476668054 ps
CPU time 2.67 seconds
Started Aug 11 05:34:08 PM PDT 24
Finished Aug 11 05:34:10 PM PDT 24
Peak memory 213748 kb
Host smart-b7502bdd-ddfb-4f41-977b-f88f7b7cc20b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153713690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_nack_acqfull.4153713690
Directory /workspace/49.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/49.i2c_target_nack_acqfull_addr.1536475029
Short name T485
Test name
Test status
Simulation time 417803468 ps
CPU time 2.58 seconds
Started Aug 11 05:34:10 PM PDT 24
Finished Aug 11 05:34:13 PM PDT 24
Peak memory 205604 kb
Host smart-b6340a65-c686-4215-b0d8-1b3551408e1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536475029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_nack_acqfull_addr.1536475029
Directory /workspace/49.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/49.i2c_target_nack_txstretch.2731363731
Short name T1100
Test name
Test status
Simulation time 133002276 ps
CPU time 1.54 seconds
Started Aug 11 05:34:09 PM PDT 24
Finished Aug 11 05:34:10 PM PDT 24
Peak memory 222204 kb
Host smart-2df44cdd-781d-46b1-9199-7a30a1013b23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731363731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_nack_txstretch.2731363731
Directory /workspace/49.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/49.i2c_target_perf.2277516335
Short name T832
Test name
Test status
Simulation time 2786730876 ps
CPU time 4.99 seconds
Started Aug 11 05:34:08 PM PDT 24
Finished Aug 11 05:34:13 PM PDT 24
Peak memory 213972 kb
Host smart-8b1deeb3-65d6-47d8-a302-e4dc6074ff16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277516335 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.2277516335
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smbus_maxlen.1346153860
Short name T959
Test name
Test status
Simulation time 2137875871 ps
CPU time 2.56 seconds
Started Aug 11 05:34:06 PM PDT 24
Finished Aug 11 05:34:08 PM PDT 24
Peak memory 205368 kb
Host smart-78e4d538-3b4a-410b-90b9-9a62a35c91ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346153860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_smbus_maxlen.1346153860
Directory /workspace/49.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.1896814161
Short name T823
Test name
Test status
Simulation time 491782835 ps
CPU time 16.25 seconds
Started Aug 11 05:34:00 PM PDT 24
Finished Aug 11 05:34:16 PM PDT 24
Peak memory 222072 kb
Host smart-844d6f4b-83b4-4a92-a468-dd447cbbccf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896814161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.1896814161
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.2314206363
Short name T941
Test name
Test status
Simulation time 44246638885 ps
CPU time 196.63 seconds
Started Aug 11 05:34:06 PM PDT 24
Finished Aug 11 05:37:23 PM PDT 24
Peak memory 1330676 kb
Host smart-d73fe5e5-9ece-4f22-bc29-310a5327d931
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314206363 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_stress_all.2314206363
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1553922121
Short name T115
Test name
Test status
Simulation time 977124331 ps
CPU time 18.94 seconds
Started Aug 11 05:34:02 PM PDT 24
Finished Aug 11 05:34:21 PM PDT 24
Peak memory 222428 kb
Host smart-7b2ea9ed-c20a-4ce1-a8a0-37eb580c2eb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553922121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1553922121
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2010703264
Short name T349
Test name
Test status
Simulation time 24773988072 ps
CPU time 85.08 seconds
Started Aug 11 05:34:01 PM PDT 24
Finished Aug 11 05:35:26 PM PDT 24
Peak memory 1275868 kb
Host smart-583a04fb-b89f-4ee7-8a63-2b8383b8711d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010703264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2010703264
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.2062416433
Short name T817
Test name
Test status
Simulation time 1674533283 ps
CPU time 2.73 seconds
Started Aug 11 05:34:00 PM PDT 24
Finished Aug 11 05:34:03 PM PDT 24
Peak memory 213840 kb
Host smart-1a6b61b1-be4c-43a4-b067-df735bb3102b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062416433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.2062416433
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1648317546
Short name T1579
Test name
Test status
Simulation time 1203577737 ps
CPU time 6.5 seconds
Started Aug 11 05:33:59 PM PDT 24
Finished Aug 11 05:34:05 PM PDT 24
Peak memory 222016 kb
Host smart-b94f6707-d786-4b09-a42b-a481f92ab673
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648317546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1648317546
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.3463257660
Short name T971
Test name
Test status
Simulation time 186089885 ps
CPU time 3.48 seconds
Started Aug 11 05:34:06 PM PDT 24
Finished Aug 11 05:34:09 PM PDT 24
Peak memory 205520 kb
Host smart-58e56d7f-5d65-42ba-ab3e-b9a7dcd06bb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463257660 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.3463257660
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.4090582739
Short name T396
Test name
Test status
Simulation time 64002503 ps
CPU time 0.62 seconds
Started Aug 11 05:26:31 PM PDT 24
Finished Aug 11 05:26:32 PM PDT 24
Peak memory 204692 kb
Host smart-d71d16a6-0505-4565-bd1a-bbd3020d450f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090582739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.4090582739
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2555674685
Short name T422
Test name
Test status
Simulation time 577223577 ps
CPU time 3.03 seconds
Started Aug 11 05:26:20 PM PDT 24
Finished Aug 11 05:26:23 PM PDT 24
Peak memory 230688 kb
Host smart-d3a4412e-b04c-4c93-84f4-4ff44470e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555674685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2555674685
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2905403355
Short name T362
Test name
Test status
Simulation time 430179518 ps
CPU time 5.94 seconds
Started Aug 11 05:26:18 PM PDT 24
Finished Aug 11 05:26:24 PM PDT 24
Peak memory 248708 kb
Host smart-db5ba8ea-cc80-4ddc-b155-111b87b6815b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905403355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2905403355
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3433634492
Short name T876
Test name
Test status
Simulation time 13969160005 ps
CPU time 305.82 seconds
Started Aug 11 05:26:21 PM PDT 24
Finished Aug 11 05:31:27 PM PDT 24
Peak memory 953688 kb
Host smart-3c7dbccc-038c-47d5-b0e1-b514999d5449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433634492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3433634492
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3433646191
Short name T983
Test name
Test status
Simulation time 3489417623 ps
CPU time 55.98 seconds
Started Aug 11 05:26:21 PM PDT 24
Finished Aug 11 05:27:18 PM PDT 24
Peak memory 622624 kb
Host smart-3bee57ed-bb63-46f3-a236-d8a9d3bb90bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433646191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3433646191
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.386641232
Short name T1446
Test name
Test status
Simulation time 1136746654 ps
CPU time 1.06 seconds
Started Aug 11 05:26:21 PM PDT 24
Finished Aug 11 05:26:23 PM PDT 24
Peak memory 205180 kb
Host smart-d8901be4-60d6-4349-9e1d-41749e4240e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386641232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt
.386641232
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3490381398
Short name T1684
Test name
Test status
Simulation time 129682789 ps
CPU time 3.26 seconds
Started Aug 11 05:26:19 PM PDT 24
Finished Aug 11 05:26:22 PM PDT 24
Peak memory 205420 kb
Host smart-c7ae24bf-505e-4df2-9dac-233ea3af75a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490381398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3490381398
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.2855198008
Short name T715
Test name
Test status
Simulation time 3450261113 ps
CPU time 224.39 seconds
Started Aug 11 05:26:22 PM PDT 24
Finished Aug 11 05:30:07 PM PDT 24
Peak memory 1021956 kb
Host smart-0df59c62-0f3c-47d2-89bb-75254f26e9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855198008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.2855198008
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2249635598
Short name T257
Test name
Test status
Simulation time 414469232 ps
CPU time 17.08 seconds
Started Aug 11 05:26:26 PM PDT 24
Finished Aug 11 05:26:44 PM PDT 24
Peak memory 205456 kb
Host smart-687b0404-7b22-415f-8716-6b482aaa681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249635598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2249635598
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_override.2183983816
Short name T1133
Test name
Test status
Simulation time 112565974 ps
CPU time 0.76 seconds
Started Aug 11 05:26:20 PM PDT 24
Finished Aug 11 05:26:21 PM PDT 24
Peak memory 205196 kb
Host smart-7c2aed10-fbea-465e-adb4-98318dc401a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183983816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2183983816
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3103565448
Short name T1306
Test name
Test status
Simulation time 4787544147 ps
CPU time 56.62 seconds
Started Aug 11 05:26:20 PM PDT 24
Finished Aug 11 05:27:17 PM PDT 24
Peak memory 361216 kb
Host smart-a2822720-08b1-4518-a31e-1f8d4c25bbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103565448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3103565448
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.1378143910
Short name T300
Test name
Test status
Simulation time 303327300 ps
CPU time 2.22 seconds
Started Aug 11 05:26:21 PM PDT 24
Finished Aug 11 05:26:23 PM PDT 24
Peak memory 220496 kb
Host smart-6af92109-dcd1-48e3-91a9-44201c2ba2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378143910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.1378143910
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.994853668
Short name T471
Test name
Test status
Simulation time 2871955356 ps
CPU time 69.22 seconds
Started Aug 11 05:26:21 PM PDT 24
Finished Aug 11 05:27:30 PM PDT 24
Peak memory 343592 kb
Host smart-54c64044-ddbf-4abf-bdc0-e842d0507f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994853668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.994853668
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2683550735
Short name T1073
Test name
Test status
Simulation time 6408106238 ps
CPU time 33.13 seconds
Started Aug 11 05:26:17 PM PDT 24
Finished Aug 11 05:26:50 PM PDT 24
Peak memory 213772 kb
Host smart-6f38a08e-a7a5-446b-bc7d-c07e86ba97fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683550735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2683550735
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2148680158
Short name T1590
Test name
Test status
Simulation time 6072575730 ps
CPU time 8.17 seconds
Started Aug 11 05:26:28 PM PDT 24
Finished Aug 11 05:26:36 PM PDT 24
Peak memory 212248 kb
Host smart-e998587d-2cf9-4c0e-883a-4f6547d1b402
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148680158 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2148680158
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2828773711
Short name T704
Test name
Test status
Simulation time 224347301 ps
CPU time 1.33 seconds
Started Aug 11 05:26:17 PM PDT 24
Finished Aug 11 05:26:19 PM PDT 24
Peak memory 205380 kb
Host smart-fa27285e-cfa1-4cc0-8b95-3a220add417d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828773711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2828773711
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3191958931
Short name T1338
Test name
Test status
Simulation time 1426964210 ps
CPU time 1.45 seconds
Started Aug 11 05:26:27 PM PDT 24
Finished Aug 11 05:26:28 PM PDT 24
Peak memory 208368 kb
Host smart-2f17b541-1e09-4699-bc4c-a94452c3bf10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191958931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3191958931
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.3766312918
Short name T877
Test name
Test status
Simulation time 488214207 ps
CPU time 2.58 seconds
Started Aug 11 05:26:26 PM PDT 24
Finished Aug 11 05:26:29 PM PDT 24
Peak memory 205528 kb
Host smart-0b3add22-c542-46f2-a3db-9a0de4a19807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766312918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.3766312918
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.1795528250
Short name T1254
Test name
Test status
Simulation time 118984315 ps
CPU time 1.18 seconds
Started Aug 11 05:26:24 PM PDT 24
Finished Aug 11 05:26:25 PM PDT 24
Peak memory 205444 kb
Host smart-7a0b8ae8-7eab-42a3-8e94-467c41c1de29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795528250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.1795528250
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.1000880801
Short name T1204
Test name
Test status
Simulation time 5532263480 ps
CPU time 6.4 seconds
Started Aug 11 05:26:20 PM PDT 24
Finished Aug 11 05:26:26 PM PDT 24
Peak memory 217092 kb
Host smart-4c8797b1-f34e-4ab0-bd91-c3a8f9fee3bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000880801 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.1000880801
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3447212887
Short name T377
Test name
Test status
Simulation time 12350052030 ps
CPU time 73.44 seconds
Started Aug 11 05:26:23 PM PDT 24
Finished Aug 11 05:27:36 PM PDT 24
Peak memory 1527000 kb
Host smart-48d23b4f-598c-410b-9c16-f59beebd4fd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447212887 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3447212887
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull.2980668918
Short name T775
Test name
Test status
Simulation time 2093234843 ps
CPU time 2.68 seconds
Started Aug 11 05:26:35 PM PDT 24
Finished Aug 11 05:26:38 PM PDT 24
Peak memory 213728 kb
Host smart-21c6055c-5bc3-469a-9a1a-b7ed276b1a67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980668918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_nack_acqfull.2980668918
Directory /workspace/5.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/5.i2c_target_nack_acqfull_addr.150990853
Short name T1255
Test name
Test status
Simulation time 543775830 ps
CPU time 2.77 seconds
Started Aug 11 05:26:31 PM PDT 24
Finished Aug 11 05:26:34 PM PDT 24
Peak memory 205556 kb
Host smart-57cfc078-847d-4cb4-8e0a-5a97d329ecea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150990853 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.150990853
Directory /workspace/5.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.744672705
Short name T1514
Test name
Test status
Simulation time 513590838 ps
CPU time 3.69 seconds
Started Aug 11 05:26:25 PM PDT 24
Finished Aug 11 05:26:29 PM PDT 24
Peak memory 213924 kb
Host smart-40af2d29-07df-4e22-94f6-0559e63b4ac4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744672705 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_perf.744672705
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smbus_maxlen.1818857537
Short name T1061
Test name
Test status
Simulation time 421279616 ps
CPU time 2.22 seconds
Started Aug 11 05:26:32 PM PDT 24
Finished Aug 11 05:26:34 PM PDT 24
Peak memory 205364 kb
Host smart-4a4a8e27-322a-42ab-990a-0e812a31a559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818857537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_smbus_maxlen.1818857537
Directory /workspace/5.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3376378386
Short name T1274
Test name
Test status
Simulation time 2330508358 ps
CPU time 16.85 seconds
Started Aug 11 05:26:17 PM PDT 24
Finished Aug 11 05:26:34 PM PDT 24
Peak memory 216332 kb
Host smart-316e229c-ccbf-4f90-825b-e627cf06ead6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376378386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3376378386
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3531207605
Short name T1561
Test name
Test status
Simulation time 1442244873 ps
CPU time 28.59 seconds
Started Aug 11 05:26:20 PM PDT 24
Finished Aug 11 05:26:49 PM PDT 24
Peak memory 230448 kb
Host smart-584d0063-261a-48d4-ad47-940c80a56e9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531207605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3531207605
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.3927152402
Short name T59
Test name
Test status
Simulation time 45763498226 ps
CPU time 346.8 seconds
Started Aug 11 05:26:20 PM PDT 24
Finished Aug 11 05:32:07 PM PDT 24
Peak memory 3372088 kb
Host smart-487b4a24-708a-460b-91e5-fa1a028e6b33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927152402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.3927152402
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.2777601300
Short name T964
Test name
Test status
Simulation time 1346141290 ps
CPU time 4.46 seconds
Started Aug 11 05:26:23 PM PDT 24
Finished Aug 11 05:26:27 PM PDT 24
Peak memory 214828 kb
Host smart-0053838c-33a4-4a2e-b7d3-0ece0c44f2f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777601300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.2777601300
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.467236625
Short name T1672
Test name
Test status
Simulation time 4783827746 ps
CPU time 6.7 seconds
Started Aug 11 05:26:20 PM PDT 24
Finished Aug 11 05:26:27 PM PDT 24
Peak memory 222120 kb
Host smart-2e3701da-e7fe-467b-9799-31b99aa90b57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467236625 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_timeout.467236625
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.1860232560
Short name T149
Test name
Test status
Simulation time 532864206 ps
CPU time 7.16 seconds
Started Aug 11 05:26:34 PM PDT 24
Finished Aug 11 05:26:41 PM PDT 24
Peak memory 205596 kb
Host smart-d1c45245-ddc8-4005-9c3a-0761565b8ce1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860232560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.1860232560
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1118469564
Short name T1557
Test name
Test status
Simulation time 18447334 ps
CPU time 0.64 seconds
Started Aug 11 05:26:38 PM PDT 24
Finished Aug 11 05:26:38 PM PDT 24
Peak memory 204808 kb
Host smart-ba01f3c6-4a97-4196-8f10-f763af229a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118469564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1118469564
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1816240304
Short name T1112
Test name
Test status
Simulation time 184374191 ps
CPU time 2.9 seconds
Started Aug 11 05:26:33 PM PDT 24
Finished Aug 11 05:26:36 PM PDT 24
Peak memory 213640 kb
Host smart-d5de0d8a-efcd-4eae-bf7c-7c13b57cb9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816240304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1816240304
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3007053145
Short name T308
Test name
Test status
Simulation time 1825631453 ps
CPU time 9.56 seconds
Started Aug 11 05:26:36 PM PDT 24
Finished Aug 11 05:26:46 PM PDT 24
Peak memory 300608 kb
Host smart-d39037e7-41b7-47fd-bf4f-efbe2b215097
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007053145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3007053145
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1829207719
Short name T650
Test name
Test status
Simulation time 5755430663 ps
CPU time 88.51 seconds
Started Aug 11 05:26:35 PM PDT 24
Finished Aug 11 05:28:04 PM PDT 24
Peak memory 616936 kb
Host smart-7ecef286-2885-41e2-8a61-2cc546aefbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829207719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1829207719
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1831496445
Short name T738
Test name
Test status
Simulation time 2849576155 ps
CPU time 84.98 seconds
Started Aug 11 05:26:34 PM PDT 24
Finished Aug 11 05:27:59 PM PDT 24
Peak memory 823064 kb
Host smart-f60dabb7-2f62-4c3d-b3bb-7cd3e0482fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831496445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1831496445
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.2292799466
Short name T238
Test name
Test status
Simulation time 1552707318 ps
CPU time 1.12 seconds
Started Aug 11 05:26:34 PM PDT 24
Finished Aug 11 05:26:35 PM PDT 24
Peak memory 205228 kb
Host smart-b0b10bea-318e-449b-844e-93965273c5e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292799466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.2292799466
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.2130879678
Short name T882
Test name
Test status
Simulation time 439727884 ps
CPU time 6.9 seconds
Started Aug 11 05:26:39 PM PDT 24
Finished Aug 11 05:26:46 PM PDT 24
Peak memory 224796 kb
Host smart-de379f0a-141d-4284-bbc8-a261950eefda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130879678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
2130879678
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.5267148
Short name T1661
Test name
Test status
Simulation time 5179984199 ps
CPU time 379.77 seconds
Started Aug 11 05:26:34 PM PDT 24
Finished Aug 11 05:32:54 PM PDT 24
Peak memory 1476212 kb
Host smart-5817f0c1-0c60-4819-9c2a-73b6a14a312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5267148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.5267148
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1502293205
Short name T799
Test name
Test status
Simulation time 2216253917 ps
CPU time 6.05 seconds
Started Aug 11 05:26:42 PM PDT 24
Finished Aug 11 05:26:48 PM PDT 24
Peak memory 205616 kb
Host smart-3e5115dc-2ff8-488a-bb63-e6aaa465a40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502293205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1502293205
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_override.2544276442
Short name T553
Test name
Test status
Simulation time 17428557 ps
CPU time 0.65 seconds
Started Aug 11 05:26:34 PM PDT 24
Finished Aug 11 05:26:35 PM PDT 24
Peak memory 204180 kb
Host smart-f9c26fc4-5fe1-44ea-94d3-d3816244a670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544276442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2544276442
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.2494989876
Short name T1660
Test name
Test status
Simulation time 12542887242 ps
CPU time 83.91 seconds
Started Aug 11 05:26:33 PM PDT 24
Finished Aug 11 05:27:57 PM PDT 24
Peak memory 624612 kb
Host smart-7f5e9619-1f38-494d-a5be-6065eb61f33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494989876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.2494989876
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.3502409920
Short name T117
Test name
Test status
Simulation time 159973511 ps
CPU time 3.17 seconds
Started Aug 11 05:26:35 PM PDT 24
Finished Aug 11 05:26:38 PM PDT 24
Peak memory 205424 kb
Host smart-44a0a533-1c4c-4d7b-8c45-45b4b4faee6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502409920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.3502409920
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.2038594970
Short name T289
Test name
Test status
Simulation time 7231902397 ps
CPU time 33.09 seconds
Started Aug 11 05:26:38 PM PDT 24
Finished Aug 11 05:27:11 PM PDT 24
Peak memory 330352 kb
Host smart-fad961aa-472b-403a-9921-d2f133efb43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038594970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.2038594970
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2193990444
Short name T1358
Test name
Test status
Simulation time 27735066023 ps
CPU time 427.87 seconds
Started Aug 11 05:26:32 PM PDT 24
Finished Aug 11 05:33:40 PM PDT 24
Peak memory 845148 kb
Host smart-d812f3d5-80e4-4c5e-825c-a81108fdbf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193990444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2193990444
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.460704707
Short name T379
Test name
Test status
Simulation time 1099326961 ps
CPU time 9.39 seconds
Started Aug 11 05:26:34 PM PDT 24
Finished Aug 11 05:26:44 PM PDT 24
Peak memory 213932 kb
Host smart-d3d18ced-9333-4db2-816e-b16e8609a9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460704707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.460704707
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.1174319608
Short name T947
Test name
Test status
Simulation time 2106421523 ps
CPU time 5.19 seconds
Started Aug 11 05:26:39 PM PDT 24
Finished Aug 11 05:26:44 PM PDT 24
Peak memory 213872 kb
Host smart-11bd42f4-515c-41d3-99c9-840dba64bcec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174319608 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.1174319608
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.64148923
Short name T709
Test name
Test status
Simulation time 223571130 ps
CPU time 1.61 seconds
Started Aug 11 05:26:38 PM PDT 24
Finished Aug 11 05:26:40 PM PDT 24
Peak memory 205720 kb
Host smart-dbf79b89-abf2-4c50-a319-36941b7c1abe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64148923 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_acq.64148923
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.2867154142
Short name T910
Test name
Test status
Simulation time 442018861 ps
CPU time 1.17 seconds
Started Aug 11 05:26:32 PM PDT 24
Finished Aug 11 05:26:34 PM PDT 24
Peak memory 205456 kb
Host smart-d02f871b-66d2-4e88-87bd-eb172a18cbc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867154142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.2867154142
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.2420356658
Short name T361
Test name
Test status
Simulation time 5585341372 ps
CPU time 2.41 seconds
Started Aug 11 05:26:40 PM PDT 24
Finished Aug 11 05:26:43 PM PDT 24
Peak memory 205632 kb
Host smart-81f8f834-cd8a-4c32-9afe-90147343e2d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420356658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.2420356658
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.4080169021
Short name T1141
Test name
Test status
Simulation time 157448195 ps
CPU time 1.05 seconds
Started Aug 11 05:26:40 PM PDT 24
Finished Aug 11 05:26:41 PM PDT 24
Peak memory 205344 kb
Host smart-b674cea2-9de8-48e7-8708-d76b86d1f66f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080169021 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.4080169021
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.1164164082
Short name T1129
Test name
Test status
Simulation time 3692290449 ps
CPU time 6.1 seconds
Started Aug 11 05:26:33 PM PDT 24
Finished Aug 11 05:26:39 PM PDT 24
Peak memory 220948 kb
Host smart-53f18ce9-03b6-4d55-a428-7633b8295e67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164164082 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.1164164082
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull.2244351321
Short name T1740
Test name
Test status
Simulation time 1737906061 ps
CPU time 2.4 seconds
Started Aug 11 05:26:39 PM PDT 24
Finished Aug 11 05:26:42 PM PDT 24
Peak memory 213852 kb
Host smart-ac0e9947-d800-43fc-b16c-b6e7697957c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244351321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_nack_acqfull.2244351321
Directory /workspace/6.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/6.i2c_target_nack_acqfull_addr.783811863
Short name T394
Test name
Test status
Simulation time 1741025535 ps
CPU time 2.84 seconds
Started Aug 11 05:26:40 PM PDT 24
Finished Aug 11 05:26:43 PM PDT 24
Peak memory 205656 kb
Host smart-87b5196a-045c-46ac-a899-da9690840eeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783811863 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.783811863
Directory /workspace/6.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/6.i2c_target_nack_txstretch.1293607234
Short name T1227
Test name
Test status
Simulation time 602696915 ps
CPU time 1.5 seconds
Started Aug 11 05:26:39 PM PDT 24
Finished Aug 11 05:26:40 PM PDT 24
Peak memory 222008 kb
Host smart-3795e14b-ee7f-4213-a4ac-acffcc78389b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293607234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_nack_txstretch.1293607234
Directory /workspace/6.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/6.i2c_target_perf.1345972919
Short name T671
Test name
Test status
Simulation time 554222898 ps
CPU time 3.88 seconds
Started Aug 11 05:26:39 PM PDT 24
Finished Aug 11 05:26:43 PM PDT 24
Peak memory 221004 kb
Host smart-2567b705-3510-4477-8a0a-c081005a13dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345972919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.1345972919
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smbus_maxlen.4014434857
Short name T429
Test name
Test status
Simulation time 422183270 ps
CPU time 2.27 seconds
Started Aug 11 05:26:41 PM PDT 24
Finished Aug 11 05:26:44 PM PDT 24
Peak memory 205316 kb
Host smart-5645361e-fca6-4a5c-8d65-71f7335adc0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014434857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_smbus_maxlen.4014434857
Directory /workspace/6.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2304020198
Short name T1310
Test name
Test status
Simulation time 2562750596 ps
CPU time 19.68 seconds
Started Aug 11 05:26:38 PM PDT 24
Finished Aug 11 05:26:58 PM PDT 24
Peak memory 213984 kb
Host smart-283e0770-140e-45e8-85bb-c674359c316e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304020198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2304020198
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.2279691095
Short name T1261
Test name
Test status
Simulation time 24056032481 ps
CPU time 95.9 seconds
Started Aug 11 05:26:42 PM PDT 24
Finished Aug 11 05:28:18 PM PDT 24
Peak memory 652244 kb
Host smart-5a455472-fd85-4c77-9de9-33679b3a496d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279691095 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_stress_all.2279691095
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.3120186539
Short name T387
Test name
Test status
Simulation time 11727729792 ps
CPU time 21.67 seconds
Started Aug 11 05:26:36 PM PDT 24
Finished Aug 11 05:26:58 PM PDT 24
Peak memory 224264 kb
Host smart-0157842e-440d-4814-b9d9-d720c84ad80d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120186539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.3120186539
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.564191599
Short name T132
Test name
Test status
Simulation time 36467585408 ps
CPU time 62.73 seconds
Started Aug 11 05:26:30 PM PDT 24
Finished Aug 11 05:27:33 PM PDT 24
Peak memory 1054832 kb
Host smart-2b8a8242-f35a-4999-8a98-8b80cf6b5a92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564191599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_wr.564191599
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2297381080
Short name T1349
Test name
Test status
Simulation time 3475763426 ps
CPU time 177.9 seconds
Started Aug 11 05:26:35 PM PDT 24
Finished Aug 11 05:29:33 PM PDT 24
Peak memory 975392 kb
Host smart-a30f6664-1ec6-49c8-8e5e-385721d61cb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297381080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2297381080
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2106342660
Short name T1658
Test name
Test status
Simulation time 1232755817 ps
CPU time 6.47 seconds
Started Aug 11 05:26:32 PM PDT 24
Finished Aug 11 05:26:39 PM PDT 24
Peak memory 221976 kb
Host smart-29590077-0d28-4c60-b659-a07dd259e1e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106342660 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2106342660
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.2192044290
Short name T1714
Test name
Test status
Simulation time 226578776 ps
CPU time 3.22 seconds
Started Aug 11 05:26:41 PM PDT 24
Finished Aug 11 05:26:44 PM PDT 24
Peak memory 204584 kb
Host smart-512f3d0e-980c-4527-b442-1961074745ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192044290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.2192044290
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.934543928
Short name T1398
Test name
Test status
Simulation time 26504270 ps
CPU time 0.63 seconds
Started Aug 11 05:26:56 PM PDT 24
Finished Aug 11 05:26:57 PM PDT 24
Peak memory 204756 kb
Host smart-ea6d74e4-9344-416f-af29-1876128600e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934543928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.934543928
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.247508760
Short name T1477
Test name
Test status
Simulation time 187930252 ps
CPU time 1.38 seconds
Started Aug 11 05:26:38 PM PDT 24
Finished Aug 11 05:26:40 PM PDT 24
Peak memory 213800 kb
Host smart-97ac5cbe-ceb6-483f-875d-a1bf3903f1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247508760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.247508760
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.1299402925
Short name T1578
Test name
Test status
Simulation time 650261151 ps
CPU time 3.29 seconds
Started Aug 11 05:26:39 PM PDT 24
Finished Aug 11 05:26:43 PM PDT 24
Peak memory 235264 kb
Host smart-54de0536-3eed-4787-bf21-1605714d2df5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299402925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.1299402925
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.761938989
Short name T740
Test name
Test status
Simulation time 13853482746 ps
CPU time 119.23 seconds
Started Aug 11 05:26:42 PM PDT 24
Finished Aug 11 05:28:41 PM PDT 24
Peak memory 532592 kb
Host smart-0778abfc-171d-4de4-93b5-0505658209ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761938989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.761938989
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.4181010884
Short name T1731
Test name
Test status
Simulation time 1830718716 ps
CPU time 54.75 seconds
Started Aug 11 05:26:39 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 641520 kb
Host smart-c77dbf61-4963-4753-b7ca-c27c14284b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181010884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.4181010884
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1068716563
Short name T1115
Test name
Test status
Simulation time 327431875 ps
CPU time 1.12 seconds
Started Aug 11 05:26:40 PM PDT 24
Finished Aug 11 05:26:41 PM PDT 24
Peak memory 205384 kb
Host smart-1b217ed7-a049-4021-b069-1360607000c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068716563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1068716563
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.175646825
Short name T236
Test name
Test status
Simulation time 354706017 ps
CPU time 9.88 seconds
Started Aug 11 05:26:39 PM PDT 24
Finished Aug 11 05:26:49 PM PDT 24
Peak memory 237744 kb
Host smart-e025f63d-aa50-4edf-b920-ffc05c14ad23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175646825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.175646825
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.1967328239
Short name T958
Test name
Test status
Simulation time 4272782524 ps
CPU time 216.36 seconds
Started Aug 11 05:26:43 PM PDT 24
Finished Aug 11 05:30:19 PM PDT 24
Peak memory 1016436 kb
Host smart-f3c9c1f0-092f-46f8-a55b-f1a57828170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967328239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.1967328239
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3898694480
Short name T252
Test name
Test status
Simulation time 1136030772 ps
CPU time 21.78 seconds
Started Aug 11 05:26:48 PM PDT 24
Finished Aug 11 05:27:10 PM PDT 24
Peak memory 205436 kb
Host smart-ed350c46-648a-4451-a695-5dcbe8a0b59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898694480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3898694480
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_override.4264739326
Short name T138
Test name
Test status
Simulation time 49831081 ps
CPU time 0.63 seconds
Started Aug 11 05:26:39 PM PDT 24
Finished Aug 11 05:26:40 PM PDT 24
Peak memory 205228 kb
Host smart-2bd0fbb4-5915-41e9-b071-3ec5373cc335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264739326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.4264739326
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.3168078745
Short name T1136
Test name
Test status
Simulation time 569809471 ps
CPU time 6.34 seconds
Started Aug 11 05:26:39 PM PDT 24
Finished Aug 11 05:26:45 PM PDT 24
Peak memory 234664 kb
Host smart-5ab34357-0db5-417b-9c93-3826a32c1bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168078745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.3168078745
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.1652061390
Short name T897
Test name
Test status
Simulation time 3484301166 ps
CPU time 24.6 seconds
Started Aug 11 05:26:40 PM PDT 24
Finished Aug 11 05:27:04 PM PDT 24
Peak memory 299944 kb
Host smart-abed03f6-1289-4084-a494-5c416989c06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652061390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1652061390
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2257556309
Short name T1516
Test name
Test status
Simulation time 640496467 ps
CPU time 24 seconds
Started Aug 11 05:26:41 PM PDT 24
Finished Aug 11 05:27:05 PM PDT 24
Peak memory 213776 kb
Host smart-33f2f7fc-3ee2-43a3-83f4-fb09cdf78e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257556309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2257556309
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3009428757
Short name T809
Test name
Test status
Simulation time 4372215176 ps
CPU time 4.16 seconds
Started Aug 11 05:26:49 PM PDT 24
Finished Aug 11 05:26:53 PM PDT 24
Peak memory 213924 kb
Host smart-73da390f-b97b-48db-8cf9-2e437472374f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009428757 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3009428757
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2266983176
Short name T296
Test name
Test status
Simulation time 493785113 ps
CPU time 1.22 seconds
Started Aug 11 05:26:50 PM PDT 24
Finished Aug 11 05:26:51 PM PDT 24
Peak memory 205668 kb
Host smart-7b59a5b1-b9b6-49c8-ba5d-5b86f784903f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266983176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2266983176
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1950069429
Short name T968
Test name
Test status
Simulation time 162185917 ps
CPU time 0.93 seconds
Started Aug 11 05:26:46 PM PDT 24
Finished Aug 11 05:26:47 PM PDT 24
Peak memory 205456 kb
Host smart-e9421c27-b4ad-4291-a225-bc528fa11738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950069429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1950069429
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.2884952090
Short name T1283
Test name
Test status
Simulation time 2608564188 ps
CPU time 2.85 seconds
Started Aug 11 05:26:52 PM PDT 24
Finished Aug 11 05:26:55 PM PDT 24
Peak memory 205680 kb
Host smart-9257dd4a-1ff6-4cd6-9ead-faf973569660
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884952090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.2884952090
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.3821075777
Short name T1598
Test name
Test status
Simulation time 214412059 ps
CPU time 1.08 seconds
Started Aug 11 05:26:56 PM PDT 24
Finished Aug 11 05:26:57 PM PDT 24
Peak memory 205672 kb
Host smart-938ae9cb-765b-4854-aa11-dfd907ec14ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821075777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.3821075777
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1033137482
Short name T674
Test name
Test status
Simulation time 10825400987 ps
CPU time 7.37 seconds
Started Aug 11 05:26:49 PM PDT 24
Finished Aug 11 05:26:57 PM PDT 24
Peak memory 213968 kb
Host smart-e71c0fd3-64ce-43b4-aebe-34bb50d13e95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033137482 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1033137482
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.421953165
Short name T892
Test name
Test status
Simulation time 17914704467 ps
CPU time 46.78 seconds
Started Aug 11 05:26:47 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 1079332 kb
Host smart-a592cf6f-0957-45ca-a96a-fc43f2950da1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421953165 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.421953165
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull.1124846217
Short name T1290
Test name
Test status
Simulation time 479805605 ps
CPU time 2.44 seconds
Started Aug 11 05:26:54 PM PDT 24
Finished Aug 11 05:26:56 PM PDT 24
Peak memory 213836 kb
Host smart-75997832-24e7-432a-8186-a92dcd40fa10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124846217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_nack_acqfull.1124846217
Directory /workspace/7.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/7.i2c_target_nack_acqfull_addr.3356312038
Short name T902
Test name
Test status
Simulation time 1826053296 ps
CPU time 2.51 seconds
Started Aug 11 05:26:56 PM PDT 24
Finished Aug 11 05:26:59 PM PDT 24
Peak memory 205608 kb
Host smart-fe1016b2-9f6f-4af7-a74b-8b21feb8ae8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356312038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.3356312038
Directory /workspace/7.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.4089580821
Short name T533
Test name
Test status
Simulation time 4853307982 ps
CPU time 2.83 seconds
Started Aug 11 05:26:49 PM PDT 24
Finished Aug 11 05:26:52 PM PDT 24
Peak memory 222096 kb
Host smart-5952cba7-5bec-4f8f-a6f3-5308924139b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089580821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_perf.4089580821
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smbus_maxlen.1800448735
Short name T1717
Test name
Test status
Simulation time 8303931015 ps
CPU time 2.21 seconds
Started Aug 11 05:26:54 PM PDT 24
Finished Aug 11 05:26:56 PM PDT 24
Peak memory 205516 kb
Host smart-e3f70161-5b1c-41f6-9dd1-037b1b37e444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800448735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_smbus_maxlen.1800448735
Directory /workspace/7.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.1093896764
Short name T820
Test name
Test status
Simulation time 816076099 ps
CPU time 10.37 seconds
Started Aug 11 05:26:42 PM PDT 24
Finished Aug 11 05:26:53 PM PDT 24
Peak memory 213856 kb
Host smart-3655f319-1101-4e18-9829-f954c44c91e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093896764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.1093896764
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.3363037583
Short name T1266
Test name
Test status
Simulation time 22511727214 ps
CPU time 467.51 seconds
Started Aug 11 05:26:48 PM PDT 24
Finished Aug 11 05:34:36 PM PDT 24
Peak memory 2497096 kb
Host smart-9e09102a-d923-44c3-accc-d5ca3a333bce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363037583 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.3363037583
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2574337914
Short name T965
Test name
Test status
Simulation time 1367272910 ps
CPU time 6.99 seconds
Started Aug 11 05:26:50 PM PDT 24
Finished Aug 11 05:26:57 PM PDT 24
Peak memory 205656 kb
Host smart-bc8f901b-36be-4add-a2dd-abb1e0744b08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574337914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2574337914
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.584029521
Short name T1267
Test name
Test status
Simulation time 34111066655 ps
CPU time 340.09 seconds
Started Aug 11 05:26:47 PM PDT 24
Finished Aug 11 05:32:27 PM PDT 24
Peak memory 3577704 kb
Host smart-dcb133c7-032d-4824-9dbb-50a991852f2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584029521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.584029521
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3578950336
Short name T1657
Test name
Test status
Simulation time 4379191769 ps
CPU time 12.67 seconds
Started Aug 11 05:26:49 PM PDT 24
Finished Aug 11 05:27:02 PM PDT 24
Peak memory 415316 kb
Host smart-3813e331-8885-4c76-b869-5779e35f7b59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578950336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3578950336
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1826349979
Short name T476
Test name
Test status
Simulation time 13272023218 ps
CPU time 7.17 seconds
Started Aug 11 05:26:48 PM PDT 24
Finished Aug 11 05:26:55 PM PDT 24
Peak memory 214372 kb
Host smart-10014d09-ca88-4ad3-84ce-2bce538176b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826349979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1826349979
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.2078181579
Short name T787
Test name
Test status
Simulation time 476881479 ps
CPU time 6.83 seconds
Started Aug 11 05:26:56 PM PDT 24
Finished Aug 11 05:27:03 PM PDT 24
Peak memory 205632 kb
Host smart-3ba9aed9-eff6-4b99-ae39-7a264a8b73db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078181579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.2078181579
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.897585206
Short name T179
Test name
Test status
Simulation time 18883720 ps
CPU time 0.64 seconds
Started Aug 11 05:27:11 PM PDT 24
Finished Aug 11 05:27:11 PM PDT 24
Peak memory 204760 kb
Host smart-1bfe9306-2199-4461-9366-91e212cba62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897585206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.897585206
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3887321210
Short name T26
Test name
Test status
Simulation time 1032731221 ps
CPU time 4.37 seconds
Started Aug 11 05:26:54 PM PDT 24
Finished Aug 11 05:26:58 PM PDT 24
Peak memory 230028 kb
Host smart-5e2fbf17-ada1-4050-bacb-345c177aa4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887321210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3887321210
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1431352687
Short name T701
Test name
Test status
Simulation time 336408566 ps
CPU time 16.28 seconds
Started Aug 11 05:26:55 PM PDT 24
Finished Aug 11 05:27:11 PM PDT 24
Peak memory 271984 kb
Host smart-c7d7b712-dc33-49b7-b900-91bf1231306d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431352687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1431352687
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2941317937
Short name T869
Test name
Test status
Simulation time 10542579394 ps
CPU time 53.59 seconds
Started Aug 11 05:26:54 PM PDT 24
Finished Aug 11 05:27:48 PM PDT 24
Peak memory 378784 kb
Host smart-07f5a8d9-31ca-4cc4-a5ee-00f62a0e5a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941317937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2941317937
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.3413091091
Short name T1032
Test name
Test status
Simulation time 2179770244 ps
CPU time 165.08 seconds
Started Aug 11 05:26:56 PM PDT 24
Finished Aug 11 05:29:41 PM PDT 24
Peak memory 743868 kb
Host smart-97c65d29-e493-46fc-8c67-fec6043cafa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413091091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3413091091
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.524204174
Short name T792
Test name
Test status
Simulation time 530749542 ps
CPU time 1.26 seconds
Started Aug 11 05:26:53 PM PDT 24
Finished Aug 11 05:26:55 PM PDT 24
Peak memory 205392 kb
Host smart-a25331aa-9e77-411b-a3ac-3173cea9918f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524204174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt
.524204174
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2250161542
Short name T1157
Test name
Test status
Simulation time 146419357 ps
CPU time 3.64 seconds
Started Aug 11 05:26:56 PM PDT 24
Finished Aug 11 05:27:00 PM PDT 24
Peak memory 205500 kb
Host smart-181dc7b2-f406-47ea-8960-cf82b89f1a1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250161542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2250161542
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3286044342
Short name T1277
Test name
Test status
Simulation time 8437708216 ps
CPU time 288.33 seconds
Started Aug 11 05:26:55 PM PDT 24
Finished Aug 11 05:31:43 PM PDT 24
Peak memory 1142292 kb
Host smart-b15ec20a-271a-4c9f-a241-60111ceabb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286044342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3286044342
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.3632515042
Short name T1503
Test name
Test status
Simulation time 1438420602 ps
CPU time 5.85 seconds
Started Aug 11 05:27:04 PM PDT 24
Finished Aug 11 05:27:10 PM PDT 24
Peak memory 205556 kb
Host smart-f28c7d79-c4b6-4877-94c0-4a9b1ae0c58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632515042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.3632515042
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_override.2282880216
Short name T537
Test name
Test status
Simulation time 143341341 ps
CPU time 0.65 seconds
Started Aug 11 05:26:56 PM PDT 24
Finished Aug 11 05:26:57 PM PDT 24
Peak memory 205208 kb
Host smart-8bd78f89-ebc6-4afa-a329-56412738d242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282880216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2282880216
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1444175057
Short name T1379
Test name
Test status
Simulation time 5016085726 ps
CPU time 57.8 seconds
Started Aug 11 05:26:55 PM PDT 24
Finished Aug 11 05:27:53 PM PDT 24
Peak memory 514596 kb
Host smart-8b4dc6f1-bbc0-4b3b-86a2-110dfe62ec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444175057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1444175057
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.2033276264
Short name T1725
Test name
Test status
Simulation time 689824947 ps
CPU time 7.18 seconds
Started Aug 11 05:26:53 PM PDT 24
Finished Aug 11 05:27:00 PM PDT 24
Peak memory 205380 kb
Host smart-e4eb59fa-9305-4395-9b13-822de5e38051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033276264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.2033276264
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1294300885
Short name T603
Test name
Test status
Simulation time 1315464896 ps
CPU time 61.73 seconds
Started Aug 11 05:26:52 PM PDT 24
Finished Aug 11 05:27:53 PM PDT 24
Peak memory 334928 kb
Host smart-1decddb9-d125-465c-b827-373844751fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294300885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1294300885
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.3188108374
Short name T177
Test name
Test status
Simulation time 6930150937 ps
CPU time 245.98 seconds
Started Aug 11 05:26:55 PM PDT 24
Finished Aug 11 05:31:01 PM PDT 24
Peak memory 1373936 kb
Host smart-783e49ac-18f4-4842-8dfa-e0acaff717d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188108374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.3188108374
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.1347513998
Short name T778
Test name
Test status
Simulation time 5124122975 ps
CPU time 18.02 seconds
Started Aug 11 05:26:57 PM PDT 24
Finished Aug 11 05:27:15 PM PDT 24
Peak memory 220376 kb
Host smart-3f17ab12-051f-4d72-a55b-7f0b18c307b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347513998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1347513998
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1130165267
Short name T1142
Test name
Test status
Simulation time 2871627209 ps
CPU time 3.67 seconds
Started Aug 11 05:27:01 PM PDT 24
Finished Aug 11 05:27:05 PM PDT 24
Peak memory 216892 kb
Host smart-060923c8-9f99-4ec6-953d-238391b65d63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130165267 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1130165267
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3758925519
Short name T527
Test name
Test status
Simulation time 307361243 ps
CPU time 1.24 seconds
Started Aug 11 05:26:52 PM PDT 24
Finished Aug 11 05:26:54 PM PDT 24
Peak memory 205568 kb
Host smart-2b315021-44b1-47a4-9472-e15f987396f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758925519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3758925519
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.4013197040
Short name T466
Test name
Test status
Simulation time 143325850 ps
CPU time 0.83 seconds
Started Aug 11 05:27:02 PM PDT 24
Finished Aug 11 05:27:03 PM PDT 24
Peak memory 213596 kb
Host smart-75264ef1-01b8-433d-ada1-1f2ffb2ada99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013197040 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.4013197040
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.4158038684
Short name T388
Test name
Test status
Simulation time 187394735 ps
CPU time 1.45 seconds
Started Aug 11 05:27:01 PM PDT 24
Finished Aug 11 05:27:02 PM PDT 24
Peak memory 205380 kb
Host smart-bbeea50f-8124-413e-b305-0d468f5d77d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158038684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.4158038684
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.3946320049
Short name T962
Test name
Test status
Simulation time 568469693 ps
CPU time 1.49 seconds
Started Aug 11 05:27:01 PM PDT 24
Finished Aug 11 05:27:03 PM PDT 24
Peak memory 205436 kb
Host smart-9dfa98b8-a4a3-4798-9578-f6541d7dafbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946320049 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.3946320049
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3568037674
Short name T725
Test name
Test status
Simulation time 733709013 ps
CPU time 4.7 seconds
Started Aug 11 05:26:56 PM PDT 24
Finished Aug 11 05:27:01 PM PDT 24
Peak memory 216188 kb
Host smart-2f536a91-57e3-4d46-88f0-1f5ad25ccd59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568037674 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3568037674
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.3121274015
Short name T1173
Test name
Test status
Simulation time 13183707293 ps
CPU time 14.39 seconds
Started Aug 11 05:26:52 PM PDT 24
Finished Aug 11 05:27:07 PM PDT 24
Peak memory 413272 kb
Host smart-1fadad01-3c98-4463-8f21-327f1119b103
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121274015 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.3121274015
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull.1386493718
Short name T510
Test name
Test status
Simulation time 1636538546 ps
CPU time 2.53 seconds
Started Aug 11 05:27:06 PM PDT 24
Finished Aug 11 05:27:09 PM PDT 24
Peak memory 213816 kb
Host smart-50212673-15a4-42ae-a7e4-cdaaac074fcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386493718 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_nack_acqfull.1386493718
Directory /workspace/8.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/8.i2c_target_nack_acqfull_addr.274917376
Short name T1369
Test name
Test status
Simulation time 484734572 ps
CPU time 2.64 seconds
Started Aug 11 05:27:07 PM PDT 24
Finished Aug 11 05:27:10 PM PDT 24
Peak memory 205544 kb
Host smart-ed22ce83-0d58-4eb6-b87e-74003ab69d31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274917376 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.274917376
Directory /workspace/8.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/8.i2c_target_nack_txstretch.281677501
Short name T1576
Test name
Test status
Simulation time 809466064 ps
CPU time 1.41 seconds
Started Aug 11 05:27:07 PM PDT 24
Finished Aug 11 05:27:08 PM PDT 24
Peak memory 222312 kb
Host smart-2b89327b-eac9-47f2-9435-43e9cadae8a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281677501 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_nack_txstretch.281677501
Directory /workspace/8.i2c_target_nack_txstretch/latest

Test location /workspace/coverage/default/8.i2c_target_perf.3132119488
Short name T411
Test name
Test status
Simulation time 2681888043 ps
CPU time 5.08 seconds
Started Aug 11 05:26:59 PM PDT 24
Finished Aug 11 05:27:04 PM PDT 24
Peak memory 219492 kb
Host smart-f24a8cda-4be2-453c-b64c-d151a065e1df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132119488 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.3132119488
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smbus_maxlen.2589163961
Short name T188
Test name
Test status
Simulation time 1131519510 ps
CPU time 2.13 seconds
Started Aug 11 05:27:09 PM PDT 24
Finished Aug 11 05:27:11 PM PDT 24
Peak memory 205412 kb
Host smart-925be11f-2a81-4aaa-9f89-19624bc07716
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589163961 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_smbus_maxlen.2589163961
Directory /workspace/8.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.4112653751
Short name T1422
Test name
Test status
Simulation time 538005454 ps
CPU time 16.72 seconds
Started Aug 11 05:26:56 PM PDT 24
Finished Aug 11 05:27:13 PM PDT 24
Peak memory 214128 kb
Host smart-57da417a-9215-48e3-9966-0b9b4eae6051
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112653751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.4112653751
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.1355564912
Short name T1293
Test name
Test status
Simulation time 96562292402 ps
CPU time 565.02 seconds
Started Aug 11 05:27:02 PM PDT 24
Finished Aug 11 05:36:27 PM PDT 24
Peak memory 2798300 kb
Host smart-daab8cb2-1f46-4586-924a-3ba809203bb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355564912 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.1355564912
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.952648145
Short name T1108
Test name
Test status
Simulation time 2832057422 ps
CPU time 22.33 seconds
Started Aug 11 05:26:53 PM PDT 24
Finished Aug 11 05:27:15 PM PDT 24
Peak memory 213948 kb
Host smart-46b9bf7a-da19-4c03-98b5-8f4e2d578213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952648145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.952648145
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.733057373
Short name T1327
Test name
Test status
Simulation time 26739992433 ps
CPU time 139.32 seconds
Started Aug 11 05:26:54 PM PDT 24
Finished Aug 11 05:29:14 PM PDT 24
Peak memory 1940580 kb
Host smart-09ad90b0-f172-48c9-a87b-5b5f1e33f2f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733057373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.733057373
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3142099894
Short name T392
Test name
Test status
Simulation time 4465795336 ps
CPU time 8.04 seconds
Started Aug 11 05:26:55 PM PDT 24
Finished Aug 11 05:27:03 PM PDT 24
Peak memory 275312 kb
Host smart-cad3c1fd-56bd-4b60-973f-eaccd3d7cffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142099894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3142099894
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3961572394
Short name T136
Test name
Test status
Simulation time 3650437898 ps
CPU time 7.99 seconds
Started Aug 11 05:26:54 PM PDT 24
Finished Aug 11 05:27:02 PM PDT 24
Peak memory 213872 kb
Host smart-b06ae20f-74d2-4cf8-8161-071190af7aa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961572394 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3961572394
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.890205191
Short name T827
Test name
Test status
Simulation time 105845877 ps
CPU time 2.25 seconds
Started Aug 11 05:27:01 PM PDT 24
Finished Aug 11 05:27:03 PM PDT 24
Peak memory 205640 kb
Host smart-338dc9d2-cfb4-4181-91f8-6a1d2cbb1175
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890205191 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.890205191
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.414822337
Short name T178
Test name
Test status
Simulation time 57023178 ps
CPU time 0.6 seconds
Started Aug 11 05:27:22 PM PDT 24
Finished Aug 11 05:27:23 PM PDT 24
Peak memory 205260 kb
Host smart-bc2c1211-a5ea-49a7-b395-8a1b3d8a880f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414822337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.414822337
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3055605883
Short name T18
Test name
Test status
Simulation time 438741632 ps
CPU time 1.73 seconds
Started Aug 11 05:27:14 PM PDT 24
Finished Aug 11 05:27:16 PM PDT 24
Peak memory 213772 kb
Host smart-a4f29015-048b-4a6e-a2b5-c53c44d17651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055605883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3055605883
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3516697430
Short name T1475
Test name
Test status
Simulation time 372141033 ps
CPU time 18.55 seconds
Started Aug 11 05:27:08 PM PDT 24
Finished Aug 11 05:27:27 PM PDT 24
Peak memory 280104 kb
Host smart-dd1c0b03-c090-44cb-aa9b-2d91ebf070f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516697430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3516697430
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.376883729
Short name T191
Test name
Test status
Simulation time 7091795350 ps
CPU time 101.44 seconds
Started Aug 11 05:27:07 PM PDT 24
Finished Aug 11 05:28:48 PM PDT 24
Peak memory 587120 kb
Host smart-4ae8c9b0-ef55-4257-9646-0faa6513e9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376883729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.376883729
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.473883114
Short name T517
Test name
Test status
Simulation time 25247077363 ps
CPU time 71.32 seconds
Started Aug 11 05:27:11 PM PDT 24
Finished Aug 11 05:28:23 PM PDT 24
Peak memory 707312 kb
Host smart-bd63fa41-7e14-40bc-a2cf-a800608673da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473883114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.473883114
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.531906035
Short name T1566
Test name
Test status
Simulation time 87058571 ps
CPU time 0.91 seconds
Started Aug 11 05:27:10 PM PDT 24
Finished Aug 11 05:27:11 PM PDT 24
Peak memory 205204 kb
Host smart-cb7fae70-33e1-4d47-8407-91feca871ecc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531906035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.531906035
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2229045951
Short name T970
Test name
Test status
Simulation time 198149674 ps
CPU time 10.09 seconds
Started Aug 11 05:27:10 PM PDT 24
Finished Aug 11 05:27:21 PM PDT 24
Peak memory 242784 kb
Host smart-a43905ab-1be0-49bd-bd8f-f75807e61180
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229045951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2229045951
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3243492941
Short name T169
Test name
Test status
Simulation time 9198218686 ps
CPU time 297.34 seconds
Started Aug 11 05:27:08 PM PDT 24
Finished Aug 11 05:32:05 PM PDT 24
Peak memory 1246280 kb
Host smart-85bd8da4-19ef-43aa-93a1-2262b24454e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243492941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3243492941
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.1081669945
Short name T478
Test name
Test status
Simulation time 919923346 ps
CPU time 11.86 seconds
Started Aug 11 05:27:22 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 205464 kb
Host smart-7d8e581c-9fa6-41a1-b8a5-b9027d8c2130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081669945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1081669945
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_override.2248521904
Short name T707
Test name
Test status
Simulation time 23058908 ps
CPU time 0.67 seconds
Started Aug 11 05:27:10 PM PDT 24
Finished Aug 11 05:27:11 PM PDT 24
Peak memory 205168 kb
Host smart-0e4a3a55-0cd6-4270-92de-8983c1b30e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248521904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2248521904
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1918681007
Short name T34
Test name
Test status
Simulation time 482337593 ps
CPU time 19.35 seconds
Started Aug 11 05:27:16 PM PDT 24
Finished Aug 11 05:27:35 PM PDT 24
Peak memory 217272 kb
Host smart-153769ec-d7fa-4816-9cc3-d1dd0bf9be77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918681007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1918681007
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.726249853
Short name T644
Test name
Test status
Simulation time 758679196 ps
CPU time 35.32 seconds
Started Aug 11 05:27:15 PM PDT 24
Finished Aug 11 05:27:50 PM PDT 24
Peak memory 275040 kb
Host smart-9e4d7599-fcde-47b3-88bf-4f02b39db1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726249853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.726249853
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.1205898036
Short name T1718
Test name
Test status
Simulation time 5664020433 ps
CPU time 68.61 seconds
Started Aug 11 05:27:09 PM PDT 24
Finished Aug 11 05:28:18 PM PDT 24
Peak memory 335460 kb
Host smart-d1ebdf68-c5bc-42eb-99bf-7063b33c4fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205898036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.1205898036
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2711291155
Short name T1111
Test name
Test status
Simulation time 575579625 ps
CPU time 10 seconds
Started Aug 11 05:27:13 PM PDT 24
Finished Aug 11 05:27:23 PM PDT 24
Peak memory 213696 kb
Host smart-4806b04d-aa86-4f48-8894-50609b30227e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711291155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2711291155
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.544635973
Short name T1742
Test name
Test status
Simulation time 4937611599 ps
CPU time 5.33 seconds
Started Aug 11 05:27:13 PM PDT 24
Finished Aug 11 05:27:19 PM PDT 24
Peak memory 214024 kb
Host smart-fc47899d-c39f-4aa2-b2e5-d13d3af70a09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544635973 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.544635973
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2959200189
Short name T1322
Test name
Test status
Simulation time 1175511197 ps
CPU time 1.29 seconds
Started Aug 11 05:27:15 PM PDT 24
Finished Aug 11 05:27:16 PM PDT 24
Peak memory 212900 kb
Host smart-4ac01f5f-8a4f-4575-869c-04afdd8b1bac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959200189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2959200189
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1338422248
Short name T1436
Test name
Test status
Simulation time 220278417 ps
CPU time 1.38 seconds
Started Aug 11 05:27:12 PM PDT 24
Finished Aug 11 05:27:14 PM PDT 24
Peak memory 205604 kb
Host smart-b847581f-9f23-483a-af41-a08e30924b9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338422248 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1338422248
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.295492462
Short name T1635
Test name
Test status
Simulation time 1737583085 ps
CPU time 2.56 seconds
Started Aug 11 05:27:23 PM PDT 24
Finished Aug 11 05:27:26 PM PDT 24
Peak memory 205560 kb
Host smart-39a68078-7a2c-43ec-8b7c-01a517b47b69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295492462 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.295492462
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.2985659170
Short name T1732
Test name
Test status
Simulation time 805614716 ps
CPU time 0.83 seconds
Started Aug 11 05:27:22 PM PDT 24
Finished Aug 11 05:27:23 PM PDT 24
Peak memory 205396 kb
Host smart-cccd83bf-5edd-4a37-aa7d-46df5f421893
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985659170 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.2985659170
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.809933955
Short name T624
Test name
Test status
Simulation time 550276313 ps
CPU time 3.48 seconds
Started Aug 11 05:27:14 PM PDT 24
Finished Aug 11 05:27:18 PM PDT 24
Peak memory 213728 kb
Host smart-bb3643a9-d8ed-4f9c-a4be-50457519ab01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809933955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.809933955
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.1809705040
Short name T626
Test name
Test status
Simulation time 21543730261 ps
CPU time 217.11 seconds
Started Aug 11 05:27:14 PM PDT 24
Finished Aug 11 05:30:51 PM PDT 24
Peak memory 2503420 kb
Host smart-b0ea4aaa-2185-40d1-ae19-85f2f404f43f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809705040 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.1809705040
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull.1283434131
Short name T833
Test name
Test status
Simulation time 2864228098 ps
CPU time 2.95 seconds
Started Aug 11 05:27:22 PM PDT 24
Finished Aug 11 05:27:25 PM PDT 24
Peak memory 214216 kb
Host smart-1c590a74-7843-419e-9389-032b2b0c8b6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283434131 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_nack_acqfull.1283434131
Directory /workspace/9.i2c_target_nack_acqfull/latest

Test location /workspace/coverage/default/9.i2c_target_nack_acqfull_addr.2432894502
Short name T1332
Test name
Test status
Simulation time 888573455 ps
CPU time 2.61 seconds
Started Aug 11 05:27:24 PM PDT 24
Finished Aug 11 05:27:27 PM PDT 24
Peak memory 205620 kb
Host smart-af37612c-b305-4063-b2fb-058b4cd8f1d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432894502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.2432894502
Directory /workspace/9.i2c_target_nack_acqfull_addr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.2064530692
Short name T190
Test name
Test status
Simulation time 598178567 ps
CPU time 4.2 seconds
Started Aug 11 05:27:14 PM PDT 24
Finished Aug 11 05:27:18 PM PDT 24
Peak memory 221864 kb
Host smart-e790c469-f963-4cf7-9953-9e0f56cec135
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064530692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.2064530692
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smbus_maxlen.1187203871
Short name T834
Test name
Test status
Simulation time 551536685 ps
CPU time 2.54 seconds
Started Aug 11 05:27:23 PM PDT 24
Finished Aug 11 05:27:26 PM PDT 24
Peak memory 205384 kb
Host smart-159b2fdc-e0c3-4399-8c49-a5c77475836c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187203871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_smbus_maxlen.1187203871
Directory /workspace/9.i2c_target_smbus_maxlen/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.19591484
Short name T1041
Test name
Test status
Simulation time 4509895631 ps
CPU time 19.89 seconds
Started Aug 11 05:27:17 PM PDT 24
Finished Aug 11 05:27:37 PM PDT 24
Peak memory 222100 kb
Host smart-445a2bb4-c76c-47e1-9090-caab2b180ffe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19591484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targe
t_smoke.19591484
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.1575648651
Short name T1064
Test name
Test status
Simulation time 32404985129 ps
CPU time 966.18 seconds
Started Aug 11 05:27:15 PM PDT 24
Finished Aug 11 05:43:22 PM PDT 24
Peak memory 5894256 kb
Host smart-48e6e7cd-ab5f-47a2-a53b-c8995ce19ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575648651 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_stress_all.1575648651
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1943013765
Short name T1571
Test name
Test status
Simulation time 2233431294 ps
CPU time 20.79 seconds
Started Aug 11 05:27:15 PM PDT 24
Finished Aug 11 05:27:36 PM PDT 24
Peak memory 220912 kb
Host smart-1f8ce18a-5ace-47b6-bb38-89efb712583e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943013765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1943013765
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.2130557699
Short name T680
Test name
Test status
Simulation time 66758561871 ps
CPU time 298.5 seconds
Started Aug 11 05:27:14 PM PDT 24
Finished Aug 11 05:32:13 PM PDT 24
Peak memory 3013164 kb
Host smart-8cf66fb7-927e-4008-afbc-f5c35e752173
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130557699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.2130557699
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.979711059
Short name T1556
Test name
Test status
Simulation time 498282442 ps
CPU time 1.5 seconds
Started Aug 11 05:27:14 PM PDT 24
Finished Aug 11 05:27:15 PM PDT 24
Peak memory 205620 kb
Host smart-476d0a81-3353-4954-9e2e-149a51aaf428
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979711059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.979711059
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3994251392
Short name T311
Test name
Test status
Simulation time 1224435493 ps
CPU time 6.9 seconds
Started Aug 11 05:27:16 PM PDT 24
Finished Aug 11 05:27:23 PM PDT 24
Peak memory 213784 kb
Host smart-08f12882-c25a-4a37-91c6-a510cac9d328
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994251392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3994251392
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.1485988247
Short name T492
Test name
Test status
Simulation time 213983609 ps
CPU time 3.67 seconds
Started Aug 11 05:27:23 PM PDT 24
Finished Aug 11 05:27:26 PM PDT 24
Peak memory 205668 kb
Host smart-46ab60e6-b262-477e-aa5c-3624c4631691
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485988247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.1485988247
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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