Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	734182	1			T1	2		T2	1		T3	1514
all_values[1]	734182	1			T1	2		T2	1		T3	1514
all_values[2]	734182	1			T1	2		T2	1		T3	1514
all_values[3]	734182	1			T1	2		T2	1		T3	1514
all_values[4]	734182	1			T1	2		T2	1		T3	1514
all_values[5]	734182	1			T1	2		T2	1		T3	1514
all_values[6]	734182	1			T1	2		T2	1		T3	1514
all_values[7]	734182	1			T1	2		T2	1		T3	1514
all_values[8]	734182	1			T1	2		T2	1		T3	1514
all_values[9]	734182	1			T1	2		T2	1		T3	1514
all_values[10]	734182	1			T1	2		T2	1		T3	1514
all_values[11]	734182	1			T1	2		T2	1		T3	1514
all_values[12]	734182	1			T1	2		T2	1		T3	1514
all_values[13]	734182	1			T1	2		T2	1		T3	1514
all_values[14]	734182	1			T1	2		T2	1		T3	1514

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9052638

1

T1

26

T2

13

T3

20537

auto[1]

1960092

1

T1

4

T2

2

T3

2173

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10158108

1

T1

30

T2

15

T3

22710

auto[1]

854622

1

T20

522417

T19

159160

T161

65

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104222	1			T3	1208		T7	2		T14	3632
all_values[0]	auto[0]	auto[1]	5946	1			T20	3402		T19	883		T216	4
all_values[0]	auto[1]	auto[0]	567343	1			T1	2		T2	1		T3	306
all_values[0]	auto[1]	auto[1]	56671	1			T20	36784		T19	9728		T161	4
all_values[1]	auto[0]	auto[0]	671149	1			T1	2		T2	1		T3	1514
all_values[1]	auto[0]	auto[1]	62748	1			T20	40183		T19	10609		T161	3
all_values[1]	auto[1]	auto[0]	129	1			T248	1		T172	1		T174	7
all_values[1]	auto[1]	auto[1]	156	1			T20	4		T19	2		T161	2
all_values[2]	auto[0]	auto[0]	711295	1			T1	2		T2	1		T3	1514
all_values[2]	auto[0]	auto[1]	22553	1			T19	10606		T109	274		T216	5
all_values[2]	auto[1]	auto[0]	186	1			T8	1		T47	1		T134	1
all_values[2]	auto[1]	auto[1]	148	1			T19	5		T109	2		T216	4
all_values[3]	auto[0]	auto[0]	671278	1			T1	2		T2	1		T3	1514
all_values[3]	auto[0]	auto[1]	62737	1			T20	40185		T19	10606		T161	2
all_values[3]	auto[1]	auto[1]	167	1			T20	2		T19	4		T161	4
all_values[4]	auto[0]	auto[0]	671242	1			T1	2		T2	1		T3	1514
all_values[4]	auto[0]	auto[1]	62754	1			T20	40183		T19	10607		T161	4
all_values[4]	auto[1]	auto[0]	28	1			T196	1		T238	2		T249	1
all_values[4]	auto[1]	auto[1]	158	1			T20	4		T19	3		T161	1
all_values[5]	auto[0]	auto[0]	671300	1			T1	2		T2	1		T3	1514
all_values[5]	auto[0]	auto[1]	62735	1			T20	40186		T19	10605		T161	4
all_values[5]	auto[1]	auto[1]	147	1			T19	6		T161	1		T109	2
all_values[6]	auto[0]	auto[0]	679420	1			T1	2		T2	1		T3	1514
all_values[6]	auto[0]	auto[1]	54598	1			T20	40183		T19	10606		T161	3
all_values[6]	auto[1]	auto[1]	164	1			T20	4		T19	5		T161	3
all_values[7]	auto[0]	auto[0]	685749	1			T1	2		T2	1		T3	1148
all_values[7]	auto[0]	auto[1]	21475	1			T19	10276		T109	217		T216	6
all_values[7]	auto[1]	auto[0]	25739	1			T3	366		T7	4		T14	25
all_values[7]	auto[1]	auto[1]	1219	1			T19	334		T109	59		T216	2
all_values[8]	auto[0]	auto[0]	671286	1			T1	2		T2	1		T3	1514
all_values[8]	auto[0]	auto[1]	62732	1			T20	40185		T19	10606		T161	4
all_values[8]	auto[1]	auto[1]	164	1			T20	2		T19	5		T161	1
all_values[9]	auto[0]	auto[0]	150658	1			T1	2		T2	1		T3	1489
all_values[9]	auto[0]	auto[1]	8031	1			T20	3406		T19	547		T161	4
all_values[9]	auto[1]	auto[0]	520632	1			T3	25		T7	2		T8	1
all_values[9]	auto[1]	auto[1]	54861	1			T20	36780		T19	10064		T161	2
all_values[10]	auto[0]	auto[0]	671304	1			T1	2		T2	1		T3	1514
all_values[10]	auto[0]	auto[1]	62724	1			T20	40181		T19	10608		T161	3
all_values[10]	auto[1]	auto[1]	154	1			T20	3		T19	3		T161	3
all_values[11]	auto[0]	auto[0]	2362	1			T3	38		T7	2		T14	4
all_values[11]	auto[0]	auto[1]	343	1			T20	21		T19	23		T109	13
all_values[11]	auto[1]	auto[0]	668906	1			T1	2		T2	1		T3	1476
all_values[11]	auto[1]	auto[1]	62571	1			T20	40162		T19	10586		T161	6
all_values[12]	auto[0]	auto[0]	671219	1			T1	2		T2	1		T3	1514
all_values[12]	auto[0]	auto[1]	62738	1			T20	40182		T19	10608		T109	273
all_values[12]	auto[1]	auto[0]	62	1			T47	1		T197	1		T61	1
all_values[12]	auto[1]	auto[1]	163	1			T20	3		T19	3		T109	3
all_values[13]	auto[0]	auto[0]	671297	1			T1	2		T2	1		T3	1514
all_values[13]	auto[0]	auto[1]	62733	1			T20	40182		T19	10609		T161	2
all_values[13]	auto[1]	auto[1]	152	1			T20	5		T19	2		T161	4
all_values[14]	auto[0]	auto[0]	671302	1			T1	2		T2	1		T3	1514
all_values[14]	auto[0]	auto[1]	62708	1			T20	40183		T19	10605		T161	2
all_values[14]	auto[1]	auto[1]	172	1			T20	2		T19	6		T161	3