Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	734182	1			T1	2		T2	1		T3	1514
all_pins[1]	734182	1			T1	2		T2	1		T3	1514
all_pins[2]	734182	1			T1	2		T2	1		T3	1514
all_pins[3]	734182	1			T1	2		T2	1		T3	1514
all_pins[4]	734182	1			T1	2		T2	1		T3	1514
all_pins[5]	734182	1			T1	2		T2	1		T3	1514
all_pins[6]	734182	1			T1	2		T2	1		T3	1514
all_pins[7]	734182	1			T1	2		T2	1		T3	1514
all_pins[8]	734182	1			T1	2		T2	1		T3	1514
all_pins[9]	734182	1			T1	2		T2	1		T3	1514
all_pins[10]	734182	1			T1	2		T2	1		T3	1514
all_pins[11]	734182	1			T1	2		T2	1		T3	1514
all_pins[12]	734182	1			T1	2		T2	1		T3	1514
all_pins[13]	734182	1			T1	2		T2	1		T3	1514
all_pins[14]	734182	1			T1	2		T2	1		T3	1514

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9058902	1			T1	26		T2	13		T3	20529
values[0x1]	1953828	1			T1	4		T2	2		T3	2181
transitions[0x0=>0x1]	1953357	1			T1	4		T2	2		T3	2181
transitions[0x1=>0x0]	1952043	1			T1	3		T2	1		T3	2181

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	113711	1			T3	1208		T5	1		T7	37
all_pins[0]	values[0x1]	620471	1			T1	2		T2	1		T3	306
all_pins[0]	transitions[0x0=>0x1]	620288	1			T1	2		T2	1		T3	306
all_pins[0]	transitions[0x1=>0x0]	54	1			T172	1		T19	1		T257	2
all_pins[1]	values[0x0]	733945	1			T1	2		T2	1		T3	1514
all_pins[1]	values[0x1]	237	1			T20	1		T248	1		T172	1
all_pins[1]	transitions[0x0=>0x1]	221	1			T20	1		T248	1		T172	1
all_pins[1]	transitions[0x1=>0x0]	113	1			T8	1		T47	1		T134	1
all_pins[2]	values[0x0]	734053	1			T1	2		T2	1		T3	1514
all_pins[2]	values[0x1]	129	1			T8	1		T47	1		T134	1
all_pins[2]	transitions[0x0=>0x1]	112	1			T8	1		T47	1		T134	1
all_pins[2]	transitions[0x1=>0x0]	68	1			T20	1		T19	1		T161	2
all_pins[3]	values[0x0]	734097	1			T1	2		T2	1		T3	1514
all_pins[3]	values[0x1]	85	1			T20	1		T19	1		T161	2
all_pins[3]	transitions[0x0=>0x1]	70	1			T19	1		T161	1		T109	2
all_pins[3]	transitions[0x1=>0x0]	98	1			T20	2		T196	1		T238	2
all_pins[4]	values[0x0]	734069	1			T1	2		T2	1		T3	1514
all_pins[4]	values[0x1]	113	1			T20	3		T196	1		T238	2
all_pins[4]	transitions[0x0=>0x1]	94	1			T20	3		T196	1		T238	2
all_pins[4]	transitions[0x1=>0x0]	64	1			T19	3		T258	3		T259	2
all_pins[5]	values[0x0]	734099	1			T1	2		T2	1		T3	1514
all_pins[5]	values[0x1]	83	1			T19	4		T161	1		T217	1
all_pins[5]	transitions[0x0=>0x1]	65	1			T19	2		T161	1		T217	1
all_pins[5]	transitions[0x1=>0x0]	56	1			T20	3		T161	1		T109	1
all_pins[6]	values[0x0]	734108	1			T1	2		T2	1		T3	1514
all_pins[6]	values[0x1]	74	1			T20	3		T19	2		T161	1
all_pins[6]	transitions[0x0=>0x1]	56	1			T20	3		T19	2		T161	1
all_pins[6]	transitions[0x1=>0x0]	29357	1			T3	374		T14	25		T20	712
all_pins[7]	values[0x0]	704807	1			T1	2		T2	1		T3	1140
all_pins[7]	values[0x1]	29375	1			T3	374		T14	25		T20	712
all_pins[7]	transitions[0x0=>0x1]	29362	1			T3	374		T14	25		T20	712
all_pins[7]	transitions[0x1=>0x0]	75	1			T20	2		T19	2		T109	1
all_pins[8]	values[0x0]	734094	1			T1	2		T2	1		T3	1514
all_pins[8]	values[0x1]	88	1			T20	2		T19	2		T109	1
all_pins[8]	transitions[0x0=>0x1]	67	1			T20	2		T19	1		T109	1
all_pins[8]	transitions[0x1=>0x0]	575418	1			T3	25		T7	2		T8	1
all_pins[9]	values[0x0]	158743	1			T1	2		T2	1		T3	1489
all_pins[9]	values[0x1]	575439	1			T3	25		T7	2		T8	1
all_pins[9]	transitions[0x0=>0x1]	575420	1			T3	25		T7	2		T8	1
all_pins[9]	transitions[0x1=>0x0]	54	1			T20	2		T19	1		T161	2
all_pins[10]	values[0x0]	734109	1			T1	2		T2	1		T3	1514
all_pins[10]	values[0x1]	73	1			T20	2		T19	1		T161	3
all_pins[10]	transitions[0x0=>0x1]	50	1			T20	2		T161	2		T217	1
all_pins[10]	transitions[0x1=>0x0]	727323	1			T1	2		T2	1		T3	1476
all_pins[11]	values[0x0]	6836	1			T3	38		T5	1		T7	37
all_pins[11]	values[0x1]	727346	1			T1	2		T2	1		T3	1476
all_pins[11]	transitions[0x0=>0x1]	727308	1			T1	2		T2	1		T3	1476
all_pins[11]	transitions[0x1=>0x0]	111	1			T20	1		T61	1		T62	1
all_pins[12]	values[0x0]	734033	1			T1	2		T2	1		T3	1514
all_pins[12]	values[0x1]	149	1			T20	1		T47	1		T197	1
all_pins[12]	transitions[0x0=>0x1]	129	1			T47	1		T197	1		T61	1
all_pins[12]	transitions[0x1=>0x0]	63	1			T20	3		T19	1		T161	1
all_pins[13]	values[0x0]	734099	1			T1	2		T2	1		T3	1514
all_pins[13]	values[0x1]	83	1			T20	4		T19	1		T161	1
all_pins[13]	transitions[0x0=>0x1]	62	1			T20	3		T19	1		T109	2
all_pins[13]	transitions[0x1=>0x0]	62	1			T19	3		T109	2		T216	2
all_pins[14]	values[0x0]	734099	1			T1	2		T2	1		T3	1514
all_pins[14]	values[0x1]	83	1			T20	1		T19	3		T161	1
all_pins[14]	transitions[0x0=>0x1]	53	1			T19	1		T161	1		T109	1
all_pins[14]	transitions[0x1=>0x0]	619127	1			T1	1		T3	306		T4	1