Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	359	1			T20	7		T19	7		T161	4
all_values[1]	359	1			T20	7		T19	7		T161	4
all_values[2]	359	1			T20	7		T19	7		T161	4
all_values[3]	359	1			T20	7		T19	7		T161	4
all_values[4]	359	1			T20	7		T19	7		T161	4
all_values[5]	359	1			T20	7		T19	7		T161	4
all_values[6]	359	1			T20	7		T19	7		T161	4
all_values[7]	359	1			T20	7		T19	7		T161	4
all_values[8]	359	1			T20	7		T19	7		T161	4
all_values[9]	359	1			T20	7		T19	7		T161	4
all_values[10]	359	1			T20	7		T19	7		T161	4
all_values[11]	359	1			T20	7		T19	7		T161	4
all_values[12]	359	1			T20	7		T19	7		T161	4
all_values[13]	359	1			T20	7		T19	7		T161	4
all_values[14]	359	1			T20	7		T19	7		T161	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2923

1

T20

58

T19

61

T161

24

auto[1]

2462

1

T20

47

T19

44

T161

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

920

1

T20

28

T19

5

T161

19

auto[1]

4465

1

T20

77

T19

100

T161

41

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3160

1

T20

64

T19

55

T161

40

auto[1]

2225

1

T20

41

T19

50

T161

20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	42	1			T20	1		T161	1		T109	3
all_values[0]	auto[0]	auto[0]	auto[1]	71	1			T20	3		T19	1		T161	1
all_values[0]	auto[0]	auto[1]	auto[0]	23	1			T161	1		T109	1		T258	1
all_values[0]	auto[0]	auto[1]	auto[1]	70	1			T19	1		T216	2		T217	2
all_values[0]	auto[1]	auto[0]	auto[1]	94	1			T20	2		T19	5		T216	2
all_values[0]	auto[1]	auto[1]	auto[1]	59	1			T20	1		T161	1		T216	3
all_values[1]	auto[0]	auto[0]	auto[0]	32	1			T161	1		T109	1		T260	1
all_values[1]	auto[0]	auto[0]	auto[1]	83	1			T20	2		T19	3		T109	1
all_values[1]	auto[0]	auto[1]	auto[0]	19	1			T258	1		T261	1		T110	1
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T20	1		T19	2		T161	1
all_values[1]	auto[1]	auto[0]	auto[1]	73	1			T20	2		T109	2		T216	1
all_values[1]	auto[1]	auto[1]	auto[1]	76	1			T20	2		T19	2		T161	2
all_values[2]	auto[0]	auto[0]	auto[0]	43	1			T20	3		T161	1		T262	1
all_values[2]	auto[0]	auto[0]	auto[1]	73	1			T19	2		T109	2		T216	2
all_values[2]	auto[0]	auto[1]	auto[0]	30	1			T20	4		T161	3		T259	1
all_values[2]	auto[0]	auto[1]	auto[1]	65	1			T216	1		T217	1		T258	2
all_values[2]	auto[1]	auto[0]	auto[1]	83	1			T19	5		T109	1		T216	4
all_values[2]	auto[1]	auto[1]	auto[1]	65	1			T109	1		T217	2		T258	4
all_values[3]	auto[0]	auto[0]	auto[0]	30	1			T19	1		T216	1		T259	1
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T20	3		T19	2		T161	1
all_values[3]	auto[0]	auto[1]	auto[0]	24	1			T258	2		T259	2		T261	2
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T20	1		T19	2		T161	2
all_values[3]	auto[1]	auto[0]	auto[1]	72	1			T20	1		T19	1		T217	1
all_values[3]	auto[1]	auto[1]	auto[1]	78	1			T20	2		T19	1		T161	1
all_values[4]	auto[0]	auto[0]	auto[0]	22	1			T19	1		T161	1		T262	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T20	2		T19	2		T161	1
all_values[4]	auto[0]	auto[1]	auto[0]	23	1			T109	2		T258	1		T260	1
all_values[4]	auto[0]	auto[1]	auto[1]	69	1			T20	1		T19	1		T161	1
all_values[4]	auto[1]	auto[0]	auto[1]	81	1			T19	3		T216	3		T262	2
all_values[4]	auto[1]	auto[1]	auto[1]	77	1			T20	4		T161	1		T109	1
all_values[5]	auto[0]	auto[0]	auto[0]	49	1			T20	1		T109	1		T216	2
all_values[5]	auto[0]	auto[0]	auto[1]	60	1			T20	1		T19	1		T109	1
all_values[5]	auto[0]	auto[1]	auto[0]	24	1			T161	1		T109	1		T259	2
all_values[5]	auto[0]	auto[1]	auto[1]	88	1			T20	3		T19	1		T161	1
all_values[5]	auto[1]	auto[0]	auto[1]	75	1			T19	3		T109	1		T216	1
all_values[5]	auto[1]	auto[1]	auto[1]	63	1			T20	2		T19	2		T161	2
all_values[6]	auto[0]	auto[0]	auto[0]	34	1			T260	1		T261	1		T111	2
all_values[6]	auto[0]	auto[0]	auto[1]	86	1			T20	2		T19	1		T161	1
all_values[6]	auto[0]	auto[1]	auto[0]	22	1			T217	1		T111	2		T113	1
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T20	1		T19	2		T161	1
all_values[6]	auto[1]	auto[0]	auto[1]	90	1			T20	2		T19	3		T109	1
all_values[6]	auto[1]	auto[1]	auto[1]	57	1			T20	2		T19	1		T161	2
all_values[7]	auto[0]	auto[0]	auto[0]	56	1			T20	5		T161	2		T216	1
all_values[7]	auto[0]	auto[0]	auto[1]	67	1			T19	2		T109	2		T258	2
all_values[7]	auto[0]	auto[1]	auto[0]	23	1			T20	2		T19	1		T161	2
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T19	2		T109	1		T216	2
all_values[7]	auto[1]	auto[0]	auto[1]	84	1			T19	1		T109	1		T216	1
all_values[7]	auto[1]	auto[1]	auto[1]	56	1			T19	1		T216	3		T258	2
all_values[8]	auto[0]	auto[0]	auto[0]	36	1			T161	1		T109	1		T216	3
all_values[8]	auto[0]	auto[0]	auto[1]	77	1			T20	1		T19	2		T161	1
all_values[8]	auto[0]	auto[1]	auto[0]	23	1			T216	4		T259	1		T110	2
all_values[8]	auto[0]	auto[1]	auto[1]	87	1			T20	3		T19	3		T161	1
all_values[8]	auto[1]	auto[0]	auto[1]	68	1			T20	2		T19	1		T161	1
all_values[8]	auto[1]	auto[1]	auto[1]	68	1			T20	1		T19	1		T109	1
all_values[9]	auto[0]	auto[0]	auto[0]	37	1			T216	1		T260	1		T263	2
all_values[9]	auto[0]	auto[0]	auto[1]	79	1			T20	2		T19	1		T161	1
all_values[9]	auto[0]	auto[1]	auto[0]	27	1			T20	1		T216	3		T258	1
all_values[9]	auto[0]	auto[1]	auto[1]	75	1			T19	2		T161	1		T109	2
all_values[9]	auto[1]	auto[0]	auto[1]	74	1			T20	3		T19	2		T161	1
all_values[9]	auto[1]	auto[1]	auto[1]	67	1			T20	1		T19	2		T161	1
all_values[10]	auto[0]	auto[0]	auto[0]	35	1			T20	3		T262	1		T259	1
all_values[10]	auto[0]	auto[0]	auto[1]	68	1			T19	3		T109	1		T216	2
all_values[10]	auto[0]	auto[1]	auto[0]	21	1			T109	2		T262	2		T259	1
all_values[10]	auto[0]	auto[1]	auto[1]	81	1			T20	1		T19	1		T161	1
all_values[10]	auto[1]	auto[0]	auto[1]	86	1			T20	2		T19	2		T109	1
all_values[10]	auto[1]	auto[1]	auto[1]	68	1			T20	1		T19	1		T161	3
all_values[11]	auto[0]	auto[0]	auto[0]	26	1			T20	2		T109	1		T216	1
all_values[11]	auto[0]	auto[0]	auto[1]	81	1			T20	1		T19	1		T161	2
all_values[11]	auto[0]	auto[1]	auto[0]	19	1			T20	2		T19	2		T262	1
all_values[11]	auto[0]	auto[1]	auto[1]	70	1			T20	1		T19	1		T161	1
all_values[11]	auto[1]	auto[0]	auto[1]	99	1			T20	1		T19	1		T161	1
all_values[11]	auto[1]	auto[1]	auto[1]	64	1			T19	2		T109	1		T216	4
all_values[12]	auto[0]	auto[0]	auto[0]	35	1			T20	1		T161	2		T258	1
all_values[12]	auto[0]	auto[0]	auto[1]	71	1			T20	1		T19	2		T109	1
all_values[12]	auto[0]	auto[1]	auto[0]	19	1			T20	1		T161	2		T259	1
all_values[12]	auto[0]	auto[1]	auto[1]	71	1			T20	1		T19	2		T217	1
all_values[12]	auto[1]	auto[0]	auto[1]	83	1			T20	2		T19	1		T109	2
all_values[12]	auto[1]	auto[1]	auto[1]	80	1			T20	1		T19	2		T109	1
all_values[13]	auto[0]	auto[0]	auto[0]	42	1			T109	2		T262	1		T263	1
all_values[13]	auto[0]	auto[0]	auto[1]	77	1			T20	1		T19	1		T161	1
all_values[13]	auto[0]	auto[1]	auto[0]	29	1			T262	2		T261	2		T113	1
all_values[13]	auto[0]	auto[1]	auto[1]	78	1			T20	1		T19	3		T161	1
all_values[13]	auto[1]	auto[0]	auto[1]	70	1			T20	2		T19	3		T161	1
all_values[13]	auto[1]	auto[1]	auto[1]	63	1			T20	3		T161	1		T109	1
all_values[14]	auto[0]	auto[0]	auto[0]	48	1			T20	1		T161	1		T216	1
all_values[14]	auto[0]	auto[0]	auto[1]	73	1			T20	2		T161	1		T109	1
all_values[14]	auto[0]	auto[1]	auto[0]	27	1			T20	1		T217	1		T262	1
all_values[14]	auto[0]	auto[1]	auto[1]	59	1			T20	1		T19	3		T216	1
all_values[14]	auto[1]	auto[0]	auto[1]	88	1			T20	1		T19	4		T109	1
all_values[14]	auto[1]	auto[1]	auto[1]	64	1			T20	1		T161	2		T109	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal