Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	724962	1			T1	2		T2	66		T3	2
all_values[1]	724962	1			T1	2		T2	66		T3	2
all_values[2]	724962	1			T1	2		T2	66		T3	2
all_values[3]	724962	1			T1	2		T2	66		T3	2
all_values[4]	724962	1			T1	2		T2	66		T3	2
all_values[5]	724962	1			T1	2		T2	66		T3	2
all_values[6]	724962	1			T1	2		T2	66		T3	2
all_values[7]	724962	1			T1	2		T2	66		T3	2
all_values[8]	724962	1			T1	2		T2	66		T3	2
all_values[9]	724962	1			T1	2		T2	66		T3	2
all_values[10]	724962	1			T1	2		T2	66		T3	2
all_values[11]	724962	1			T1	2		T2	66		T3	2
all_values[12]	724962	1			T1	2		T2	66		T3	2
all_values[13]	724962	1			T1	2		T2	66		T3	2
all_values[14]	724962	1			T1	2		T2	66		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8925939

1

T1

26

T2

852

T3

26

auto[1]

1948491

1

T1

4

T2

138

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10485745

1

T1

30

T2

990

T3

30

auto[1]

388685

1

T182

82726

T180

10299

T32

269789

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	86845	1			T2	4		T5	1		T6	2
all_values[0]	auto[0]	auto[1]	1490	1			T182	122		T180	425		T32	22
all_values[0]	auto[1]	auto[0]	611178	1			T1	2		T2	62		T3	2
all_values[0]	auto[1]	auto[1]	25449	1			T182	6242		T180	263		T32	17964
all_values[1]	auto[0]	auto[0]	697722	1			T1	2		T2	66		T3	2
all_values[1]	auto[0]	auto[1]	26801	1			T182	6358		T180	684		T32	17983
all_values[1]	auto[1]	auto[0]	295	1			T276	1		T277	26		T278	1
all_values[1]	auto[1]	auto[1]	144	1			T182	4		T180	3		T32	4
all_values[2]	auto[0]	auto[0]	697836	1			T1	2		T2	66		T3	2
all_values[2]	auto[0]	auto[1]	26791	1			T182	6362		T180	684		T32	17981
all_values[2]	auto[1]	auto[0]	194	1			T162	1		T53	1		T240	2
all_values[2]	auto[1]	auto[1]	141	1			T182	2		T180	4		T32	2
all_values[3]	auto[0]	auto[0]	698685	1			T1	2		T2	66		T3	2
all_values[3]	auto[0]	auto[1]	26120	1			T182	6362		T180	682		T32	17982
all_values[3]	auto[1]	auto[1]	157	1			T182	2		T180	4		T32	2
all_values[4]	auto[0]	auto[0]	698006	1			T1	2		T2	66		T3	2
all_values[4]	auto[0]	auto[1]	26804	1			T182	6361		T180	683		T32	17984
all_values[4]	auto[1]	auto[0]	16	1			T268	1		T262	1		T263	1
all_values[4]	auto[1]	auto[1]	136	1			T182	3		T180	5		T32	2
all_values[5]	auto[0]	auto[0]	705054	1			T1	2		T2	66		T3	2
all_values[5]	auto[0]	auto[1]	19736	1			T180	685		T32	17980		T181	2
all_values[5]	auto[1]	auto[1]	172	1			T180	2		T32	7		T181	7
all_values[6]	auto[0]	auto[0]	698027	1			T1	2		T2	66		T3	2
all_values[6]	auto[0]	auto[1]	26771	1			T182	6360		T180	681		T32	17980
all_values[6]	auto[1]	auto[1]	164	1			T182	2		T32	6		T181	4
all_values[7]	auto[0]	auto[0]	671833	1			T1	2		T2	59		T3	2
all_values[7]	auto[0]	auto[1]	25233	1			T182	5578		T180	486		T32	17808
all_values[7]	auto[1]	auto[0]	26185	1			T2	7		T5	1		T8	1
all_values[7]	auto[1]	auto[1]	1711	1			T182	786		T180	202		T32	178
all_values[8]	auto[0]	auto[0]	704385	1			T1	2		T2	66		T3	2
all_values[8]	auto[0]	auto[1]	20420	1			T180	685		T32	17984		T181	2
all_values[8]	auto[1]	auto[1]	157	1			T180	3		T32	3		T181	6
all_values[9]	auto[0]	auto[0]	154270	1			T1	2		T2	61		T3	2
all_values[9]	auto[0]	auto[1]	11344	1			T182	3104		T180	676		T32	5879
all_values[9]	auto[1]	auto[0]	543759	1			T2	5		T5	1		T8	1
all_values[9]	auto[1]	auto[1]	15589	1			T182	3260		T180	12		T32	12108
all_values[10]	auto[0]	auto[0]	698028	1			T1	2		T2	66		T3	2
all_values[10]	auto[0]	auto[1]	26800	1			T182	6363		T180	684		T32	17982
all_values[10]	auto[1]	auto[1]	134	1			T182	1		T180	4		T32	3
all_values[11]	auto[0]	auto[0]	2299	1			T2	2		T5	1		T6	2
all_values[11]	auto[0]	auto[1]	254	1			T182	11		T180	22		T32	15
all_values[11]	auto[1]	auto[0]	695743	1			T1	2		T2	64		T3	2
all_values[11]	auto[1]	auto[1]	26666	1			T182	6351		T180	665		T32	17970
all_values[12]	auto[0]	auto[0]	697948	1			T1	2		T2	66		T3	2
all_values[12]	auto[0]	auto[1]	26814	1			T182	6361		T180	684		T32	17984
all_values[12]	auto[1]	auto[0]	67	1			T53	1		T55	1		T71	1
all_values[12]	auto[1]	auto[1]	133	1			T182	3		T180	3		T32	3
all_values[13]	auto[0]	auto[0]	698685	1			T1	2		T2	66		T3	2
all_values[13]	auto[0]	auto[1]	26119	1			T182	6361		T180	683		T32	17986
all_values[13]	auto[1]	auto[1]	158	1			T182	3		T180	4		T32	1
all_values[14]	auto[0]	auto[0]	698685	1			T1	2		T2	66		T3	2
all_values[14]	auto[0]	auto[1]	26134	1			T182	6363		T180	679		T32	17982
all_values[14]	auto[1]	auto[1]	143	1			T182	1		T180	2		T32	4