Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	724962	1			T1	2		T2	66		T3	2
all_pins[1]	724962	1			T1	2		T2	66		T3	2
all_pins[2]	724962	1			T1	2		T2	66		T3	2
all_pins[3]	724962	1			T1	2		T2	66		T3	2
all_pins[4]	724962	1			T1	2		T2	66		T3	2
all_pins[5]	724962	1			T1	2		T2	66		T3	2
all_pins[6]	724962	1			T1	2		T2	66		T3	2
all_pins[7]	724962	1			T1	2		T2	66		T3	2
all_pins[8]	724962	1			T1	2		T2	66		T3	2
all_pins[9]	724962	1			T1	2		T2	66		T3	2
all_pins[10]	724962	1			T1	2		T2	66		T3	2
all_pins[11]	724962	1			T1	2		T2	66		T3	2
all_pins[12]	724962	1			T1	2		T2	66		T3	2
all_pins[13]	724962	1			T1	2		T2	66		T3	2
all_pins[14]	724962	1			T1	2		T2	66		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8932226	1			T1	26		T2	985		T3	26
values[0x1]	1942204	1			T1	4		T2	5		T3	4
transitions[0x0=>0x1]	1941565	1			T1	4		T2	5		T3	4
transitions[0x1=>0x0]	1940250	1			T1	3		T2	5		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	91807	1			T2	66		T5	1		T6	2
all_pins[0]	values[0x1]	633155	1			T1	2		T3	2		T4	2
all_pins[0]	transitions[0x0=>0x1]	632803	1			T1	2		T3	2		T4	2
all_pins[0]	transitions[0x1=>0x0]	49	1			T182	1		T180	1		T32	2
all_pins[1]	values[0x0]	724561	1			T1	2		T2	66		T3	2
all_pins[1]	values[0x1]	401	1			T276	1		T277	27		T278	1
all_pins[1]	transitions[0x0=>0x1]	385	1			T276	1		T277	27		T278	1
all_pins[1]	transitions[0x1=>0x0]	106	1			T162	1		T282	1		T283	1
all_pins[2]	values[0x0]	724840	1			T1	2		T2	66		T3	2
all_pins[2]	values[0x1]	122	1			T162	1		T282	1		T283	1
all_pins[2]	transitions[0x0=>0x1]	110	1			T162	1		T282	1		T283	1
all_pins[2]	transitions[0x1=>0x0]	50	1			T180	2		T116	4		T255	2
all_pins[3]	values[0x0]	724900	1			T1	2		T2	66		T3	2
all_pins[3]	values[0x1]	62	1			T180	2		T116	4		T255	2
all_pins[3]	transitions[0x0=>0x1]	50	1			T180	1		T116	2		T255	2
all_pins[3]	transitions[0x1=>0x0]	73	1			T268	1		T182	1		T180	3
all_pins[4]	values[0x0]	724877	1			T1	2		T2	66		T3	2
all_pins[4]	values[0x1]	85	1			T268	1		T182	1		T180	4
all_pins[4]	transitions[0x0=>0x1]	70	1			T268	1		T182	1		T180	4
all_pins[4]	transitions[0x1=>0x0]	71	1			T32	1		T181	1		T116	1
all_pins[5]	values[0x0]	724876	1			T1	2		T2	66		T3	2
all_pins[5]	values[0x1]	86	1			T32	2		T181	2		T116	2
all_pins[5]	transitions[0x0=>0x1]	69	1			T32	1		T181	1		T116	2
all_pins[5]	transitions[0x1=>0x0]	48	1			T32	2		T181	2		T116	1
all_pins[6]	values[0x0]	724897	1			T1	2		T2	66		T3	2
all_pins[6]	values[0x1]	65	1			T32	3		T181	3		T116	1
all_pins[6]	transitions[0x0=>0x1]	48	1			T32	2		T181	3		T255	1
all_pins[6]	transitions[0x1=>0x0]	30135	1			T5	1		T8	1		T9	1
all_pins[7]	values[0x0]	694810	1			T1	2		T2	66		T3	2
all_pins[7]	values[0x1]	30152	1			T5	1		T8	1		T9	1
all_pins[7]	transitions[0x0=>0x1]	30131	1			T5	1		T8	1		T9	1
all_pins[7]	transitions[0x1=>0x0]	60	1			T180	1		T32	1		T181	3
all_pins[8]	values[0x0]	724881	1			T1	2		T2	66		T3	2
all_pins[8]	values[0x1]	81	1			T180	1		T32	1		T181	4
all_pins[8]	transitions[0x0=>0x1]	52	1			T180	1		T32	1		T181	3
all_pins[8]	transitions[0x1=>0x0]	559266	1			T2	5		T5	1		T8	1
all_pins[9]	values[0x0]	165667	1			T1	2		T2	61		T3	2
all_pins[9]	values[0x1]	559295	1			T2	5		T5	1		T8	1
all_pins[9]	transitions[0x0=>0x1]	559274	1			T2	5		T5	1		T8	1
all_pins[9]	transitions[0x1=>0x0]	49	1			T182	1		T180	3		T32	3
all_pins[10]	values[0x0]	724892	1			T1	2		T2	66		T3	2
all_pins[10]	values[0x1]	70	1			T182	1		T180	4		T32	3
all_pins[10]	transitions[0x0=>0x1]	53	1			T182	1		T180	4		T32	2
all_pins[10]	transitions[0x1=>0x0]	718316	1			T1	2		T3	2		T4	2
all_pins[11]	values[0x0]	6629	1			T2	66		T5	1		T6	2
all_pins[11]	values[0x1]	718333	1			T1	2		T3	2		T4	2
all_pins[11]	transitions[0x0=>0x1]	718294	1			T1	2		T3	2		T4	2
all_pins[11]	transitions[0x1=>0x0]	97	1			T53	1		T55	1		T71	1
all_pins[12]	values[0x0]	724826	1			T1	2		T2	66		T3	2
all_pins[12]	values[0x1]	136	1			T53	1		T55	1		T71	1
all_pins[12]	transitions[0x0=>0x1]	117	1			T53	1		T55	1		T71	1
all_pins[12]	transitions[0x1=>0x0]	70	1			T180	2		T181	1		T116	1
all_pins[13]	values[0x0]	724873	1			T1	2		T2	66		T3	2
all_pins[13]	values[0x1]	89	1			T182	1		T180	2		T32	1
all_pins[13]	transitions[0x0=>0x1]	66	1			T182	1		T180	2		T181	3
all_pins[13]	transitions[0x1=>0x0]	49	1			T182	1		T180	2		T32	2
all_pins[14]	values[0x0]	724890	1			T1	2		T2	66		T3	2
all_pins[14]	values[0x1]	72	1			T182	1		T180	2		T32	3
all_pins[14]	transitions[0x0=>0x1]	43	1			T182	1		T180	2		T32	2
all_pins[14]	transitions[0x1=>0x0]	631811	1			T1	1		T3	1		T4	1