Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	336	1			T182	4		T180	8		T32	7
all_values[1]	336	1			T182	4		T180	8		T32	7
all_values[2]	336	1			T182	4		T180	8		T32	7
all_values[3]	336	1			T182	4		T180	8		T32	7
all_values[4]	336	1			T182	4		T180	8		T32	7
all_values[5]	336	1			T182	4		T180	8		T32	7
all_values[6]	336	1			T182	4		T180	8		T32	7
all_values[7]	336	1			T182	4		T180	8		T32	7
all_values[8]	336	1			T182	4		T180	8		T32	7
all_values[9]	336	1			T182	4		T180	8		T32	7
all_values[10]	336	1			T182	4		T180	8		T32	7
all_values[11]	336	1			T182	4		T180	8		T32	7
all_values[12]	336	1			T182	4		T180	8		T32	7
all_values[13]	336	1			T182	4		T180	8		T32	7
all_values[14]	336	1			T182	4		T180	8		T32	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2717

1

T182

43

T180

60

T32

46

auto[1]

2323

1

T182

17

T180

60

T32

59

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

840

1

T182

14

T180

19

T32

16

auto[1]

4200

1

T182

46

T180

101

T32

89

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2973

1

T182

37

T180

80

T32

59

auto[1]

2067

1

T182

23

T180

40

T32

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	26	1			T284	1		T285	1		T127	1
all_values[0]	auto[0]	auto[0]	auto[1]	64	1			T180	3		T32	3		T181	1
all_values[0]	auto[0]	auto[1]	auto[0]	26	1			T32	1		T285	1		T125	1
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T182	2		T180	4		T32	1
all_values[0]	auto[1]	auto[0]	auto[1]	80	1			T182	2		T180	1		T32	1
all_values[0]	auto[1]	auto[1]	auto[1]	59	1			T32	1		T181	3		T116	3
all_values[1]	auto[0]	auto[0]	auto[0]	24	1			T182	1		T180	1		T286	1
all_values[1]	auto[0]	auto[0]	auto[1]	89	1			T180	4		T32	2		T181	3
all_values[1]	auto[0]	auto[1]	auto[0]	22	1			T182	1		T255	2		T285	2
all_values[1]	auto[0]	auto[1]	auto[1]	60	1			T182	1		T32	1		T116	3
all_values[1]	auto[1]	auto[0]	auto[1]	85	1			T180	2		T181	4		T116	1
all_values[1]	auto[1]	auto[1]	auto[1]	56	1			T182	1		T180	1		T32	4
all_values[2]	auto[0]	auto[0]	auto[0]	30	1			T284	1		T285	1		T125	1
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T182	2		T180	2		T181	3
all_values[2]	auto[0]	auto[1]	auto[0]	28	1			T32	4		T285	2		T287	1
all_values[2]	auto[0]	auto[1]	auto[1]	55	1			T180	2		T32	1		T116	2
all_values[2]	auto[1]	auto[0]	auto[1]	73	1			T182	1		T180	2		T32	2
all_values[2]	auto[1]	auto[1]	auto[1]	68	1			T182	1		T180	2		T181	3
all_values[3]	auto[0]	auto[0]	auto[0]	38	1			T180	1		T32	2		T116	1
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T182	2		T180	2		T32	1
all_values[3]	auto[0]	auto[1]	auto[0]	26	1			T180	1		T32	1		T255	2
all_values[3]	auto[0]	auto[1]	auto[1]	56	1			T180	2		T181	4		T116	3
all_values[3]	auto[1]	auto[0]	auto[1]	75	1			T182	2		T180	1		T32	3
all_values[3]	auto[1]	auto[1]	auto[1]	53	1			T180	1		T181	1		T116	2
all_values[4]	auto[0]	auto[0]	auto[0]	28	1			T284	1		T125	1		T126	2
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T182	1		T180	1		T32	1
all_values[4]	auto[0]	auto[1]	auto[0]	21	1			T32	1		T181	1		T284	1
all_values[4]	auto[0]	auto[1]	auto[1]	71	1			T180	2		T32	3		T116	2
all_values[4]	auto[1]	auto[0]	auto[1]	82	1			T182	3		T180	1		T181	2
all_values[4]	auto[1]	auto[1]	auto[1]	54	1			T180	4		T32	2		T181	1
all_values[5]	auto[0]	auto[0]	auto[0]	43	1			T182	4		T180	1		T116	1
all_values[5]	auto[0]	auto[0]	auto[1]	63	1			T180	3		T32	1		T181	2
all_values[5]	auto[0]	auto[1]	auto[0]	28	1			T255	1		T288	2		T289	2
all_values[5]	auto[0]	auto[1]	auto[1]	60	1			T180	1		T32	1		T181	1
all_values[5]	auto[1]	auto[0]	auto[1]	69	1			T180	3		T32	2		T181	4
all_values[5]	auto[1]	auto[1]	auto[1]	73	1			T32	3		T116	2		T255	2
all_values[6]	auto[0]	auto[0]	auto[0]	30	1			T182	1		T180	1		T116	2
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T182	1		T32	2		T181	2
all_values[6]	auto[0]	auto[1]	auto[0]	24	1			T182	1		T180	5		T32	1
all_values[6]	auto[0]	auto[1]	auto[1]	65	1			T180	1		T32	1		T181	2
all_values[6]	auto[1]	auto[0]	auto[1]	79	1			T182	1		T32	1		T181	1
all_values[6]	auto[1]	auto[1]	auto[1]	58	1			T180	1		T32	2		T181	1
all_values[7]	auto[0]	auto[0]	auto[0]	28	1			T289	1		T127	2		T290	1
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T180	2		T32	1		T181	2
all_values[7]	auto[0]	auto[1]	auto[0]	19	1			T32	1		T181	2		T255	1
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T182	2		T180	3		T32	1
all_values[7]	auto[1]	auto[0]	auto[1]	80	1			T182	1		T180	2		T32	3
all_values[7]	auto[1]	auto[1]	auto[1]	69	1			T182	1		T180	1		T32	1
all_values[8]	auto[0]	auto[0]	auto[0]	33	1			T182	3		T116	1		T289	2
all_values[8]	auto[0]	auto[0]	auto[1]	62	1			T180	2		T32	3		T181	1
all_values[8]	auto[0]	auto[1]	auto[0]	22	1			T182	1		T181	1		T255	1
all_values[8]	auto[0]	auto[1]	auto[1]	78	1			T180	3		T32	1		T181	1
all_values[8]	auto[1]	auto[0]	auto[1]	78	1			T180	2		T181	1		T116	3
all_values[8]	auto[1]	auto[1]	auto[1]	63	1			T180	1		T32	3		T181	3
all_values[9]	auto[0]	auto[0]	auto[0]	33	1			T181	2		T127	1		T291	1
all_values[9]	auto[0]	auto[0]	auto[1]	69	1			T182	1		T180	2		T32	4
all_values[9]	auto[0]	auto[1]	auto[0]	25	1			T181	1		T255	2		T289	1
all_values[9]	auto[0]	auto[1]	auto[1]	71	1			T182	2		T180	4		T181	3
all_values[9]	auto[1]	auto[0]	auto[1]	73	1			T182	1		T180	1		T32	2
all_values[9]	auto[1]	auto[1]	auto[1]	65	1			T180	1		T32	1		T116	1
all_values[10]	auto[0]	auto[0]	auto[0]	32	1			T181	1		T125	1		T127	2
all_values[10]	auto[0]	auto[0]	auto[1]	67	1			T182	2		T180	1		T32	1
all_values[10]	auto[0]	auto[1]	auto[0]	25	1			T32	2		T181	1		T288	1
all_values[10]	auto[0]	auto[1]	auto[1]	78	1			T182	1		T180	3		T32	1
all_values[10]	auto[1]	auto[0]	auto[1]	68	1			T182	1		T180	1		T32	1
all_values[10]	auto[1]	auto[1]	auto[1]	66	1			T180	3		T32	2		T181	1
all_values[11]	auto[0]	auto[0]	auto[0]	38	1			T182	2		T180	1		T32	1
all_values[11]	auto[0]	auto[0]	auto[1]	64	1			T182	1		T180	2		T32	1
all_values[11]	auto[0]	auto[1]	auto[0]	18	1			T32	1		T255	1		T127	1
all_values[11]	auto[0]	auto[1]	auto[1]	77	1			T180	3		T32	1		T181	2
all_values[11]	auto[1]	auto[0]	auto[1]	75	1			T182	1		T180	1		T32	1
all_values[11]	auto[1]	auto[1]	auto[1]	64	1			T180	1		T32	2		T181	1
all_values[12]	auto[0]	auto[0]	auto[0]	31	1			T180	1		T289	1		T285	1
all_values[12]	auto[0]	auto[0]	auto[1]	78	1			T182	1		T180	3		T32	1
all_values[12]	auto[0]	auto[1]	auto[0]	16	1			T285	2		T126	1		T292	1
all_values[12]	auto[0]	auto[1]	auto[1]	78	1			T180	1		T32	3		T116	1
all_values[12]	auto[1]	auto[0]	auto[1]	79	1			T182	3		T180	3		T181	3
all_values[12]	auto[1]	auto[1]	auto[1]	54	1			T32	3		T181	2		T116	1
all_values[13]	auto[0]	auto[0]	auto[0]	41	1			T180	1		T289	2		T284	1
all_values[13]	auto[0]	auto[0]	auto[1]	71	1			T182	2		T180	2		T32	4
all_values[13]	auto[0]	auto[1]	auto[0]	21	1			T181	1		T289	2		T284	1
all_values[13]	auto[0]	auto[1]	auto[1]	75	1			T180	2		T32	1		T181	1
all_values[13]	auto[1]	auto[0]	auto[1]	57	1			T182	2		T181	1		T116	1
all_values[13]	auto[1]	auto[1]	auto[1]	71	1			T180	3		T32	2		T181	1
all_values[14]	auto[0]	auto[0]	auto[0]	33	1			T180	3		T181	1		T288	1
all_values[14]	auto[0]	auto[0]	auto[1]	67	1			T181	1		T116	1		T255	2
all_values[14]	auto[0]	auto[1]	auto[0]	31	1			T180	3		T32	1		T181	1
all_values[14]	auto[0]	auto[1]	auto[1]	64	1			T182	2		T180	1		T32	2
all_values[14]	auto[1]	auto[0]	auto[1]	74	1			T182	1		T180	1		T32	2
all_values[14]	auto[1]	auto[1]	auto[1]	67	1			T182	1		T32	2		T116	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal