Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	681578	1			T1	3		T2	2		T3	2
all_values[1]	681578	1			T1	3		T2	2		T3	2
all_values[2]	681578	1			T1	3		T2	2		T3	2
all_values[3]	681578	1			T1	3		T2	2		T3	2
all_values[4]	681578	1			T1	3		T2	2		T3	2
all_values[5]	681578	1			T1	3		T2	2		T3	2
all_values[6]	681578	1			T1	3		T2	2		T3	2
all_values[7]	681578	1			T1	3		T2	2		T3	2
all_values[8]	681578	1			T1	3		T2	2		T3	2
all_values[9]	681578	1			T1	3		T2	2		T3	2
all_values[10]	681578	1			T1	3		T2	2		T3	2
all_values[11]	681578	1			T1	3		T2	2		T3	2
all_values[12]	681578	1			T1	3		T2	2		T3	2
all_values[13]	681578	1			T1	3		T2	2		T3	2
all_values[14]	681578	1			T1	3		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8404116

1

T1

39

T2

26

T3

26

auto[1]

1819554

1

T1

6

T2

4

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9314916

1

T1

45

T2

30

T3

30

auto[1]

908754

1

T17

162221

T33

397160

T111

163171

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99842	1			T1	1		T7	2		T8	106
all_values[0]	auto[0]	auto[1]	6160	1			T17	937		T33	2148		T111	72
all_values[0]	auto[1]	auto[0]	526353	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	49223	1			T17	10002		T33	24330		T111	5451
all_values[1]	auto[0]	auto[0]	620255	1			T1	3		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	60942	1			T17	10934		T33	26472		T111	11256
all_values[1]	auto[1]	auto[0]	227	1			T245	2		T246	1		T247	1
all_values[1]	auto[1]	auto[1]	154	1			T17	6		T33	5		T111	5
all_values[2]	auto[0]	auto[0]	620289	1			T1	3		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	60948	1			T17	10936		T33	26473		T111	11255
all_values[2]	auto[1]	auto[0]	193	1			T54	1		T50	1		T210	2
all_values[2]	auto[1]	auto[1]	148	1			T17	4		T33	4		T111	6
all_values[3]	auto[0]	auto[0]	620858	1			T1	3		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	60548	1			T17	10561		T33	26469		T111	11254
all_values[3]	auto[1]	auto[1]	172	1			T17	1		T33	9		T111	6
all_values[4]	auto[0]	auto[0]	620486	1			T1	3		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	60941	1			T17	10934		T33	26471		T111	11255
all_values[4]	auto[1]	auto[0]	13	1			T22	2		T150	1		T227	1
all_values[4]	auto[1]	auto[1]	138	1			T17	5		T33	6		T111	6
all_values[5]	auto[0]	auto[0]	620500	1			T1	3		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	60914	1			T17	10940		T33	26473		T111	11256
all_values[5]	auto[1]	auto[1]	164	1			T17	1		T33	5		T111	4
all_values[6]	auto[0]	auto[0]	620497	1			T1	3		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	60907	1			T17	10936		T33	26469		T111	11254
all_values[6]	auto[1]	auto[1]	174	1			T17	4		T33	7		T111	7
all_values[7]	auto[0]	auto[0]	595789	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	59000	1			T17	10025		T33	26138		T111	10779
all_values[7]	auto[1]	auto[0]	25077	1			T1	1		T32	1		T17	132
all_values[7]	auto[1]	auto[1]	1712	1			T17	540		T33	339		T111	482
all_values[8]	auto[0]	auto[0]	620483	1			T1	3		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	60921	1			T17	10932		T33	26471		T111	11256
all_values[8]	auto[1]	auto[1]	174	1			T17	9		T33	7		T111	4
all_values[9]	auto[0]	auto[0]	140816	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	4870	1			T17	1305		T33	1719		T111	782
all_values[9]	auto[1]	auto[0]	479669	1			T1	1		T6	1		T7	1
all_values[9]	auto[1]	auto[1]	56223	1			T17	9636		T33	24758		T111	10478
all_values[10]	auto[0]	auto[0]	620502	1			T1	3		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	60947	1			T17	10935		T33	26476		T111	11256
all_values[10]	auto[1]	auto[1]	129	1			T17	4		T33	1		T111	5
all_values[11]	auto[0]	auto[0]	2280	1			T1	1		T7	2		T8	2
all_values[11]	auto[0]	auto[1]	244	1			T17	19		T33	14		T111	22
all_values[11]	auto[1]	auto[0]	618590	1			T1	2		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	60464	1			T17	10546		T33	26464		T111	11239
all_values[12]	auto[0]	auto[0]	620786	1			T1	3		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	60582	1			T17	10560		T33	26475		T111	11257
all_values[12]	auto[1]	auto[0]	65	1			T54	1		T50	1		T67	1
all_values[12]	auto[1]	auto[1]	145	1			T17	3		T33	3		T111	4
all_values[13]	auto[0]	auto[0]	620487	1			T1	3		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	60925	1			T17	10936		T33	26472		T111	11258
all_values[13]	auto[1]	auto[1]	166	1			T17	5		T33	6		T111	3
all_values[14]	auto[0]	auto[0]	620859	1			T1	3		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	60538	1			T17	10560		T33	26473		T111	11257
all_values[14]	auto[1]	auto[1]	181	1			T17	5		T33	3		T111	2