Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	681578	1			T1	3		T2	2		T3	2
all_pins[1]	681578	1			T1	3		T2	2		T3	2
all_pins[2]	681578	1			T1	3		T2	2		T3	2
all_pins[3]	681578	1			T1	3		T2	2		T3	2
all_pins[4]	681578	1			T1	3		T2	2		T3	2
all_pins[5]	681578	1			T1	3		T2	2		T3	2
all_pins[6]	681578	1			T1	3		T2	2		T3	2
all_pins[7]	681578	1			T1	3		T2	2		T3	2
all_pins[8]	681578	1			T1	3		T2	2		T3	2
all_pins[9]	681578	1			T1	3		T2	2		T3	2
all_pins[10]	681578	1			T1	3		T2	2		T3	2
all_pins[11]	681578	1			T1	3		T2	2		T3	2
all_pins[12]	681578	1			T1	3		T2	2		T3	2
all_pins[13]	681578	1			T1	3		T2	2		T3	2
all_pins[14]	681578	1			T1	3		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8409854	1			T1	39		T2	26		T3	26
values[0x1]	1813816	1			T1	6		T2	4		T3	4
transitions[0x0=>0x1]	1813217	1			T1	6		T2	4		T3	4
transitions[0x1=>0x0]	1811916	1			T1	5		T2	3		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	109351	1			T1	1		T7	2		T8	106
all_pins[0]	values[0x1]	572227	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	571925	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	85	1			T33	5		T111	1		T253	4
all_pins[1]	values[0x0]	681191	1			T1	3		T2	2		T3	2
all_pins[1]	values[0x1]	387	1			T33	5		T111	3		T245	2
all_pins[1]	transitions[0x0=>0x1]	364	1			T33	5		T111	2		T245	2
all_pins[1]	transitions[0x1=>0x0]	104	1			T17	2		T54	1		T111	4
all_pins[2]	values[0x0]	681451	1			T1	3		T2	2		T3	2
all_pins[2]	values[0x1]	127	1			T17	2		T54	1		T111	5
all_pins[2]	transitions[0x0=>0x1]	107	1			T17	2		T54	1		T111	5
all_pins[2]	transitions[0x1=>0x0]	57	1			T33	7		T111	2		T112	3
all_pins[3]	values[0x0]	681501	1			T1	3		T2	2		T3	2
all_pins[3]	values[0x1]	77	1			T33	7		T111	2		T209	1
all_pins[3]	transitions[0x0=>0x1]	57	1			T33	5		T111	2		T209	1
all_pins[3]	transitions[0x1=>0x0]	63	1			T17	2		T22	2		T33	1
all_pins[4]	values[0x0]	681495	1			T1	3		T2	2		T3	2
all_pins[4]	values[0x1]	83	1			T17	2		T22	2		T33	3
all_pins[4]	transitions[0x0=>0x1]	71	1			T17	2		T22	2		T33	1
all_pins[4]	transitions[0x1=>0x0]	66	1			T33	1		T111	1		T254	3
all_pins[5]	values[0x0]	681500	1			T1	3		T2	2		T3	2
all_pins[5]	values[0x1]	78	1			T33	3		T111	1		T254	4
all_pins[5]	transitions[0x0=>0x1]	60	1			T33	2		T111	1		T254	4
all_pins[5]	transitions[0x1=>0x0]	77	1			T17	3		T33	3		T111	5
all_pins[6]	values[0x0]	681483	1			T1	3		T2	2		T3	2
all_pins[6]	values[0x1]	95	1			T17	3		T33	4		T111	5
all_pins[6]	transitions[0x0=>0x1]	76	1			T17	3		T33	2		T111	4
all_pins[6]	transitions[0x1=>0x0]	29299	1			T1	1		T32	1		T17	772
all_pins[7]	values[0x0]	652260	1			T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	29318	1			T1	1		T32	1		T17	772
all_pins[7]	transitions[0x0=>0x1]	29304	1			T1	1		T32	1		T17	772
all_pins[7]	transitions[0x1=>0x0]	66	1			T17	7		T33	2		T254	2
all_pins[8]	values[0x0]	681498	1			T1	3		T2	2		T3	2
all_pins[8]	values[0x1]	80	1			T17	7		T33	2		T111	1
all_pins[8]	transitions[0x0=>0x1]	53	1			T17	6		T33	2		T209	2
all_pins[8]	transitions[0x1=>0x0]	535814	1			T1	1		T6	1		T7	1
all_pins[9]	values[0x0]	145737	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	535841	1			T1	1		T6	1		T7	1
all_pins[9]	transitions[0x0=>0x1]	535823	1			T1	1		T6	1		T7	1
all_pins[9]	transitions[0x1=>0x0]	55	1			T17	1		T111	3		T254	3
all_pins[10]	values[0x0]	681505	1			T1	3		T2	2		T3	2
all_pins[10]	values[0x1]	73	1			T17	1		T111	3		T254	5
all_pins[10]	transitions[0x0=>0x1]	48	1			T111	1		T254	4		T112	1
all_pins[10]	transitions[0x1=>0x0]	675099	1			T1	2		T2	2		T3	2
all_pins[11]	values[0x0]	6454	1			T1	1		T7	2		T8	2
all_pins[11]	values[0x1]	675124	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	675087	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	103	1			T17	2		T50	1		T111	1
all_pins[12]	values[0x0]	681438	1			T1	3		T2	2		T3	2
all_pins[12]	values[0x1]	140	1			T17	3		T54	1		T50	1
all_pins[12]	transitions[0x0=>0x1]	125	1			T17	3		T54	1		T50	1
all_pins[12]	transitions[0x1=>0x0]	67	1			T17	4		T33	1		T111	1
all_pins[13]	values[0x0]	681496	1			T1	3		T2	2		T3	2
all_pins[13]	values[0x1]	82	1			T17	4		T33	2		T111	1
all_pins[13]	transitions[0x0=>0x1]	60	1			T17	4		T33	1		T111	1
all_pins[13]	transitions[0x1=>0x0]	62	1			T17	1		T111	2		T209	3
all_pins[14]	values[0x0]	681494	1			T1	3		T2	2		T3	2
all_pins[14]	values[0x1]	84	1			T17	1		T33	1		T111	2
all_pins[14]	transitions[0x0=>0x1]	57	1			T17	1		T33	1		T209	2
all_pins[14]	transitions[0x1=>0x0]	570899	1			T1	1		T2	1		T3	1