Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	347	1			T17	11		T33	11		T111	11
all_values[1]	347	1			T17	11		T33	11		T111	11
all_values[2]	347	1			T17	11		T33	11		T111	11
all_values[3]	347	1			T17	11		T33	11		T111	11
all_values[4]	347	1			T17	11		T33	11		T111	11
all_values[5]	347	1			T17	11		T33	11		T111	11
all_values[6]	347	1			T17	11		T33	11		T111	11
all_values[7]	347	1			T17	11		T33	11		T111	11
all_values[8]	347	1			T17	11		T33	11		T111	11
all_values[9]	347	1			T17	11		T33	11		T111	11
all_values[10]	347	1			T17	11		T33	11		T111	11
all_values[11]	347	1			T17	11		T33	11		T111	11
all_values[12]	347	1			T17	11		T33	11		T111	11
all_values[13]	347	1			T17	11		T33	11		T111	11
all_values[14]	347	1			T17	11		T33	11		T111	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2881

1

T17

102

T33

85

T111

73

auto[1]

2324

1

T17

63

T33

80

T111

92

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

831

1

T17

34

T33

10

T111

12

auto[1]

4374

1

T17

131

T33

155

T111

153

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3056

1

T17

100

T33

99

T111

98

auto[1]

2149

1

T17

65

T33

66

T111

67

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	16	1			T17	2		T254	1		T114	1
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T17	3		T33	5		T111	1
all_values[0]	auto[0]	auto[1]	auto[0]	17	1			T111	6		T254	1		T255	2
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T17	4		T33	1		T111	2
all_values[0]	auto[1]	auto[0]	auto[1]	96	1			T17	1		T33	5		T111	1
all_values[0]	auto[1]	auto[1]	auto[1]	55	1			T17	1		T111	1		T209	1
all_values[1]	auto[0]	auto[0]	auto[0]	31	1			T17	1		T112	1		T256	1
all_values[1]	auto[0]	auto[0]	auto[1]	66	1			T17	2		T33	2		T111	1
all_values[1]	auto[0]	auto[1]	auto[0]	18	1			T33	1		T216	5		T256	1
all_values[1]	auto[0]	auto[1]	auto[1]	78	1			T17	2		T33	3		T111	5
all_values[1]	auto[1]	auto[0]	auto[1]	84	1			T17	6		T33	1		T111	2
all_values[1]	auto[1]	auto[1]	auto[1]	70	1			T33	4		T111	3		T209	2
all_values[2]	auto[0]	auto[0]	auto[0]	35	1			T17	1		T33	1		T112	1
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T17	5		T33	2		T111	4
all_values[2]	auto[0]	auto[1]	auto[0]	16	1			T254	1		T114	1		T255	1
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T17	1		T33	4		T111	1
all_values[2]	auto[1]	auto[0]	auto[1]	81	1			T17	3		T33	4		T111	1
all_values[2]	auto[1]	auto[1]	auto[1]	67	1			T17	1		T111	5		T209	2
all_values[3]	auto[0]	auto[0]	auto[0]	35	1			T17	2		T209	1		T112	1
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T17	3		T33	1		T111	3
all_values[3]	auto[0]	auto[1]	auto[0]	21	1			T17	5		T111	1		T254	1
all_values[3]	auto[0]	auto[1]	auto[1]	62	1			T33	3		T111	3		T209	1
all_values[3]	auto[1]	auto[0]	auto[1]	92	1			T33	4		T111	3		T254	4
all_values[3]	auto[1]	auto[1]	auto[1]	51	1			T17	1		T33	3		T111	1
all_values[4]	auto[0]	auto[0]	auto[0]	44	1			T17	2		T33	1		T209	1
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T17	3		T33	1		T111	2
all_values[4]	auto[0]	auto[1]	auto[0]	21	1			T209	1		T254	2		T256	2
all_values[4]	auto[0]	auto[1]	auto[1]	61	1			T17	1		T33	3		T111	3
all_values[4]	auto[1]	auto[0]	auto[1]	79	1			T17	2		T33	4		T111	3
all_values[4]	auto[1]	auto[1]	auto[1]	59	1			T17	3		T33	2		T111	3
all_values[5]	auto[0]	auto[0]	auto[0]	42	1			T209	1		T114	4		T257	2
all_values[5]	auto[0]	auto[0]	auto[1]	73	1			T17	5		T33	4		T111	7
all_values[5]	auto[0]	auto[1]	auto[0]	21	1			T111	1		T257	2		T258	1
all_values[5]	auto[0]	auto[1]	auto[1]	71	1			T17	3		T33	3		T209	1
all_values[5]	auto[1]	auto[0]	auto[1]	81	1			T17	3		T33	1		T111	3
all_values[5]	auto[1]	auto[1]	auto[1]	59	1			T33	3		T254	2		T112	3
all_values[6]	auto[0]	auto[0]	auto[0]	33	1			T17	1		T209	1		T112	3
all_values[6]	auto[0]	auto[0]	auto[1]	62	1			T17	3		T33	3		T111	1
all_values[6]	auto[0]	auto[1]	auto[0]	27	1			T33	2		T209	1		T254	2
all_values[6]	auto[0]	auto[1]	auto[1]	86	1			T17	2		T33	3		T111	4
all_values[6]	auto[1]	auto[0]	auto[1]	80	1			T17	1		T33	1		T111	1
all_values[6]	auto[1]	auto[1]	auto[1]	59	1			T17	4		T33	2		T111	5
all_values[7]	auto[0]	auto[0]	auto[0]	44	1			T17	4		T216	1		T259	2
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T17	2		T33	3		T111	3
all_values[7]	auto[0]	auto[1]	auto[0]	18	1			T33	1		T209	1		T254	1
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T17	2		T33	4		T111	3
all_values[7]	auto[1]	auto[0]	auto[1]	84	1			T17	3		T33	3		T111	1
all_values[7]	auto[1]	auto[1]	auto[1]	45	1			T111	4		T254	3		T112	2
all_values[8]	auto[0]	auto[0]	auto[0]	27	1			T113	2		T260	1		T261	1
all_values[8]	auto[0]	auto[0]	auto[1]	76	1			T17	2		T33	1		T111	6
all_values[8]	auto[0]	auto[1]	auto[0]	24	1			T111	1		T209	2		T112	1
all_values[8]	auto[0]	auto[1]	auto[1]	76	1			T17	3		T33	5		T111	1
all_values[8]	auto[1]	auto[0]	auto[1]	86	1			T17	4		T33	5		T111	2
all_values[8]	auto[1]	auto[1]	auto[1]	58	1			T17	2		T111	1		T209	1
all_values[9]	auto[0]	auto[0]	auto[0]	26	1			T33	1		T112	1		T216	1
all_values[9]	auto[0]	auto[0]	auto[1]	67	1			T17	5		T111	3		T209	1
all_values[9]	auto[0]	auto[1]	auto[0]	27	1			T111	1		T113	2		T255	1
all_values[9]	auto[0]	auto[1]	auto[1]	74	1			T33	4		T111	3		T254	3
all_values[9]	auto[1]	auto[0]	auto[1]	83	1			T17	2		T33	2		T111	1
all_values[9]	auto[1]	auto[1]	auto[1]	70	1			T17	4		T33	4		T111	3
all_values[10]	auto[0]	auto[0]	auto[0]	47	1			T17	1		T33	1		T209	3
all_values[10]	auto[0]	auto[0]	auto[1]	79	1			T17	1		T33	6		T111	5
all_values[10]	auto[0]	auto[1]	auto[0]	20	1			T17	1		T209	1		T254	1
all_values[10]	auto[0]	auto[1]	auto[1]	72	1			T17	4		T33	3		T111	1
all_values[10]	auto[1]	auto[0]	auto[1]	66	1			T17	4		T33	1		T111	2
all_values[10]	auto[1]	auto[1]	auto[1]	63	1			T111	3		T254	4		T112	1
all_values[11]	auto[0]	auto[0]	auto[0]	33	1			T17	4		T254	1		T112	1
all_values[11]	auto[0]	auto[0]	auto[1]	74	1			T33	1		T111	2		T254	6
all_values[11]	auto[0]	auto[1]	auto[0]	30	1			T254	1		T112	4		T255	1
all_values[11]	auto[0]	auto[1]	auto[1]	71	1			T17	1		T33	4		T111	3
all_values[11]	auto[1]	auto[0]	auto[1]	77	1			T17	4		T111	3		T254	4
all_values[11]	auto[1]	auto[1]	auto[1]	62	1			T17	2		T33	6		T111	3
all_values[12]	auto[0]	auto[0]	auto[0]	32	1			T17	3		T209	1		T216	2
all_values[12]	auto[0]	auto[0]	auto[1]	74	1			T17	1		T33	5		T111	3
all_values[12]	auto[0]	auto[1]	auto[0]	16	1			T17	3		T209	1		T259	1
all_values[12]	auto[0]	auto[1]	auto[1]	80	1			T17	1		T33	3		T111	4
all_values[12]	auto[1]	auto[0]	auto[1]	79	1			T33	1		T209	1		T254	3
all_values[12]	auto[1]	auto[1]	auto[1]	66	1			T17	3		T33	2		T111	4
all_values[13]	auto[0]	auto[0]	auto[0]	29	1			T216	1		T259	3		T262	2
all_values[13]	auto[0]	auto[0]	auto[1]	72	1			T17	1		T33	5		T111	1
all_values[13]	auto[0]	auto[1]	auto[0]	25	1			T254	1		T259	1		T263	1
all_values[13]	auto[0]	auto[1]	auto[1]	77	1			T17	3		T111	6		T209	1
all_values[13]	auto[1]	auto[0]	auto[1]	87	1			T17	4		T33	4		T111	3
all_values[13]	auto[1]	auto[1]	auto[1]	57	1			T17	3		T33	2		T111	1
all_values[14]	auto[0]	auto[0]	auto[0]	39	1			T17	4		T33	2		T111	1
all_values[14]	auto[0]	auto[0]	auto[1]	80	1			T17	2		T33	3		T111	2
all_values[14]	auto[0]	auto[1]	auto[0]	17	1			T111	1		T209	1		T254	1
all_values[14]	auto[0]	auto[1]	auto[1]	58	1			T17	1		T33	4		T111	3
all_values[14]	auto[1]	auto[0]	auto[1]	79	1			T17	2		T33	1		T111	2
all_values[14]	auto[1]	auto[1]	auto[1]	74	1			T17	2		T33	1		T111	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal