Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	702313	1			T1	1		T2	2		T3	4
all_values[1]	702313	1			T1	1		T2	2		T3	4
all_values[2]	702313	1			T1	1		T2	2		T3	4
all_values[3]	702313	1			T1	1		T2	2		T3	4
all_values[4]	702313	1			T1	1		T2	2		T3	4
all_values[5]	702313	1			T1	1		T2	2		T3	4
all_values[6]	702313	1			T1	1		T2	2		T3	4
all_values[7]	702313	1			T1	1		T2	2		T3	4
all_values[8]	702313	1			T1	1		T2	2		T3	4
all_values[9]	702313	1			T1	1		T2	2		T3	4
all_values[10]	702313	1			T1	1		T2	2		T3	4
all_values[11]	702313	1			T1	1		T2	2		T3	4
all_values[12]	702313	1			T1	1		T2	2		T3	4
all_values[13]	702313	1			T1	1		T2	2		T3	4
all_values[14]	702313	1			T1	1		T2	2		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8687776

1

T1

15

T2

30

T3

57

auto[1]

1846919

1

T3

3

T4

116

T6

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9674097

1

T1

15

T2

30

T3

60

auto[1]

860598

1

T138

90582

T124

76943

T181

67

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99489	1			T1	1		T2	2		T3	3
all_values[0]	auto[0]	auto[1]	6778	1			T138	1539		T124	131		T139	773
all_values[0]	auto[1]	auto[0]	545420	1			T3	1		T4	58		T6	2
all_values[0]	auto[1]	auto[1]	50626	1			T138	4500		T124	5788		T181	4
all_values[1]	auto[0]	auto[0]	644177	1			T1	1		T2	2		T3	4
all_values[1]	auto[0]	auto[1]	57621	1			T138	6028		T124	5910		T181	5
all_values[1]	auto[1]	auto[0]	322	1			T28	1		T290	7		T291	1
all_values[1]	auto[1]	auto[1]	193	1			T138	12		T124	9		T181	1
all_values[2]	auto[0]	auto[0]	644295	1			T1	1		T2	2		T3	4
all_values[2]	auto[0]	auto[1]	57663	1			T138	6033		T124	5917		T181	4
all_values[2]	auto[1]	auto[0]	193	1			T74	1		T78	2		T67	1
all_values[2]	auto[1]	auto[1]	162	1			T138	7		T124	2		T181	2
all_values[3]	auto[0]	auto[0]	643848	1			T1	1		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	58272	1			T138	6031		T124	5916		T181	3
all_values[3]	auto[1]	auto[1]	193	1			T138	8		T124	3		T181	3
all_values[4]	auto[0]	auto[0]	650522	1			T1	1		T2	2		T3	4
all_values[4]	auto[0]	auto[1]	51624	1			T138	6031		T181	4		T127	659
all_values[4]	auto[1]	auto[0]	19	1			T45	1		T284	1		T292	1
all_values[4]	auto[1]	auto[1]	148	1			T138	6		T181	1		T127	1
all_values[5]	auto[0]	auto[0]	643826	1			T1	1		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	58314	1			T138	6034		T124	5915		T181	2
all_values[5]	auto[1]	auto[1]	173	1			T138	6		T124	3		T181	2
all_values[6]	auto[0]	auto[0]	643832	1			T1	1		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	58295	1			T138	6032		T124	5916		T181	4
all_values[6]	auto[1]	auto[1]	186	1			T138	8		T124	2		T181	1
all_values[7]	auto[0]	auto[0]	617147	1			T1	1		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	55506	1			T138	5587		T124	5485		T181	6
all_values[7]	auto[1]	auto[0]	26685	1			T3	1		T6	1		T29	1
all_values[7]	auto[1]	auto[1]	2975	1			T138	453		T124	434		T127	158
all_values[8]	auto[0]	auto[0]	643863	1			T1	1		T2	2		T3	4
all_values[8]	auto[0]	auto[1]	58273	1			T138	6027		T124	5917		T127	660
all_values[8]	auto[1]	auto[1]	177	1			T138	10		T124	2		T139	8
all_values[9]	auto[0]	auto[0]	167356	1			T1	1		T2	2		T3	4
all_values[9]	auto[0]	auto[1]	15916	1			T138	3065		T124	958		T127	623
all_values[9]	auto[1]	auto[0]	476495	1			T6	1		T29	1		T49	1
all_values[9]	auto[1]	auto[1]	42546	1			T138	2975		T124	4961		T127	38
all_values[10]	auto[0]	auto[0]	643840	1			T1	1		T2	2		T3	4
all_values[10]	auto[0]	auto[1]	58324	1			T138	6032		T124	5918		T181	3
all_values[10]	auto[1]	auto[1]	149	1			T138	6		T124	1		T181	3
all_values[11]	auto[0]	auto[0]	2314	1			T1	1		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	315	1			T138	29		T127	6		T139	28
all_values[11]	auto[1]	auto[0]	647452	1			T3	1		T4	58		T6	2
all_values[11]	auto[1]	auto[1]	52232	1			T138	6009		T181	4		T127	653
all_values[12]	auto[0]	auto[0]	644194	1			T1	1		T2	2		T3	4
all_values[12]	auto[0]	auto[1]	57897	1			T138	6031		T124	5916		T181	4
all_values[12]	auto[1]	auto[0]	62	1			T67	1		T72	1		T73	1
all_values[12]	auto[1]	auto[1]	160	1			T138	9		T124	1		T181	1
all_values[13]	auto[0]	auto[0]	644238	1			T1	1		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	57888	1			T138	6029		T124	5919		T181	2
all_values[13]	auto[1]	auto[1]	187	1			T138	9		T181	3		T127	3
all_values[14]	auto[0]	auto[0]	644508	1			T1	1		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	57641	1			T138	6023		T124	5917		T181	2
all_values[14]	auto[1]	auto[1]	164	1			T138	13		T124	2		T181	3