Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	702313	1			T1	1		T2	2		T3	4
all_pins[1]	702313	1			T1	1		T2	2		T3	4
all_pins[2]	702313	1			T1	1		T2	2		T3	4
all_pins[3]	702313	1			T1	1		T2	2		T3	4
all_pins[4]	702313	1			T1	1		T2	2		T3	4
all_pins[5]	702313	1			T1	1		T2	2		T3	4
all_pins[6]	702313	1			T1	1		T2	2		T3	4
all_pins[7]	702313	1			T1	1		T2	2		T3	4
all_pins[8]	702313	1			T1	1		T2	2		T3	4
all_pins[9]	702313	1			T1	1		T2	2		T3	4
all_pins[10]	702313	1			T1	1		T2	2		T3	4
all_pins[11]	702313	1			T1	1		T2	2		T3	4
all_pins[12]	702313	1			T1	1		T2	2		T3	4
all_pins[13]	702313	1			T1	1		T2	2		T3	4
all_pins[14]	702313	1			T1	1		T2	2		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8693286	1			T1	15		T2	30		T3	57
values[0x1]	1841409	1			T3	3		T4	116		T6	6
transitions[0x0=>0x1]	1840657	1			T3	3		T4	116		T6	6
transitions[0x1=>0x0]	1839345	1			T3	2		T4	115		T6	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	109568	1			T1	1		T2	2		T3	3
all_pins[0]	values[0x1]	592745	1			T3	1		T4	58		T6	2
all_pins[0]	transitions[0x0=>0x1]	592333	1			T3	1		T4	58		T6	2
all_pins[0]	transitions[0x1=>0x0]	75	1			T138	4		T139	5		T297	2
all_pins[1]	values[0x0]	701826	1			T1	1		T2	2		T3	4
all_pins[1]	values[0x1]	487	1			T28	1		T290	8		T291	2
all_pins[1]	transitions[0x0=>0x1]	458	1			T28	1		T290	8		T291	2
all_pins[1]	transitions[0x1=>0x0]	102	1			T74	1		T208	1		T298	1
all_pins[2]	values[0x0]	702182	1			T1	1		T2	2		T3	4
all_pins[2]	values[0x1]	131	1			T74	1		T208	1		T298	1
all_pins[2]	transitions[0x0=>0x1]	112	1			T74	1		T208	1		T298	1
all_pins[2]	transitions[0x1=>0x0]	98	1			T138	3		T124	2		T181	3
all_pins[3]	values[0x0]	702196	1			T1	1		T2	2		T3	4
all_pins[3]	values[0x1]	117	1			T138	4		T124	2		T181	3
all_pins[3]	transitions[0x0=>0x1]	96	1			T138	4		T124	2		T181	2
all_pins[3]	transitions[0x1=>0x0]	66	1			T45	1		T284	1		T292	1
all_pins[4]	values[0x0]	702226	1			T1	1		T2	2		T3	4
all_pins[4]	values[0x1]	87	1			T45	1		T284	1		T292	1
all_pins[4]	transitions[0x0=>0x1]	81	1			T45	1		T284	1		T292	1
all_pins[4]	transitions[0x1=>0x0]	88	1			T138	5		T124	2		T181	2
all_pins[5]	values[0x0]	702219	1			T1	1		T2	2		T3	4
all_pins[5]	values[0x1]	94	1			T138	5		T124	2		T181	2
all_pins[5]	transitions[0x0=>0x1]	67	1			T138	3		T124	2		T181	2
all_pins[5]	transitions[0x1=>0x0]	82	1			T138	3		T181	1		T139	6
all_pins[6]	values[0x0]	702204	1			T1	1		T2	2		T3	4
all_pins[6]	values[0x1]	109	1			T138	5		T181	1		T139	7
all_pins[6]	transitions[0x0=>0x1]	73	1			T138	4		T181	1		T139	5
all_pins[6]	transitions[0x1=>0x0]	32272	1			T3	1		T6	1		T29	1
all_pins[7]	values[0x0]	670005	1			T1	1		T2	2		T3	3
all_pins[7]	values[0x1]	32308	1			T3	1		T6	1		T29	1
all_pins[7]	transitions[0x0=>0x1]	32282	1			T3	1		T6	1		T29	1
all_pins[7]	transitions[0x1=>0x0]	64	1			T138	5		T124	2		T139	2
all_pins[8]	values[0x0]	702223	1			T1	1		T2	2		T3	4
all_pins[8]	values[0x1]	90	1			T138	5		T124	2		T139	2
all_pins[8]	transitions[0x0=>0x1]	63	1			T138	4		T124	2		T139	1
all_pins[8]	transitions[0x1=>0x0]	518936	1			T6	1		T29	1		T49	1
all_pins[9]	values[0x0]	183350	1			T1	1		T2	2		T3	4
all_pins[9]	values[0x1]	518963	1			T6	1		T29	1		T49	1
all_pins[9]	transitions[0x0=>0x1]	518944	1			T6	1		T29	1		T49	1
all_pins[9]	transitions[0x1=>0x0]	54	1			T138	3		T181	1		T127	2
all_pins[10]	values[0x0]	702240	1			T1	1		T2	2		T3	4
all_pins[10]	values[0x1]	73	1			T138	3		T181	1		T127	2
all_pins[10]	transitions[0x0=>0x1]	56	1			T138	3		T181	1		T127	1
all_pins[10]	transitions[0x1=>0x0]	695853	1			T3	1		T4	58		T6	2
all_pins[11]	values[0x0]	6443	1			T1	1		T2	2		T3	3
all_pins[11]	values[0x1]	695870	1			T3	1		T4	58		T6	2
all_pins[11]	transitions[0x0=>0x1]	695833	1			T3	1		T4	58		T6	2
all_pins[11]	transitions[0x1=>0x0]	111	1			T67	1		T72	1		T73	1
all_pins[12]	values[0x0]	702165	1			T1	1		T2	2		T3	4
all_pins[12]	values[0x1]	148	1			T67	1		T72	1		T73	1
all_pins[12]	transitions[0x0=>0x1]	128	1			T67	1		T72	1		T73	1
all_pins[12]	transitions[0x1=>0x0]	72	1			T138	6		T127	1		T139	2
all_pins[13]	values[0x0]	702221	1			T1	1		T2	2		T3	4
all_pins[13]	values[0x1]	92	1			T138	6		T181	1		T127	1
all_pins[13]	transitions[0x0=>0x1]	71	1			T138	3		T181	1		T127	1
all_pins[13]	transitions[0x1=>0x0]	74	1			T138	5		T124	1		T139	2
all_pins[14]	values[0x0]	702218	1			T1	1		T2	2		T3	4
all_pins[14]	values[0x1]	95	1			T138	8		T124	1		T139	3
all_pins[14]	transitions[0x0=>0x1]	60	1			T138	7		T139	3		T297	1
all_pins[14]	transitions[0x1=>0x0]	591398	1			T4	57		T6	1		T7	1