Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	394	1			T138	21		T124	4		T181	4
all_values[1]	394	1			T138	21		T124	4		T181	4
all_values[2]	394	1			T138	21		T124	4		T181	4
all_values[3]	394	1			T138	21		T124	4		T181	4
all_values[4]	394	1			T138	21		T124	4		T181	4
all_values[5]	394	1			T138	21		T124	4		T181	4
all_values[6]	394	1			T138	21		T124	4		T181	4
all_values[7]	394	1			T138	21		T124	4		T181	4
all_values[8]	394	1			T138	21		T124	4		T181	4
all_values[9]	394	1			T138	21		T124	4		T181	4
all_values[10]	394	1			T138	21		T124	4		T181	4
all_values[11]	394	1			T138	21		T124	4		T181	4
all_values[12]	394	1			T138	21		T124	4		T181	4
all_values[13]	394	1			T138	21		T124	4		T181	4
all_values[14]	394	1			T138	21		T124	4		T181	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3144

1

T138

169

T124

28

T181

23

auto[1]

2766

1

T138

146

T124

32

T181

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

919

1

T138

18

T124

12

T181

19

auto[1]

4991

1

T138

297

T124

48

T181

41

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3464

1

T138

197

T124

38

T181

42

auto[1]

2446

1

T138

118

T124

22

T181

18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	45	1			T138	1		T127	2		T299	1
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T138	6		T139	5		T297	1
all_values[0]	auto[0]	auto[1]	auto[0]	22	1			T181	2		T127	2		T141	2
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T138	8		T124	1		T181	1
all_values[0]	auto[1]	auto[0]	auto[1]	77	1			T138	5		T139	5		T140	3
all_values[0]	auto[1]	auto[1]	auto[1]	84	1			T138	1		T124	3		T181	1
all_values[1]	auto[0]	auto[0]	auto[0]	40	1			T127	4		T140	1		T299	1
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T138	3		T124	2		T181	3
all_values[1]	auto[0]	auto[1]	auto[0]	19	1			T297	1		T144	1		T300	1
all_values[1]	auto[0]	auto[1]	auto[1]	72	1			T138	6		T139	5		T140	1
all_values[1]	auto[1]	auto[0]	auto[1]	89	1			T138	9		T124	2		T139	5
all_values[1]	auto[1]	auto[1]	auto[1]	89	1			T138	3		T181	1		T139	5
all_values[2]	auto[0]	auto[0]	auto[0]	30	1			T127	2		T141	1		T143	1
all_values[2]	auto[0]	auto[0]	auto[1]	99	1			T138	9		T124	2		T139	3
all_values[2]	auto[0]	auto[1]	auto[0]	18	1			T127	2		T139	1		T299	1
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T138	5		T181	2		T139	4
all_values[2]	auto[1]	auto[0]	auto[1]	91	1			T138	4		T181	1		T139	4
all_values[2]	auto[1]	auto[1]	auto[1]	71	1			T138	3		T124	2		T181	1
all_values[3]	auto[0]	auto[0]	auto[0]	44	1			T138	1		T139	3		T143	2
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T138	5		T124	1		T127	2
all_values[3]	auto[0]	auto[1]	auto[0]	22	1			T297	2		T141	1		T301	1
all_values[3]	auto[0]	auto[1]	auto[1]	88	1			T138	8		T124	1		T181	2
all_values[3]	auto[1]	auto[0]	auto[1]	74	1			T138	1		T124	1		T127	1
all_values[3]	auto[1]	auto[1]	auto[1]	90	1			T138	6		T124	1		T181	2
all_values[4]	auto[0]	auto[0]	auto[0]	47	1			T138	3		T124	2		T127	1
all_values[4]	auto[0]	auto[0]	auto[1]	90	1			T138	9		T127	2		T139	2
all_values[4]	auto[0]	auto[1]	auto[0]	31	1			T124	2		T181	1		T139	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T138	3		T181	2		T139	5
all_values[4]	auto[1]	auto[0]	auto[1]	89	1			T138	3		T139	5		T140	1
all_values[4]	auto[1]	auto[1]	auto[1]	59	1			T138	3		T181	1		T127	1
all_values[5]	auto[0]	auto[0]	auto[0]	26	1			T124	1		T181	1		T140	1
all_values[5]	auto[0]	auto[0]	auto[1]	98	1			T138	6		T127	1		T139	6
all_values[5]	auto[0]	auto[1]	auto[0]	19	1			T181	1		T139	1		T140	2
all_values[5]	auto[0]	auto[1]	auto[1]	89	1			T138	8		T124	2		T181	1
all_values[5]	auto[1]	auto[0]	auto[1]	75	1			T138	5		T124	1		T127	2
all_values[5]	auto[1]	auto[1]	auto[1]	87	1			T138	2		T181	1		T139	6
all_values[6]	auto[0]	auto[0]	auto[0]	25	1			T124	1		T140	1		T141	2
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T138	4		T124	1		T127	1
all_values[6]	auto[0]	auto[1]	auto[0]	24	1			T181	1		T142	2		T26	1
all_values[6]	auto[0]	auto[1]	auto[1]	96	1			T138	9		T181	2		T127	1
all_values[6]	auto[1]	auto[0]	auto[1]	93	1			T138	5		T124	2		T127	1
all_values[6]	auto[1]	auto[1]	auto[1]	88	1			T138	3		T181	1		T127	1
all_values[7]	auto[0]	auto[0]	auto[0]	38	1			T139	1		T143	1		T302	1
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T138	7		T181	3		T127	1
all_values[7]	auto[0]	auto[1]	auto[0]	12	1			T297	1		T26	1		T300	1
all_values[7]	auto[0]	auto[1]	auto[1]	84	1			T138	5		T124	3		T139	7
all_values[7]	auto[1]	auto[0]	auto[1]	85	1			T138	5		T127	3		T139	5
all_values[7]	auto[1]	auto[1]	auto[1]	91	1			T138	4		T124	1		T181	1
all_values[8]	auto[0]	auto[0]	auto[0]	51	1			T138	3		T181	2		T127	1
all_values[8]	auto[0]	auto[0]	auto[1]	81	1			T138	3		T127	1		T139	3
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T181	2		T297	1		T142	1
all_values[8]	auto[0]	auto[1]	auto[1]	82	1			T138	7		T124	2		T127	1
all_values[8]	auto[1]	auto[0]	auto[1]	84	1			T138	2		T139	4		T140	1
all_values[8]	auto[1]	auto[1]	auto[1]	71	1			T138	6		T124	2		T127	1
all_values[9]	auto[0]	auto[0]	auto[0]	39	1			T181	2		T139	1		T141	2
all_values[9]	auto[0]	auto[0]	auto[1]	101	1			T138	6		T124	2		T139	4
all_values[9]	auto[0]	auto[1]	auto[0]	28	1			T181	2		T139	1		T142	1
all_values[9]	auto[0]	auto[1]	auto[1]	63	1			T138	6		T127	1		T139	6
all_values[9]	auto[1]	auto[0]	auto[1]	83	1			T138	5		T127	3		T139	3
all_values[9]	auto[1]	auto[1]	auto[1]	80	1			T138	4		T124	2		T139	3
all_values[10]	auto[0]	auto[0]	auto[0]	37	1			T138	2		T127	1		T143	1
all_values[10]	auto[0]	auto[0]	auto[1]	101	1			T138	8		T124	3		T181	1
all_values[10]	auto[0]	auto[1]	auto[0]	19	1			T139	2		T297	1		T140	1
all_values[10]	auto[0]	auto[1]	auto[1]	88	1			T138	5		T127	1		T139	4
all_values[10]	auto[1]	auto[0]	auto[1]	88	1			T138	3		T124	1		T181	2
all_values[10]	auto[1]	auto[1]	auto[1]	61	1			T138	3		T181	1		T127	1
all_values[11]	auto[0]	auto[0]	auto[0]	41	1			T138	2		T124	2		T181	1
all_values[11]	auto[0]	auto[0]	auto[1]	82	1			T138	11		T139	5		T297	2
all_values[11]	auto[0]	auto[1]	auto[0]	26	1			T124	2		T181	1		T127	1
all_values[11]	auto[0]	auto[1]	auto[1]	82	1			T138	2		T181	1		T127	1
all_values[11]	auto[1]	auto[0]	auto[1]	83	1			T138	2		T139	2		T140	3
all_values[11]	auto[1]	auto[1]	auto[1]	80	1			T138	4		T181	1		T127	1
all_values[12]	auto[0]	auto[0]	auto[0]	39	1			T299	1		T141	2		T303	2
all_values[12]	auto[0]	auto[0]	auto[1]	71	1			T138	6		T181	2		T139	4
all_values[12]	auto[0]	auto[1]	auto[0]	33	1			T124	2		T181	1		T139	2
all_values[12]	auto[0]	auto[1]	auto[1]	91	1			T138	6		T124	1		T127	2
all_values[12]	auto[1]	auto[0]	auto[1]	80	1			T138	3		T127	2		T139	3
all_values[12]	auto[1]	auto[1]	auto[1]	80	1			T138	6		T124	1		T181	1
all_values[13]	auto[0]	auto[0]	auto[0]	29	1			T138	2		T127	1		T304	2
all_values[13]	auto[0]	auto[0]	auto[1]	92	1			T138	4		T181	1		T127	1
all_values[13]	auto[0]	auto[1]	auto[0]	23	1			T181	1		T139	1		T297	1
all_values[13]	auto[0]	auto[1]	auto[1]	77	1			T138	6		T124	2		T127	1
all_values[13]	auto[1]	auto[0]	auto[1]	99	1			T138	7		T124	2		T181	1
all_values[13]	auto[1]	auto[1]	auto[1]	74	1			T138	2		T181	1		T127	1
all_values[14]	auto[0]	auto[0]	auto[0]	42	1			T138	3		T127	2		T139	1
all_values[14]	auto[0]	auto[0]	auto[1]	91	1			T138	2		T124	2		T181	2
all_values[14]	auto[0]	auto[1]	auto[0]	25	1			T138	1		T181	1		T127	2
all_values[14]	auto[0]	auto[1]	auto[1]	85	1			T138	6		T124	1		T139	4
all_values[14]	auto[1]	auto[0]	auto[1]	77	1			T138	4		T181	1		T139	2
all_values[14]	auto[1]	auto[1]	auto[1]	74	1			T138	5		T124	1		T139	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal