Unified Coverage Report :: Cond split page

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 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T79,T217,T218
1	0	Covered	T215,T222,T223

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T79,T217,T218
0	1	0	Covered	T215,T222,T223
1	0	0	Covered	T79,T217,T218

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T215,T222,T223
0	1	0	Covered	T214,T216,T221
1	0	0	Not Covered

 LINE       3390
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3391
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3392
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3393
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3394
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3395
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_STATUS_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       3396
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_RDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       3397
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FDATA_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3398
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_FIFO_CTRL_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3399
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       3400
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_CONFIG_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       3401
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_FIFO_STATUS_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       3402
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_FIFO_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3403
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_OVRD_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3404
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_VAL_OFFSET)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3405
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING0_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3406
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING1_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3407
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING2_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       3408
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING3_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       3409
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMING4_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3410
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TIMEOUT_CTRL_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3411
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ID_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3412
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       3413
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TXDATA_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       3414
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_TIMEOUT_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3415
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_TIMEOUT_CTRL_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       3416
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_NACK_COUNT_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3417
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_ACK_CTRL_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3418
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_ACQ_FIFO_NEXT_DATA_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3419
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_HOST_NACK_HANDLER_TIMEOUT_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       3420
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_CONTROLLER_EVENTS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       3421
 EXPRESSION (reg_addr == i2c_reg_pkg::I2C_TARGET_EVENTS_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       3424
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       3424
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       3428
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T214,T215,T216

 LINE       3428
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b0011 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b0111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
32 (addr_hit[31] & ((\|(4'...	Covered	T1,T4,T5
31 (addr_hit[30] & ((\|(4'...	Covered	T4,T5,T9
30 (addr_hit[29] & ((\|(4'...	Covered	T4,T5,T9
29 (addr_hit[28] & ((\|(4'...	Covered	T1,T4,T5
28 (addr_hit[27] & ((\|(4'...	Covered	T1,T4,T5
27 (addr_hit[26] & ((\|(4'...	Covered	T1,T4,T5
26 (addr_hit[25] & ((\|(4'...	Covered	T4,T5,T9
25 (addr_hit[24] & ((\|(4'...	Covered	T4,T5,T9
24 (addr_hit[23] & ((\|(4'...	Covered	T4,T5,T9
23 (addr_hit[22] & ((\|(4'...	Covered	T4,T5,T7
22 (addr_hit[21] & ((\|(4'...	Covered	T1,T4,T5
21 (addr_hit[20] & ((\|(4'...	Covered	T4,T5,T9
20 (addr_hit[19] & ((\|(4'...	Covered	T4,T5,T9
19 (addr_hit[18] & ((\|(4'...	Covered	T1,T4,T5
18 (addr_hit[17] & ((\|(4'...	Covered	T4,T5,T9
17 (addr_hit[16] & ((\|(4'...	Covered	T4,T5,T9
16 (addr_hit[15] & ((\|(4'...	Covered	T4,T5,T9
15 (addr_hit[14] & ((\|(4'...	Covered	T1,T4,T5
14 (addr_hit[13] & ((\|(4'...	Covered	T1,T4,T5
13 (addr_hit[12] & ((\|(4'...	Covered	T1,T4,T5
12 (addr_hit[11] & ((\|(4'...	Covered	T1,T2,T4
11 (addr_hit[10] & ((\|(4'...	Covered	T1,T4,T5
10 (addr_hit[9] & ((\|(4'b...	Covered	T1,T4,T5
9 (addr_hit[8] & ((\|(4'b...	Covered	T1,T4,T5
8 (addr_hit[7] & ((\|(4'b...	Covered	T1,T4,T5
7 (addr_hit[6] & ((\|(4'b...	Covered	T1,T3,T4
6 (addr_hit[5] & ((\|(4'b...	Covered	T2,T3,T4
5 (addr_hit[4] & ((\|(4'b...	Covered	T1,T4,T5
4 (addr_hit[3] & ((\|(4'b...	Covered	T1,T4,T5
3 (addr_hit[2] & ((\|(4'b...	Covered	T1,T4,T5
2 (addr_hit[1] & ((\|(4'b...	Covered	T1,T4,T5
1 (addr_hit[0] & ((\|(4'b...	Covered	T1,T2,T3

 LINE       3428
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       3428
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T4

 LINE       3428
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       3428
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T50
1	1	Covered	T1,T2,T4

 LINE       3428
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T50,T48
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T50,T74
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T9

 LINE       3428
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T9

 LINE       3428
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T5,T9

 LINE       3428
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T9

 LINE       3428
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T9

 LINE       3428
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T7

 LINE       3428
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T9

 LINE       3428
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T5,T9

 LINE       3428
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T66
1	1	Covered	T4,T5,T9

 LINE       3428
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T4,T5

 LINE       3428
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       3428
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T9

 LINE       3428
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       3464
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T214,T216,T224
1	1	1	Covered	T1,T2,T3

 LINE       3481
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T214,T216,T221
1	1	1	Covered	T1,T2,T3

 LINE       3512
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T214,T216,T221
1	1	1	Covered	T138,T124,T181

 LINE       3543
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T223,T224,T225
1	1	1	Covered	T103,T104,T105

 LINE       3546
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T214,T221,T224
1	1	1	Covered	T1,T2,T3

 LINE       3561
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T114,T226,T227
1	1	1	Covered	T2,T3,T4

 LINE       3562
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T226
1	1	1	Covered	T3,T4,T11

 LINE       3563
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T214,T216,T221
1	1	1	Covered	T2,T3,T4

 LINE       3576
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T214,T216,T221
1	1	1	Covered	T1,T2,T3

 LINE       3585
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T214,T215,T216
1	1	1	Covered	T3,T4,T5

 LINE       3590
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T216,T223,T228
1	1	1	Covered	T3,T4,T5

 LINE       3595
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T215,T114,T229
1	1	1	Covered	T2,T40,T41

 LINE       3596
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T223,T230,T229
1	1	1	Covered	T7,T8,T9

 LINE       3597
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T221,T224,T225
1	1	1	Covered	T1,T85,T106

 LINE       3604
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T222,T223,T231
1	1	1	Not Covered

 LINE       3605
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T214,T222,T221
1	1	1	Covered	T3,T4,T5

 LINE       3610
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T214,T221,T228
1	1	1	Covered	T3,T4,T5

 LINE       3615
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T214,T222,T221
1	1	1	Covered	T3,T4,T5

 LINE       3620
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T216,T221,T224
1	1	1	Covered	T3,T4,T5

 LINE       3625
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T216,T221,T228
1	1	1	Covered	T3,T4,T5

 LINE       3630
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T214,T215,T216
1	1	1	Covered	T3,T4,T5