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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.40 97.30 89.91 97.22 72.62 94.40 98.44 89.89


Total test records in report: 1853
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T1761 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2649442861 Aug 21 08:48:23 AM UTC 24 Aug 21 08:48:24 AM UTC 24 44804349 ps
T303 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.3339286888 Aug 21 08:48:22 AM UTC 24 Aug 21 08:48:24 AM UTC 24 28593383 ps
T1762 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.1555754740 Aug 21 08:48:19 AM UTC 24 Aug 21 08:48:25 AM UTC 24 285314237 ps
T1763 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2297114852 Aug 21 08:48:22 AM UTC 24 Aug 21 08:48:25 AM UTC 24 41518430 ps
T1764 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2294179154 Aug 21 08:48:23 AM UTC 24 Aug 21 08:48:25 AM UTC 24 422298554 ps
T229 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.3820447708 Aug 21 08:48:22 AM UTC 24 Aug 21 08:48:25 AM UTC 24 166821604 ps
T1765 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4084752350 Aug 21 08:48:24 AM UTC 24 Aug 21 08:48:26 AM UTC 24 108683785 ps
T1766 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.2203614259 Aug 21 08:48:24 AM UTC 24 Aug 21 08:48:26 AM UTC 24 34712136 ps
T1767 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.4046579480 Aug 21 08:48:24 AM UTC 24 Aug 21 08:48:26 AM UTC 24 25574212 ps
T1768 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.1121720822 Aug 21 08:48:22 AM UTC 24 Aug 21 08:48:26 AM UTC 24 73207889 ps
T1769 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.298184698 Aug 21 08:48:25 AM UTC 24 Aug 21 08:48:27 AM UTC 24 28036163 ps
T1770 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.4241679054 Aug 21 08:48:25 AM UTC 24 Aug 21 08:48:27 AM UTC 24 47460726 ps
T1771 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2223771732 Aug 21 08:48:25 AM UTC 24 Aug 21 08:48:28 AM UTC 24 40710826 ps
T226 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2286659679 Aug 21 08:48:24 AM UTC 24 Aug 21 08:48:28 AM UTC 24 286857425 ps
T1772 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.413565134 Aug 21 08:48:26 AM UTC 24 Aug 21 08:48:28 AM UTC 24 55794938 ps
T1773 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.4110259060 Aug 21 08:48:25 AM UTC 24 Aug 21 08:48:28 AM UTC 24 90893688 ps
T1774 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.1279857522 Aug 21 08:48:25 AM UTC 24 Aug 21 08:48:28 AM UTC 24 141230896 ps
T1775 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.3913216582 Aug 21 08:48:27 AM UTC 24 Aug 21 08:48:28 AM UTC 24 19142294 ps
T1776 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.2576504007 Aug 21 08:48:27 AM UTC 24 Aug 21 08:48:29 AM UTC 24 16283041 ps
T1777 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.784173902 Aug 21 08:48:26 AM UTC 24 Aug 21 08:48:29 AM UTC 24 36569665 ps
T1778 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.796437582 Aug 21 08:48:26 AM UTC 24 Aug 21 08:48:29 AM UTC 24 58335663 ps
T1779 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.3155257073 Aug 21 08:48:27 AM UTC 24 Aug 21 08:48:30 AM UTC 24 163934675 ps
T1780 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3813613956 Aug 21 08:48:28 AM UTC 24 Aug 21 08:48:30 AM UTC 24 41132369 ps
T1781 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3651591080 Aug 21 08:48:28 AM UTC 24 Aug 21 08:48:30 AM UTC 24 36210046 ps
T1782 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.881726692 Aug 21 08:48:25 AM UTC 24 Aug 21 08:48:31 AM UTC 24 1407251005 ps
T1783 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.1809303584 Aug 21 08:48:26 AM UTC 24 Aug 21 08:48:31 AM UTC 24 155047628 ps
T1784 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.2586856822 Aug 21 08:48:29 AM UTC 24 Aug 21 08:48:31 AM UTC 24 25691912 ps
T1785 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.650013943 Aug 21 08:48:29 AM UTC 24 Aug 21 08:48:31 AM UTC 24 38416448 ps
T1786 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.3619450119 Aug 21 08:48:28 AM UTC 24 Aug 21 08:48:32 AM UTC 24 505061457 ps
T182 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1207812423 Aug 21 08:48:29 AM UTC 24 Aug 21 08:48:32 AM UTC 24 100712250 ps
T232 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3212213044 Aug 21 08:48:29 AM UTC 24 Aug 21 08:48:32 AM UTC 24 256103933 ps
T1787 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1760038415 Aug 21 08:48:30 AM UTC 24 Aug 21 08:48:33 AM UTC 24 48683923 ps
T1788 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.938915812 Aug 21 08:48:31 AM UTC 24 Aug 21 08:48:33 AM UTC 24 16794579 ps
T1789 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.1189055209 Aug 21 08:48:29 AM UTC 24 Aug 21 08:48:33 AM UTC 24 258063006 ps
T1790 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1684646585 Aug 21 08:48:31 AM UTC 24 Aug 21 08:48:33 AM UTC 24 147927656 ps
T1791 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.557254309 Aug 21 08:48:29 AM UTC 24 Aug 21 08:48:33 AM UTC 24 140330218 ps
T1792 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3883590776 Aug 21 08:48:31 AM UTC 24 Aug 21 08:48:33 AM UTC 24 648423495 ps
T227 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.291480812 Aug 21 08:48:31 AM UTC 24 Aug 21 08:48:34 AM UTC 24 420369019 ps
T1793 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.2704325301 Aug 21 08:48:32 AM UTC 24 Aug 21 08:48:34 AM UTC 24 21453667 ps
T1794 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.4000555061 Aug 21 08:48:32 AM UTC 24 Aug 21 08:48:34 AM UTC 24 21699092 ps
T1795 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.2685237038 Aug 21 08:48:31 AM UTC 24 Aug 21 08:48:34 AM UTC 24 330178033 ps
T1796 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1065375725 Aug 21 08:48:32 AM UTC 24 Aug 21 08:48:34 AM UTC 24 61216879 ps
T1797 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2009585314 Aug 21 08:48:32 AM UTC 24 Aug 21 08:48:35 AM UTC 24 29702310 ps
T1798 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.780029656 Aug 21 08:48:33 AM UTC 24 Aug 21 08:48:36 AM UTC 24 45148621 ps
T251 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1169482576 Aug 21 08:48:33 AM UTC 24 Aug 21 08:48:36 AM UTC 24 20206347 ps
T1799 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.3584352128 Aug 21 08:48:34 AM UTC 24 Aug 21 08:48:36 AM UTC 24 40976846 ps
T1800 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.2178428889 Aug 21 08:48:34 AM UTC 24 Aug 21 08:48:36 AM UTC 24 70708527 ps
T1801 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.2328072582 Aug 21 08:48:32 AM UTC 24 Aug 21 08:48:36 AM UTC 24 152099234 ps
T1802 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1027367403 Aug 21 08:48:33 AM UTC 24 Aug 21 08:48:36 AM UTC 24 54745417 ps
T1803 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1098327219 Aug 21 08:48:34 AM UTC 24 Aug 21 08:48:36 AM UTC 24 56766192 ps
T1804 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.4112292974 Aug 21 08:48:32 AM UTC 24 Aug 21 08:48:37 AM UTC 24 475336562 ps
T1805 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.1782031367 Aug 21 08:48:34 AM UTC 24 Aug 21 08:48:37 AM UTC 24 248723123 ps
T293 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.2269341684 Aug 21 08:48:34 AM UTC 24 Aug 21 08:48:37 AM UTC 24 777617510 ps
T1806 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.479695288 Aug 21 08:48:35 AM UTC 24 Aug 21 08:48:37 AM UTC 24 48681607 ps
T1807 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.3219729446 Aug 21 08:48:35 AM UTC 24 Aug 21 08:48:37 AM UTC 24 59758222 ps
T1808 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.4143001417 Aug 21 08:48:35 AM UTC 24 Aug 21 08:48:37 AM UTC 24 189372543 ps
T1809 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.654531190 Aug 21 08:48:35 AM UTC 24 Aug 21 08:48:38 AM UTC 24 79256324 ps
T1810 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.915581134 Aug 21 08:48:35 AM UTC 24 Aug 21 08:48:38 AM UTC 24 49313555 ps
T1811 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3687927926 Aug 21 08:48:35 AM UTC 24 Aug 21 08:48:38 AM UTC 24 41346701 ps
T1812 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.1999037695 Aug 21 08:48:36 AM UTC 24 Aug 21 08:48:38 AM UTC 24 34423048 ps
T1813 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.2502076133 Aug 21 08:48:35 AM UTC 24 Aug 21 08:48:38 AM UTC 24 63750226 ps
T234 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.2819086681 Aug 21 08:48:35 AM UTC 24 Aug 21 08:48:38 AM UTC 24 252333265 ps
T1814 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.412818118 Aug 21 08:48:37 AM UTC 24 Aug 21 08:48:39 AM UTC 24 67208577 ps
T1815 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.16796157 Aug 21 08:48:38 AM UTC 24 Aug 21 08:48:40 AM UTC 24 21001686 ps
T1816 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.3051036927 Aug 21 08:48:38 AM UTC 24 Aug 21 08:48:40 AM UTC 24 32654194 ps
T1817 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.1884996847 Aug 21 08:48:38 AM UTC 24 Aug 21 08:48:40 AM UTC 24 24288778 ps
T1818 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1177997395 Aug 21 08:48:38 AM UTC 24 Aug 21 08:48:40 AM UTC 24 31730476 ps
T1819 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.1976274000 Aug 21 08:48:36 AM UTC 24 Aug 21 08:48:40 AM UTC 24 853023165 ps
T1820 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3823465902 Aug 21 08:48:38 AM UTC 24 Aug 21 08:48:40 AM UTC 24 70474967 ps
T1821 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.4014752767 Aug 21 08:48:36 AM UTC 24 Aug 21 08:48:40 AM UTC 24 129207093 ps
T1822 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.731173956 Aug 21 08:48:38 AM UTC 24 Aug 21 08:48:40 AM UTC 24 84216067 ps
T1823 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1438004051 Aug 21 08:48:38 AM UTC 24 Aug 21 08:48:40 AM UTC 24 53164750 ps
T1824 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.3566930713 Aug 21 08:48:38 AM UTC 24 Aug 21 08:48:41 AM UTC 24 65666443 ps
T1825 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.2300457087 Aug 21 08:48:39 AM UTC 24 Aug 21 08:48:41 AM UTC 24 41373686 ps
T1826 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.1114690029 Aug 21 08:48:39 AM UTC 24 Aug 21 08:48:41 AM UTC 24 18745385 ps
T1827 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.2723282587 Aug 21 08:48:39 AM UTC 24 Aug 21 08:48:41 AM UTC 24 17807176 ps
T1828 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.2761745612 Aug 21 08:48:40 AM UTC 24 Aug 21 08:48:41 AM UTC 24 18187860 ps
T231 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.2160914140 Aug 21 08:48:38 AM UTC 24 Aug 21 08:48:41 AM UTC 24 1170870288 ps
T1829 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.2323085110 Aug 21 08:48:39 AM UTC 24 Aug 21 08:48:41 AM UTC 24 27408344 ps
T1830 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.3758515168 Aug 21 08:48:39 AM UTC 24 Aug 21 08:48:41 AM UTC 24 15972769 ps
T1831 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.394884076 Aug 21 08:48:40 AM UTC 24 Aug 21 08:48:41 AM UTC 24 47719515 ps
T1832 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.4127993604 Aug 21 08:48:40 AM UTC 24 Aug 21 08:48:42 AM UTC 24 36848681 ps
T1833 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.2928155122 Aug 21 08:48:41 AM UTC 24 Aug 21 08:48:43 AM UTC 24 31411613 ps
T1834 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.2440957797 Aug 21 08:48:41 AM UTC 24 Aug 21 08:48:43 AM UTC 24 17651440 ps
T1835 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.2933688868 Aug 21 08:48:41 AM UTC 24 Aug 21 08:48:43 AM UTC 24 51076801 ps
T1836 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.2096038345 Aug 21 08:48:41 AM UTC 24 Aug 21 08:48:43 AM UTC 24 38971760 ps
T1837 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.2611608330 Aug 21 08:48:41 AM UTC 24 Aug 21 08:48:43 AM UTC 24 57911301 ps
T1838 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.141893464 Aug 21 08:48:41 AM UTC 24 Aug 21 08:48:43 AM UTC 24 15576383 ps
T1839 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.1543990952 Aug 21 08:48:41 AM UTC 24 Aug 21 08:48:43 AM UTC 24 19445914 ps
T1840 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.2973735000 Aug 21 08:48:41 AM UTC 24 Aug 21 08:48:43 AM UTC 24 60636855 ps
T1841 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.1855131793 Aug 21 08:48:41 AM UTC 24 Aug 21 08:48:43 AM UTC 24 53311943 ps
T1842 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.1990916071 Aug 21 08:48:41 AM UTC 24 Aug 21 08:48:43 AM UTC 24 17086606 ps
T1843 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.1554868896 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:44 AM UTC 24 38314800 ps
T1844 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.1332686536 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:44 AM UTC 24 20128322 ps
T1845 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.2611275203 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:45 AM UTC 24 45159137 ps
T1846 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.637103119 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:45 AM UTC 24 21339405 ps
T1847 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.1909746484 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:45 AM UTC 24 49668135 ps
T1848 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.2471266814 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:45 AM UTC 24 16095580 ps
T1849 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.1005853940 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:45 AM UTC 24 26462325 ps
T1850 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.2325300425 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:45 AM UTC 24 20339242 ps
T1851 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.1938347294 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:45 AM UTC 24 17179844 ps
T1852 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.1938744169 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:45 AM UTC 24 18142261 ps
T1853 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.2422167473 Aug 21 08:48:43 AM UTC 24 Aug 21 08:48:45 AM UTC 24 123952720 ps

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_hrst.2198133163
Short name T9
Test name
Test status
Simulation time 246885498 ps
CPU time 1.88 seconds
Started Aug 21 08:22:05 AM UTC 24
Finished Aug 21 08:22:08 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2198133163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.i2c_target_hrst.2198133163
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.1388545357
Short name T11
Test name
Test status
Simulation time 990264301 ps
CPU time 7.77 seconds
Started Aug 21 08:22:07 AM UTC 24
Finished Aug 21 08:22:17 AM UTC 24
Peak memory 216852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1388545357 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1388545357
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.2227935101
Short name T55
Test name
Test status
Simulation time 1804786963 ps
CPU time 10.72 seconds
Started Aug 21 08:22:02 AM UTC 24
Finished Aug 21 08:22:15 AM UTC 24
Peak memory 227240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2227935101 -as
sert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2227935101
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_glitch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_stress_all.1142162232
Short name T138
Test name
Test status
Simulation time 66449714193 ps
CPU time 261.68 seconds
Started Aug 21 08:22:42 AM UTC 24
Finished Aug 21 08:27:08 AM UTC 24
Peak memory 884180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1142162232 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.1142162232
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1190405008
Short name T112
Test name
Test status
Simulation time 278078392 ps
CPU time 1.41 seconds
Started Aug 21 08:48:08 AM UTC 24
Finished Aug 21 08:48:11 AM UTC 24
Peak memory 214740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=1190405008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1190405008
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.3950184062
Short name T5
Test name
Test status
Simulation time 261284147 ps
CPU time 2 seconds
Started Aug 21 08:22:02 AM UTC 24
Finished Aug 21 08:22:06 AM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3950184062 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3950184062
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.4131708441
Short name T107
Test name
Test status
Simulation time 5230076883 ps
CPU time 58.75 seconds
Started Aug 21 08:22:13 AM UTC 24
Finished Aug 21 08:23:13 AM UTC 24
Peak memory 872644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4131708441 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.4131708441
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_nack_txstretch.3119740716
Short name T63
Test name
Test status
Simulation time 138950133 ps
CPU time 1.79 seconds
Started Aug 21 08:22:10 AM UTC 24
Finished Aug 21 08:22:14 AM UTC 24
Peak memory 232588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3119740716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_nack_txstretch.3119740716
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_override.1617080057
Short name T154
Test name
Test status
Simulation time 34415459 ps
CPU time 1 seconds
Started Aug 21 08:22:37 AM UTC 24
Finished Aug 21 08:22:40 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1617080057 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1617080057
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.629508747
Short name T79
Test name
Test status
Simulation time 161913629 ps
CPU time 0.87 seconds
Started Aug 21 08:22:11 AM UTC 24
Finished Aug 21 08:22:13 AM UTC 24
Peak memory 246676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=629508747 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.629508747
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.1066124696
Short name T51
Test name
Test status
Simulation time 9556770125 ps
CPU time 10.01 seconds
Started Aug 21 08:22:02 AM UTC 24
Finished Aug 21 08:22:14 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1066124696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_timeout.1066124696
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.1940170106
Short name T2
Test name
Test status
Simulation time 156696913 ps
CPU time 1.91 seconds
Started Aug 21 08:21:58 AM UTC 24
Finished Aug 21 08:22:01 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1940170106 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.1940170106
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.241423815
Short name T29
Test name
Test status
Simulation time 1090481870 ps
CPU time 5.26 seconds
Started Aug 21 08:22:00 AM UTC 24
Finished Aug 21 08:22:09 AM UTC 24
Peak memory 258088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=241423815 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.241423815
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull_addr.3886225556
Short name T52
Test name
Test status
Simulation time 1286286553 ps
CPU time 3.82 seconds
Started Aug 21 08:28:27 AM UTC 24
Finished Aug 21 08:28:32 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3886225556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_nack_acqfull_addr.3886225556
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.1032123241
Short name T73
Test name
Test status
Simulation time 549164155 ps
CPU time 4.03 seconds
Started Aug 21 08:22:36 AM UTC 24
Finished Aug 21 08:22:42 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1032123241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_nack_acqfull_addr.1032123241
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_stress_all.1857832650
Short name T26
Test name
Test status
Simulation time 24290679360 ps
CPU time 633.23 seconds
Started Aug 21 08:38:27 AM UTC 24
Finished Aug 21 08:49:07 AM UTC 24
Peak memory 1227040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1857832650 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.1857832650
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.1820690944
Short name T71
Test name
Test status
Simulation time 3540287258 ps
CPU time 5.93 seconds
Started Aug 21 08:22:30 AM UTC 24
Finished Aug 21 08:22:37 AM UTC 24
Peak memory 226960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1820690944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1820690944
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.917172753
Short name T113
Test name
Test status
Simulation time 227245895 ps
CPU time 1.7 seconds
Started Aug 21 08:48:08 AM UTC 24
Finished Aug 21 08:48:11 AM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=917172753 -asse
rt nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.917172753
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.3338701265
Short name T215
Test name
Test status
Simulation time 441986279 ps
CPU time 3.16 seconds
Started Aug 21 08:47:59 AM UTC 24
Finished Aug 21 08:48:03 AM UTC 24
Peak memory 215244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3338701265 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3338701265
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.4119662142
Short name T56
Test name
Test status
Simulation time 16252542274 ps
CPU time 21.39 seconds
Started Aug 21 08:22:02 AM UTC 24
Finished Aug 21 08:22:26 AM UTC 24
Peak memory 535060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=4119662142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.4119662142
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_error_intr.958376044
Short name T24
Test name
Test status
Simulation time 188181139 ps
CPU time 2.27 seconds
Started Aug 21 08:24:13 AM UTC 24
Finished Aug 21 08:24:17 AM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=958376044 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.958376044
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.2090486373
Short name T86
Test name
Test status
Simulation time 758019148 ps
CPU time 7.94 seconds
Started Aug 21 08:22:13 AM UTC 24
Finished Aug 21 08:22:22 AM UTC 24
Peak memory 216728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2090486373 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.2090486373
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_stress_all.3701789307
Short name T141
Test name
Test status
Simulation time 133980376250 ps
CPU time 210.31 seconds
Started Aug 21 08:45:06 AM UTC 24
Finished Aug 21 08:48:39 AM UTC 24
Peak memory 2087164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3701789307 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.3701789307
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull.1444232560
Short name T60
Test name
Test status
Simulation time 2391551240 ps
CPU time 4.13 seconds
Started Aug 21 08:26:36 AM UTC 24
Finished Aug 21 08:26:41 AM UTC 24
Peak memory 227156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1444232560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 13.i2c_target_nack_acqfull.1444232560
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.3932028807
Short name T233
Test name
Test status
Simulation time 101626161 ps
CPU time 3.12 seconds
Started Aug 21 08:48:17 AM UTC 24
Finished Aug 21 08:48:21 AM UTC 24
Peak memory 215276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3932028807 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3932028807
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.4156377848
Short name T284
Test name
Test status
Simulation time 364556322 ps
CPU time 16.66 seconds
Started Aug 21 08:24:02 AM UTC 24
Finished Aug 21 08:24:20 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4156377848 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.4156377848
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_stress_all.4045007266
Short name T127
Test name
Test status
Simulation time 10334959166 ps
CPU time 309.9 seconds
Started Aug 21 08:32:10 AM UTC 24
Finished Aug 21 08:37:24 AM UTC 24
Peak memory 1710340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4045007266 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.4045007266
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_alert_test.219121282
Short name T103
Test name
Test status
Simulation time 146531511 ps
CPU time 0.92 seconds
Started Aug 21 08:22:11 AM UTC 24
Finished Aug 21 08:22:13 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=219121282 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.219121282
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.3494839734
Short name T74
Test name
Test status
Simulation time 345615389 ps
CPU time 2.55 seconds
Started Aug 21 08:22:07 AM UTC 24
Finished Aug 21 08:22:11 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3494839734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.3494839734
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.3647080276
Short name T92
Test name
Test status
Simulation time 1139364961 ps
CPU time 11.49 seconds
Started Aug 21 08:38:27 AM UTC 24
Finished Aug 21 08:38:39 AM UTC 24
Peak memory 233632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3647080276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_targ
et_smoke.3647080276
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.4064381130
Short name T456
Test name
Test status
Simulation time 165040394 ps
CPU time 2.82 seconds
Started Aug 21 08:25:04 AM UTC 24
Finished Aug 21 08:25:08 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4064381130 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.4064381130
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.3214442121
Short name T44
Test name
Test status
Simulation time 393748239 ps
CPU time 16.24 seconds
Started Aug 21 08:22:48 AM UTC 24
Finished Aug 21 08:23:06 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3214442121 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3214442121
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.2275964903
Short name T1753
Test name
Test status
Simulation time 43175888 ps
CPU time 0.96 seconds
Started Aug 21 08:48:29 AM UTC 24
Finished Aug 21 08:48:31 AM UTC 24
Peak memory 214256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2275964903 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2275964903
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.3240745800
Short name T309
Test name
Test status
Simulation time 6800165889 ps
CPU time 55.73 seconds
Started Aug 21 08:35:24 AM UTC 24
Finished Aug 21 08:36:21 AM UTC 24
Peak memory 309432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3240745800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 30.i2c_target_stress_all.3240745800
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.2886970891
Short name T274
Test name
Test status
Simulation time 518878748 ps
CPU time 6.84 seconds
Started Aug 21 08:37:17 AM UTC 24
Finished Aug 21 08:37:25 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2886970891 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2886970891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_perf.1901379768
Short name T779
Test name
Test status
Simulation time 24810257585 ps
CPU time 364.35 seconds
Started Aug 21 08:24:12 AM UTC 24
Finished Aug 21 08:30:21 AM UTC 24
Peak memory 315528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1901379768 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1901379768
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.370117996
Short name T230
Test name
Test status
Simulation time 911896678 ps
CPU time 2.19 seconds
Started Aug 21 08:48:21 AM UTC 24
Finished Aug 21 08:48:24 AM UTC 24
Peak memory 215164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=370117996 -a
ssert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.370117996
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_mode_toggle.2864234256
Short name T288
Test name
Test status
Simulation time 343074148 ps
CPU time 6.44 seconds
Started Aug 21 08:30:41 AM UTC 24
Finished Aug 21 08:30:49 AM UTC 24
Peak memory 233612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2864234256 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.2864234256
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.1120601507
Short name T517
Test name
Test status
Simulation time 3767807926 ps
CPU time 201.87 seconds
Started Aug 21 08:22:39 AM UTC 24
Finished Aug 21 08:26:05 AM UTC 24
Peak memory 1093792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1120601507 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1120601507
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.4045745670
Short name T236
Test name
Test status
Simulation time 17377678 ps
CPU time 1.01 seconds
Started Aug 21 08:48:02 AM UTC 24
Finished Aug 21 08:48:04 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4045745670 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.4045745670
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_fmt.3767147968
Short name T269
Test name
Test status
Simulation time 136243510 ps
CPU time 1.65 seconds
Started Aug 21 08:28:05 AM UTC 24
Finished Aug 21 08:28:07 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3767147968 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fmt.3767147968
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.1574271240
Short name T169
Test name
Test status
Simulation time 1423887234 ps
CPU time 14.17 seconds
Started Aug 21 08:22:28 AM UTC 24
Finished Aug 21 08:22:44 AM UTC 24
Peak memory 233900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1574271240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stress_rd.1574271240
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_override.538819450
Short name T285
Test name
Test status
Simulation time 47047475 ps
CPU time 0.97 seconds
Started Aug 21 08:40:10 AM UTC 24
Finished Aug 21 08:40:12 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=538819450 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.538819450
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.3653582613
Short name T33
Test name
Test status
Simulation time 2309137862 ps
CPU time 8.65 seconds
Started Aug 21 08:23:39 AM UTC 24
Finished Aug 21 08:23:49 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3653582613 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3653582613
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2286659679
Short name T226
Test name
Test status
Simulation time 286857425 ps
CPU time 3.03 seconds
Started Aug 21 08:48:24 AM UTC 24
Finished Aug 21 08:48:28 AM UTC 24
Peak memory 215220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2286659679 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2286659679
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_acq.1225639035
Short name T238
Test name
Test status
Simulation time 310219316 ps
CPU time 2 seconds
Started Aug 21 08:28:15 AM UTC 24
Finished Aug 21 08:28:18 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1225639035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_acq.1225639035
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_perf.768961880
Short name T42
Test name
Test status
Simulation time 4019950549 ps
CPU time 5.39 seconds
Started Aug 21 08:28:06 AM UTC 24
Finished Aug 21 08:28:12 AM UTC 24
Peak memory 254280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=768961880 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.768961880
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.1367083373
Short name T144
Test name
Test status
Simulation time 36713063 ps
CPU time 1.03 seconds
Started Aug 21 08:48:05 AM UTC 24
Finished Aug 21 08:48:07 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1367083373 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1367083373
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.4221276279
Short name T7
Test name
Test status
Simulation time 832614336 ps
CPU time 0.95 seconds
Started Aug 21 08:22:05 AM UTC 24
Finished Aug 21 08:22:07 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4221276279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 0.i2c_target_fifo_reset_tx.4221276279
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.6790408
Short name T75
Test name
Test status
Simulation time 891112514 ps
CPU time 12.87 seconds
Started Aug 21 08:22:07 AM UTC 24
Finished Aug 21 08:22:22 AM UTC 24
Peak memory 216796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=6790408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_tx_stretch_ctrl.6790408
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.2811475411
Short name T174
Test name
Test status
Simulation time 1578691613 ps
CPU time 11.93 seconds
Started Aug 21 08:22:14 AM UTC 24
Finished Aug 21 08:22:28 AM UTC 24
Peak memory 233820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2811475411 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2811475411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.1607216537
Short name T296
Test name
Test status
Simulation time 30970685338 ps
CPU time 431.4 seconds
Started Aug 21 08:25:14 AM UTC 24
Finished Aug 21 08:32:30 AM UTC 24
Peak memory 4821156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1607216537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 10.i2c_target_stress_all.1607216537
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.398391775
Short name T312
Test name
Test status
Simulation time 530980347 ps
CPU time 2.13 seconds
Started Aug 21 08:25:58 AM UTC 24
Finished Aug 21 08:26:02 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=398391775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_fifo_reset_acq.398391775
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.1182000620
Short name T282
Test name
Test status
Simulation time 198796073 ps
CPU time 8.72 seconds
Started Aug 21 08:33:54 AM UTC 24
Finished Aug 21 08:34:04 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1182000620 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.1182000620
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.682648612
Short name T277
Test name
Test status
Simulation time 529148803 ps
CPU time 8.95 seconds
Started Aug 21 08:46:45 AM UTC 24
Finished Aug 21 08:46:56 AM UTC 24
Peak memory 216852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=682648612 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.682648612
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.1722123596
Short name T221
Test name
Test status
Simulation time 183836759 ps
CPU time 3.07 seconds
Started Aug 21 08:48:03 AM UTC 24
Finished Aug 21 08:48:08 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1722123596 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1722123596
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.2160914140
Short name T231
Test name
Test status
Simulation time 1170870288 ps
CPU time 2.52 seconds
Started Aug 21 08:48:38 AM UTC 24
Finished Aug 21 08:48:41 AM UTC 24
Peak memory 215160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2160914140 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2160914140
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.3679271456
Short name T25
Test name
Test status
Simulation time 517898803 ps
CPU time 2.75 seconds
Started Aug 21 08:32:09 AM UTC 24
Finished Aug 21 08:32:13 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3679271456 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3679271456
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.3776703684
Short name T36
Test name
Test status
Simulation time 307550475 ps
CPU time 2.56 seconds
Started Aug 21 08:41:25 AM UTC 24
Finished Aug 21 08:41:29 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3776703684 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3776703684
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1207812423
Short name T182
Test name
Test status
Simulation time 100712250 ps
CPU time 1.72 seconds
Started Aug 21 08:48:29 AM UTC 24
Finished Aug 21 08:48:32 AM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=120
7812423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_out
standing.1207812423
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_mode_toggle.1699555613
Short name T32
Test name
Test status
Simulation time 606405028 ps
CPU time 2.24 seconds
Started Aug 21 08:25:38 AM UTC 24
Finished Aug 21 08:25:42 AM UTC 24
Peak memory 231164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1699555613 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.1699555613
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_mode_toggle.2909420438
Short name T82
Test name
Test status
Simulation time 232458858 ps
CPU time 4.85 seconds
Started Aug 21 08:33:50 AM UTC 24
Finished Aug 21 08:33:56 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2909420438 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2909420438
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.2830093884
Short name T110
Test name
Test status
Simulation time 396835190 ps
CPU time 1.97 seconds
Started Aug 21 08:48:02 AM UTC 24
Finished Aug 21 08:48:05 AM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2830093884 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2830093884
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.1077073882
Short name T248
Test name
Test status
Simulation time 115866936 ps
CPU time 6.14 seconds
Started Aug 21 08:48:02 AM UTC 24
Finished Aug 21 08:48:09 AM UTC 24
Peak memory 215180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1077073882 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1077073882
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.3139986414
Short name T235
Test name
Test status
Simulation time 17537298 ps
CPU time 1.01 seconds
Started Aug 21 08:48:01 AM UTC 24
Finished Aug 21 08:48:03 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3139986414 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3139986414
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.561204928
Short name T216
Test name
Test status
Simulation time 30903805 ps
CPU time 2.05 seconds
Started Aug 21 08:48:03 AM UTC 24
Finished Aug 21 08:48:07 AM UTC 24
Peak memory 225540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=561204928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.561204928
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.1317858597
Short name T143
Test name
Test status
Simulation time 19180626 ps
CPU time 1.09 seconds
Started Aug 21 08:48:00 AM UTC 24
Finished Aug 21 08:48:02 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1317858597 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1317858597
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2565804093
Short name T252
Test name
Test status
Simulation time 105089109 ps
CPU time 1.29 seconds
Started Aug 21 08:48:02 AM UTC 24
Finished Aug 21 08:48:04 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=256
5804093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_outs
tanding.2565804093
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.3942622439
Short name T214
Test name
Test status
Simulation time 64398503 ps
CPU time 1.88 seconds
Started Aug 21 08:47:59 AM UTC 24
Finished Aug 21 08:48:02 AM UTC 24
Peak memory 214656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3942622439 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3942622439
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.1956389098
Short name T249
Test name
Test status
Simulation time 1453969952 ps
CPU time 5.68 seconds
Started Aug 21 08:48:06 AM UTC 24
Finished Aug 21 08:48:13 AM UTC 24
Peak memory 215180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1956389098 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1956389098
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.546189790
Short name T111
Test name
Test status
Simulation time 19465778 ps
CPU time 1.2 seconds
Started Aug 21 08:48:05 AM UTC 24
Finished Aug 21 08:48:07 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=546189790 -asse
rt nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.546189790
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.310535666
Short name T253
Test name
Test status
Simulation time 134376838 ps
CPU time 1.17 seconds
Started Aug 21 08:48:06 AM UTC 24
Finished Aug 21 08:48:08 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=310535666 -assert nop
ostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.310535666
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3895811618
Short name T254
Test name
Test status
Simulation time 93408431 ps
CPU time 1.28 seconds
Started Aug 21 08:48:08 AM UTC 24
Finished Aug 21 08:48:11 AM UTC 24
Peak memory 214600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=389
5811618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outs
tanding.3895811618
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.858610112
Short name T222
Test name
Test status
Simulation time 569237358 ps
CPU time 3.04 seconds
Started Aug 21 08:48:03 AM UTC 24
Finished Aug 21 08:48:08 AM UTC 24
Peak memory 215292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=858610112 -a
ssert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.858610112
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.796437582
Short name T1778
Test name
Test status
Simulation time 58335663 ps
CPU time 1.4 seconds
Started Aug 21 08:48:26 AM UTC 24
Finished Aug 21 08:48:29 AM UTC 24
Peak memory 214684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=796437582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.796437582
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.413565134
Short name T1772
Test name
Test status
Simulation time 55794938 ps
CPU time 0.9 seconds
Started Aug 21 08:48:26 AM UTC 24
Finished Aug 21 08:48:28 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=413565134 -assert nop
ostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.413565134
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.4241679054
Short name T1770
Test name
Test status
Simulation time 47460726 ps
CPU time 0.97 seconds
Started Aug 21 08:48:25 AM UTC 24
Finished Aug 21 08:48:27 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241679054 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.4241679054
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.784173902
Short name T1777
Test name
Test status
Simulation time 36569665 ps
CPU time 1.25 seconds
Started Aug 21 08:48:26 AM UTC 24
Finished Aug 21 08:48:29 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=784
173902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_outs
tanding.784173902
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.4110259060
Short name T1773
Test name
Test status
Simulation time 90893688 ps
CPU time 2.14 seconds
Started Aug 21 08:48:25 AM UTC 24
Finished Aug 21 08:48:28 AM UTC 24
Peak memory 215256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4110259060 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.4110259060
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.1279857522
Short name T1774
Test name
Test status
Simulation time 141230896 ps
CPU time 2.07 seconds
Started Aug 21 08:48:25 AM UTC 24
Finished Aug 21 08:48:28 AM UTC 24
Peak memory 215288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1279857522 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1279857522
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3651591080
Short name T1781
Test name
Test status
Simulation time 36210046 ps
CPU time 1.36 seconds
Started Aug 21 08:48:28 AM UTC 24
Finished Aug 21 08:48:30 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=3651591080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3651591080
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.3913216582
Short name T1775
Test name
Test status
Simulation time 19142294 ps
CPU time 0.93 seconds
Started Aug 21 08:48:27 AM UTC 24
Finished Aug 21 08:48:28 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3913216582 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3913216582
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.2576504007
Short name T1776
Test name
Test status
Simulation time 16283041 ps
CPU time 0.96 seconds
Started Aug 21 08:48:27 AM UTC 24
Finished Aug 21 08:48:29 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2576504007 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2576504007
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3813613956
Short name T1780
Test name
Test status
Simulation time 41132369 ps
CPU time 1.33 seconds
Started Aug 21 08:48:28 AM UTC 24
Finished Aug 21 08:48:30 AM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=381
3613956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_out
standing.3813613956
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.1809303584
Short name T1783
Test name
Test status
Simulation time 155047628 ps
CPU time 3.41 seconds
Started Aug 21 08:48:26 AM UTC 24
Finished Aug 21 08:48:31 AM UTC 24
Peak memory 215192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1809303584 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1809303584
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.3155257073
Short name T1779
Test name
Test status
Simulation time 163934675 ps
CPU time 2.04 seconds
Started Aug 21 08:48:27 AM UTC 24
Finished Aug 21 08:48:30 AM UTC 24
Peak memory 215384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3155257073 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3155257073
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.650013943
Short name T1785
Test name
Test status
Simulation time 38416448 ps
CPU time 1.14 seconds
Started Aug 21 08:48:29 AM UTC 24
Finished Aug 21 08:48:31 AM UTC 24
Peak memory 214744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=650013943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.650013943
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.2586856822
Short name T1784
Test name
Test status
Simulation time 25691912 ps
CPU time 1.06 seconds
Started Aug 21 08:48:29 AM UTC 24
Finished Aug 21 08:48:31 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2586856822 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2586856822
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.3619450119
Short name T1786
Test name
Test status
Simulation time 505061457 ps
CPU time 2.95 seconds
Started Aug 21 08:48:28 AM UTC 24
Finished Aug 21 08:48:32 AM UTC 24
Peak memory 215244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3619450119 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.3619450119
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.557254309
Short name T1791
Test name
Test status
Simulation time 140330218 ps
CPU time 2.79 seconds
Started Aug 21 08:48:29 AM UTC 24
Finished Aug 21 08:48:33 AM UTC 24
Peak memory 214852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=557254309 -a
ssert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.557254309
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1684646585
Short name T1790
Test name
Test status
Simulation time 147927656 ps
CPU time 1.18 seconds
Started Aug 21 08:48:31 AM UTC 24
Finished Aug 21 08:48:33 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=1684646585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1684646585
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.938915812
Short name T1788
Test name
Test status
Simulation time 16794579 ps
CPU time 1.04 seconds
Started Aug 21 08:48:31 AM UTC 24
Finished Aug 21 08:48:33 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=938915812 -assert nop
ostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.938915812
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1760038415
Short name T1787
Test name
Test status
Simulation time 48683923 ps
CPU time 1.07 seconds
Started Aug 21 08:48:30 AM UTC 24
Finished Aug 21 08:48:33 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1760038415 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1760038415
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3883590776
Short name T1792
Test name
Test status
Simulation time 648423495 ps
CPU time 1.38 seconds
Started Aug 21 08:48:31 AM UTC 24
Finished Aug 21 08:48:33 AM UTC 24
Peak memory 214720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=388
3590776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_out
standing.3883590776
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.1189055209
Short name T1789
Test name
Test status
Simulation time 258063006 ps
CPU time 2.52 seconds
Started Aug 21 08:48:29 AM UTC 24
Finished Aug 21 08:48:33 AM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1189055209 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1189055209
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3212213044
Short name T232
Test name
Test status
Simulation time 256103933 ps
CPU time 1.85 seconds
Started Aug 21 08:48:29 AM UTC 24
Finished Aug 21 08:48:32 AM UTC 24
Peak memory 214576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3212213044 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3212213044
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1065375725
Short name T1796
Test name
Test status
Simulation time 61216879 ps
CPU time 1.08 seconds
Started Aug 21 08:48:32 AM UTC 24
Finished Aug 21 08:48:34 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=1065375725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1065375725
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.2704325301
Short name T1793
Test name
Test status
Simulation time 21453667 ps
CPU time 1.11 seconds
Started Aug 21 08:48:32 AM UTC 24
Finished Aug 21 08:48:34 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2704325301 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2704325301
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.4000555061
Short name T1794
Test name
Test status
Simulation time 21699092 ps
CPU time 1.07 seconds
Started Aug 21 08:48:32 AM UTC 24
Finished Aug 21 08:48:34 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4000555061 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.4000555061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2009585314
Short name T1797
Test name
Test status
Simulation time 29702310 ps
CPU time 1.28 seconds
Started Aug 21 08:48:32 AM UTC 24
Finished Aug 21 08:48:35 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=200
9585314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_out
standing.2009585314
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.2685237038
Short name T1795
Test name
Test status
Simulation time 330178033 ps
CPU time 2.45 seconds
Started Aug 21 08:48:31 AM UTC 24
Finished Aug 21 08:48:34 AM UTC 24
Peak memory 215304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2685237038 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2685237038
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.291480812
Short name T227
Test name
Test status
Simulation time 420369019 ps
CPU time 2.04 seconds
Started Aug 21 08:48:31 AM UTC 24
Finished Aug 21 08:48:34 AM UTC 24
Peak memory 215304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=291480812 -a
ssert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.291480812
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1098327219
Short name T1803
Test name
Test status
Simulation time 56766192 ps
CPU time 1.44 seconds
Started Aug 21 08:48:34 AM UTC 24
Finished Aug 21 08:48:36 AM UTC 24
Peak memory 214748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=1098327219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1098327219
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1169482576
Short name T251
Test name
Test status
Simulation time 20206347 ps
CPU time 1.06 seconds
Started Aug 21 08:48:33 AM UTC 24
Finished Aug 21 08:48:36 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1169482576 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1169482576
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.780029656
Short name T1798
Test name
Test status
Simulation time 45148621 ps
CPU time 0.84 seconds
Started Aug 21 08:48:33 AM UTC 24
Finished Aug 21 08:48:36 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=780029656 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.780029656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1027367403
Short name T1802
Test name
Test status
Simulation time 54745417 ps
CPU time 1.38 seconds
Started Aug 21 08:48:33 AM UTC 24
Finished Aug 21 08:48:36 AM UTC 24
Peak memory 214760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=102
7367403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_out
standing.1027367403
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.4112292974
Short name T1804
Test name
Test status
Simulation time 475336562 ps
CPU time 3.45 seconds
Started Aug 21 08:48:32 AM UTC 24
Finished Aug 21 08:48:37 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4112292974 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.4112292974
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.2328072582
Short name T1801
Test name
Test status
Simulation time 152099234 ps
CPU time 2.84 seconds
Started Aug 21 08:48:32 AM UTC 24
Finished Aug 21 08:48:36 AM UTC 24
Peak memory 215140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2328072582 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2328072582
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.654531190
Short name T1809
Test name
Test status
Simulation time 79256324 ps
CPU time 1.44 seconds
Started Aug 21 08:48:35 AM UTC 24
Finished Aug 21 08:48:38 AM UTC 24
Peak memory 214592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=654531190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.654531190
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.2178428889
Short name T1800
Test name
Test status
Simulation time 70708527 ps
CPU time 1.04 seconds
Started Aug 21 08:48:34 AM UTC 24
Finished Aug 21 08:48:36 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2178428889 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2178428889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.3584352128
Short name T1799
Test name
Test status
Simulation time 40976846 ps
CPU time 0.96 seconds
Started Aug 21 08:48:34 AM UTC 24
Finished Aug 21 08:48:36 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3584352128 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3584352128
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.4143001417
Short name T1808
Test name
Test status
Simulation time 189372543 ps
CPU time 1.38 seconds
Started Aug 21 08:48:35 AM UTC 24
Finished Aug 21 08:48:37 AM UTC 24
Peak memory 214660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=414
3001417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_out
standing.4143001417
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.1782031367
Short name T1805
Test name
Test status
Simulation time 248723123 ps
CPU time 2.08 seconds
Started Aug 21 08:48:34 AM UTC 24
Finished Aug 21 08:48:37 AM UTC 24
Peak memory 215308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1782031367 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1782031367
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.2269341684
Short name T293
Test name
Test status
Simulation time 777617510 ps
CPU time 2.43 seconds
Started Aug 21 08:48:34 AM UTC 24
Finished Aug 21 08:48:37 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2269341684 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2269341684
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.915581134
Short name T1810
Test name
Test status
Simulation time 49313555 ps
CPU time 1.15 seconds
Started Aug 21 08:48:35 AM UTC 24
Finished Aug 21 08:48:38 AM UTC 24
Peak memory 214684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=915581134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.915581134
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.3219729446
Short name T1807
Test name
Test status
Simulation time 59758222 ps
CPU time 0.89 seconds
Started Aug 21 08:48:35 AM UTC 24
Finished Aug 21 08:48:37 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3219729446 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3219729446
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.479695288
Short name T1806
Test name
Test status
Simulation time 48681607 ps
CPU time 0.92 seconds
Started Aug 21 08:48:35 AM UTC 24
Finished Aug 21 08:48:37 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=479695288 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.479695288
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3687927926
Short name T1811
Test name
Test status
Simulation time 41346701 ps
CPU time 1.19 seconds
Started Aug 21 08:48:35 AM UTC 24
Finished Aug 21 08:48:38 AM UTC 24
Peak memory 214744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=368
7927926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_out
standing.3687927926
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.2502076133
Short name T1813
Test name
Test status
Simulation time 63750226 ps
CPU time 2.24 seconds
Started Aug 21 08:48:35 AM UTC 24
Finished Aug 21 08:48:38 AM UTC 24
Peak memory 215300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2502076133 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2502076133
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.2819086681
Short name T234
Test name
Test status
Simulation time 252333265 ps
CPU time 1.98 seconds
Started Aug 21 08:48:35 AM UTC 24
Finished Aug 21 08:48:38 AM UTC 24
Peak memory 214644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2819086681 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2819086681
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1177997395
Short name T1818
Test name
Test status
Simulation time 31730476 ps
CPU time 1.31 seconds
Started Aug 21 08:48:38 AM UTC 24
Finished Aug 21 08:48:40 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=1177997395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1177997395
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.412818118
Short name T1814
Test name
Test status
Simulation time 67208577 ps
CPU time 0.96 seconds
Started Aug 21 08:48:37 AM UTC 24
Finished Aug 21 08:48:39 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=412818118 -assert nop
ostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.412818118
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.1999037695
Short name T1812
Test name
Test status
Simulation time 34423048 ps
CPU time 0.87 seconds
Started Aug 21 08:48:36 AM UTC 24
Finished Aug 21 08:48:38 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1999037695 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1999037695
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1438004051
Short name T1823
Test name
Test status
Simulation time 53164750 ps
CPU time 1.63 seconds
Started Aug 21 08:48:38 AM UTC 24
Finished Aug 21 08:48:40 AM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=143
8004051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_out
standing.1438004051
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.4014752767
Short name T1821
Test name
Test status
Simulation time 129207093 ps
CPU time 2.88 seconds
Started Aug 21 08:48:36 AM UTC 24
Finished Aug 21 08:48:40 AM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4014752767 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.4014752767
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.1976274000
Short name T1819
Test name
Test status
Simulation time 853023165 ps
CPU time 2.63 seconds
Started Aug 21 08:48:36 AM UTC 24
Finished Aug 21 08:48:40 AM UTC 24
Peak memory 215164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1976274000 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1976274000
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.731173956
Short name T1822
Test name
Test status
Simulation time 84216067 ps
CPU time 1.16 seconds
Started Aug 21 08:48:38 AM UTC 24
Finished Aug 21 08:48:40 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=731173956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.731173956
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.1884996847
Short name T1817
Test name
Test status
Simulation time 24288778 ps
CPU time 1.03 seconds
Started Aug 21 08:48:38 AM UTC 24
Finished Aug 21 08:48:40 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1884996847 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1884996847
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.16796157
Short name T1815
Test name
Test status
Simulation time 21001686 ps
CPU time 0.83 seconds
Started Aug 21 08:48:38 AM UTC 24
Finished Aug 21 08:48:40 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16796157 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.16796157
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3823465902
Short name T1820
Test name
Test status
Simulation time 70474967 ps
CPU time 1.16 seconds
Started Aug 21 08:48:38 AM UTC 24
Finished Aug 21 08:48:40 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=382
3465902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_out
standing.3823465902
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.3566930713
Short name T1824
Test name
Test status
Simulation time 65666443 ps
CPU time 2.17 seconds
Started Aug 21 08:48:38 AM UTC 24
Finished Aug 21 08:48:41 AM UTC 24
Peak memory 225644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3566930713 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3566930713
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.2629640031
Short name T243
Test name
Test status
Simulation time 53482126 ps
CPU time 1.61 seconds
Started Aug 21 08:48:12 AM UTC 24
Finished Aug 21 08:48:14 AM UTC 24
Peak memory 214700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2629640031 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2629640031
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.3256272324
Short name T1748
Test name
Test status
Simulation time 66529925 ps
CPU time 2.86 seconds
Started Aug 21 08:48:10 AM UTC 24
Finished Aug 21 08:48:14 AM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3256272324 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3256272324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.671421829
Short name T242
Test name
Test status
Simulation time 29016067 ps
CPU time 1.07 seconds
Started Aug 21 08:48:10 AM UTC 24
Finished Aug 21 08:48:13 AM UTC 24
Peak memory 214748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=671421829 -asse
rt nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.671421829
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3598383855
Short name T240
Test name
Test status
Simulation time 426644026 ps
CPU time 1.74 seconds
Started Aug 21 08:48:12 AM UTC 24
Finished Aug 21 08:48:15 AM UTC 24
Peak memory 214716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=3598383855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3598383855
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.3919617249
Short name T137
Test name
Test status
Simulation time 57464859 ps
CPU time 1.09 seconds
Started Aug 21 08:48:10 AM UTC 24
Finished Aug 21 08:48:13 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3919617249 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3919617249
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.3463146041
Short name T304
Test name
Test status
Simulation time 52705823 ps
CPU time 1.03 seconds
Started Aug 21 08:48:09 AM UTC 24
Finished Aug 21 08:48:12 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3463146041 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3463146041
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3442194173
Short name T255
Test name
Test status
Simulation time 30647233 ps
CPU time 1.15 seconds
Started Aug 21 08:48:12 AM UTC 24
Finished Aug 21 08:48:14 AM UTC 24
Peak memory 214244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=344
2194173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outs
tanding.3442194173
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.2283029346
Short name T228
Test name
Test status
Simulation time 82601073 ps
CPU time 2.03 seconds
Started Aug 21 08:48:09 AM UTC 24
Finished Aug 21 08:48:13 AM UTC 24
Peak memory 215340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2283029346 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2283029346
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.1473426838
Short name T223
Test name
Test status
Simulation time 100449515 ps
CPU time 1.88 seconds
Started Aug 21 08:48:09 AM UTC 24
Finished Aug 21 08:48:12 AM UTC 24
Peak memory 214700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1473426838 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1473426838
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.3051036927
Short name T1816
Test name
Test status
Simulation time 32654194 ps
CPU time 0.86 seconds
Started Aug 21 08:48:38 AM UTC 24
Finished Aug 21 08:48:40 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3051036927 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3051036927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.1114690029
Short name T1826
Test name
Test status
Simulation time 18745385 ps
CPU time 0.98 seconds
Started Aug 21 08:48:39 AM UTC 24
Finished Aug 21 08:48:41 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1114690029 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1114690029
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.2300457087
Short name T1825
Test name
Test status
Simulation time 41373686 ps
CPU time 0.87 seconds
Started Aug 21 08:48:39 AM UTC 24
Finished Aug 21 08:48:41 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2300457087 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2300457087
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.2323085110
Short name T1829
Test name
Test status
Simulation time 27408344 ps
CPU time 1 seconds
Started Aug 21 08:48:39 AM UTC 24
Finished Aug 21 08:48:41 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2323085110 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2323085110
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.3758515168
Short name T1830
Test name
Test status
Simulation time 15972769 ps
CPU time 0.93 seconds
Started Aug 21 08:48:39 AM UTC 24
Finished Aug 21 08:48:41 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3758515168 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3758515168
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.2723282587
Short name T1827
Test name
Test status
Simulation time 17807176 ps
CPU time 0.97 seconds
Started Aug 21 08:48:39 AM UTC 24
Finished Aug 21 08:48:41 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2723282587 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.2723282587
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.4127993604
Short name T1832
Test name
Test status
Simulation time 36848681 ps
CPU time 1.01 seconds
Started Aug 21 08:48:40 AM UTC 24
Finished Aug 21 08:48:42 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4127993604 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.4127993604
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.394884076
Short name T1831
Test name
Test status
Simulation time 47719515 ps
CPU time 0.86 seconds
Started Aug 21 08:48:40 AM UTC 24
Finished Aug 21 08:48:41 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=394884076 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.394884076
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.2761745612
Short name T1828
Test name
Test status
Simulation time 18187860 ps
CPU time 0.82 seconds
Started Aug 21 08:48:40 AM UTC 24
Finished Aug 21 08:48:41 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2761745612 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2761745612
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.2933688868
Short name T1835
Test name
Test status
Simulation time 51076801 ps
CPU time 0.96 seconds
Started Aug 21 08:48:41 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2933688868 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2933688868
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.92644103
Short name T244
Test name
Test status
Simulation time 193417634 ps
CPU time 1.98 seconds
Started Aug 21 08:48:14 AM UTC 24
Finished Aug 21 08:48:17 AM UTC 24
Peak memory 214700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=92644103 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o
pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.92644103
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.4078347895
Short name T250
Test name
Test status
Simulation time 118345598 ps
CPU time 5.41 seconds
Started Aug 21 08:48:14 AM UTC 24
Finished Aug 21 08:48:21 AM UTC 24
Peak memory 215368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4078347895 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.4078347895
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.2249058382
Short name T1750
Test name
Test status
Simulation time 23989495 ps
CPU time 1.15 seconds
Started Aug 21 08:48:13 AM UTC 24
Finished Aug 21 08:48:15 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2249058382 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2249058382
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3583422933
Short name T237
Test name
Test status
Simulation time 53600987 ps
CPU time 1.27 seconds
Started Aug 21 08:48:15 AM UTC 24
Finished Aug 21 08:48:18 AM UTC 24
Peak memory 214740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=3583422933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3583422933
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.3540368642
Short name T1749
Test name
Test status
Simulation time 73937988 ps
CPU time 1.04 seconds
Started Aug 21 08:48:13 AM UTC 24
Finished Aug 21 08:48:15 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3540368642 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3540368642
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.1651605080
Short name T300
Test name
Test status
Simulation time 49274896 ps
CPU time 0.91 seconds
Started Aug 21 08:48:13 AM UTC 24
Finished Aug 21 08:48:15 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1651605080 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1651605080
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1552844778
Short name T256
Test name
Test status
Simulation time 53533302 ps
CPU time 1.05 seconds
Started Aug 21 08:48:14 AM UTC 24
Finished Aug 21 08:48:16 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=155
2844778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outs
tanding.1552844778
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.2060005118
Short name T224
Test name
Test status
Simulation time 28501368 ps
CPU time 2.18 seconds
Started Aug 21 08:48:12 AM UTC 24
Finished Aug 21 08:48:15 AM UTC 24
Peak memory 215276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2060005118 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2060005118
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.385489995
Short name T114
Test name
Test status
Simulation time 600779239 ps
CPU time 2.65 seconds
Started Aug 21 08:48:12 AM UTC 24
Finished Aug 21 08:48:16 AM UTC 24
Peak memory 215160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=385489995 -a
ssert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.385489995
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.2928155122
Short name T1833
Test name
Test status
Simulation time 31411613 ps
CPU time 0.82 seconds
Started Aug 21 08:48:41 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2928155122 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2928155122
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.2440957797
Short name T1834
Test name
Test status
Simulation time 17651440 ps
CPU time 0.8 seconds
Started Aug 21 08:48:41 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2440957797 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2440957797
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.2096038345
Short name T1836
Test name
Test status
Simulation time 38971760 ps
CPU time 0.85 seconds
Started Aug 21 08:48:41 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2096038345 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2096038345
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.141893464
Short name T1838
Test name
Test status
Simulation time 15576383 ps
CPU time 0.93 seconds
Started Aug 21 08:48:41 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=141893464 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.141893464
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.2611608330
Short name T1837
Test name
Test status
Simulation time 57911301 ps
CPU time 0.87 seconds
Started Aug 21 08:48:41 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2611608330 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2611608330
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.2973735000
Short name T1840
Test name
Test status
Simulation time 60636855 ps
CPU time 1.09 seconds
Started Aug 21 08:48:41 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2973735000 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2973735000
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.1543990952
Short name T1839
Test name
Test status
Simulation time 19445914 ps
CPU time 0.99 seconds
Started Aug 21 08:48:41 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1543990952 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1543990952
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.1855131793
Short name T1841
Test name
Test status
Simulation time 53311943 ps
CPU time 0.96 seconds
Started Aug 21 08:48:41 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1855131793 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1855131793
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.1990916071
Short name T1842
Test name
Test status
Simulation time 17086606 ps
CPU time 0.97 seconds
Started Aug 21 08:48:41 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1990916071 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1990916071
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.1332686536
Short name T1844
Test name
Test status
Simulation time 20128322 ps
CPU time 0.87 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:44 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1332686536 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1332686536
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.1912449354
Short name T245
Test name
Test status
Simulation time 196776337 ps
CPU time 2.42 seconds
Started Aug 21 08:48:16 AM UTC 24
Finished Aug 21 08:48:19 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1912449354 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1912449354
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.1928413301
Short name T1755
Test name
Test status
Simulation time 1976459098 ps
CPU time 3.73 seconds
Started Aug 21 08:48:16 AM UTC 24
Finished Aug 21 08:48:21 AM UTC 24
Peak memory 215156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1928413301 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1928413301
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.3220513747
Short name T1751
Test name
Test status
Simulation time 20188817 ps
CPU time 1.12 seconds
Started Aug 21 08:48:16 AM UTC 24
Finished Aug 21 08:48:18 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3220513747 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3220513747
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2074946733
Short name T116
Test name
Test status
Simulation time 28333661 ps
CPU time 1.3 seconds
Started Aug 21 08:48:17 AM UTC 24
Finished Aug 21 08:48:19 AM UTC 24
Peak memory 214740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=2074946733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2074946733
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.1942217440
Short name T257
Test name
Test status
Simulation time 19437736 ps
CPU time 1.11 seconds
Started Aug 21 08:48:16 AM UTC 24
Finished Aug 21 08:48:18 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1942217440 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1942217440
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.1538381569
Short name T302
Test name
Test status
Simulation time 19184055 ps
CPU time 1 seconds
Started Aug 21 08:48:16 AM UTC 24
Finished Aug 21 08:48:18 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1538381569 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1538381569
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3882497756
Short name T115
Test name
Test status
Simulation time 111559267 ps
CPU time 1.81 seconds
Started Aug 21 08:48:16 AM UTC 24
Finished Aug 21 08:48:19 AM UTC 24
Peak memory 214700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=388
2497756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outs
tanding.3882497756
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.4021911033
Short name T225
Test name
Test status
Simulation time 124651100 ps
CPU time 2.67 seconds
Started Aug 21 08:48:16 AM UTC 24
Finished Aug 21 08:48:19 AM UTC 24
Peak memory 215300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4021911033 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.4021911033
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.2228498608
Short name T1752
Test name
Test status
Simulation time 101890103 ps
CPU time 1.89 seconds
Started Aug 21 08:48:16 AM UTC 24
Finished Aug 21 08:48:19 AM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2228498608 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2228498608
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.1554868896
Short name T1843
Test name
Test status
Simulation time 38314800 ps
CPU time 0.71 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:44 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1554868896 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.1554868896
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.637103119
Short name T1846
Test name
Test status
Simulation time 21339405 ps
CPU time 0.97 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:45 AM UTC 24
Peak memory 214560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=637103119 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.637103119
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.2471266814
Short name T1848
Test name
Test status
Simulation time 16095580 ps
CPU time 0.86 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:45 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471266814 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2471266814
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.2611275203
Short name T1845
Test name
Test status
Simulation time 45159137 ps
CPU time 0.77 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:45 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2611275203 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2611275203
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.1909746484
Short name T1847
Test name
Test status
Simulation time 49668135 ps
CPU time 0.81 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:45 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1909746484 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1909746484
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.1005853940
Short name T1849
Test name
Test status
Simulation time 26462325 ps
CPU time 0.82 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:45 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1005853940 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1005853940
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.1938347294
Short name T1851
Test name
Test status
Simulation time 17179844 ps
CPU time 0.9 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:45 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1938347294 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1938347294
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.2325300425
Short name T1850
Test name
Test status
Simulation time 20339242 ps
CPU time 0.88 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:45 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2325300425 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2325300425
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.1938744169
Short name T1852
Test name
Test status
Simulation time 18142261 ps
CPU time 0.82 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:45 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1938744169 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1938744169
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.2422167473
Short name T1853
Test name
Test status
Simulation time 123952720 ps
CPU time 0.93 seconds
Started Aug 21 08:48:43 AM UTC 24
Finished Aug 21 08:48:45 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2422167473 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2422167473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2882871355
Short name T118
Test name
Test status
Simulation time 128409484 ps
CPU time 1.27 seconds
Started Aug 21 08:48:18 AM UTC 24
Finished Aug 21 08:48:21 AM UTC 24
Peak memory 214800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=2882871355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2882871355
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.1880239187
Short name T246
Test name
Test status
Simulation time 24691244 ps
CPU time 1.09 seconds
Started Aug 21 08:48:18 AM UTC 24
Finished Aug 21 08:48:20 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1880239187 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1880239187
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.494931196
Short name T1754
Test name
Test status
Simulation time 27521784 ps
CPU time 1.05 seconds
Started Aug 21 08:48:18 AM UTC 24
Finished Aug 21 08:48:20 AM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=494931196 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.494931196
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2732917186
Short name T258
Test name
Test status
Simulation time 60187432 ps
CPU time 1.16 seconds
Started Aug 21 08:48:18 AM UTC 24
Finished Aug 21 08:48:21 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=273
2917186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_outs
tanding.2732917186
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.3821741957
Short name T117
Test name
Test status
Simulation time 285805959 ps
CPU time 1.68 seconds
Started Aug 21 08:48:17 AM UTC 24
Finished Aug 21 08:48:20 AM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3821741957 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3821741957
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2358937956
Short name T1759
Test name
Test status
Simulation time 28585983 ps
CPU time 1.26 seconds
Started Aug 21 08:48:21 AM UTC 24
Finished Aug 21 08:48:23 AM UTC 24
Peak memory 214740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=2358937956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2358937956
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.2970574967
Short name T247
Test name
Test status
Simulation time 18271305 ps
CPU time 1.04 seconds
Started Aug 21 08:48:20 AM UTC 24
Finished Aug 21 08:48:22 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2970574967 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2970574967
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.714023214
Short name T1756
Test name
Test status
Simulation time 22010323 ps
CPU time 0.92 seconds
Started Aug 21 08:48:20 AM UTC 24
Finished Aug 21 08:48:22 AM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=714023214 -assert nopost
proc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.714023214
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2511007427
Short name T1758
Test name
Test status
Simulation time 55974535 ps
CPU time 1.11 seconds
Started Aug 21 08:48:21 AM UTC 24
Finished Aug 21 08:48:23 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=251
1007427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outs
tanding.2511007427
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.1555754740
Short name T1762
Test name
Test status
Simulation time 285314237 ps
CPU time 4.25 seconds
Started Aug 21 08:48:19 AM UTC 24
Finished Aug 21 08:48:25 AM UTC 24
Peak memory 215276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1555754740 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1555754740
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.4097224297
Short name T294
Test name
Test status
Simulation time 259378111 ps
CPU time 2.95 seconds
Started Aug 21 08:48:20 AM UTC 24
Finished Aug 21 08:48:24 AM UTC 24
Peak memory 215220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4097224297 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4097224297
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2297114852
Short name T1763
Test name
Test status
Simulation time 41518430 ps
CPU time 1.53 seconds
Started Aug 21 08:48:22 AM UTC 24
Finished Aug 21 08:48:25 AM UTC 24
Peak memory 214740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=2297114852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2297114852
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.1793406378
Short name T119
Test name
Test status
Simulation time 26846128 ps
CPU time 1.13 seconds
Started Aug 21 08:48:21 AM UTC 24
Finished Aug 21 08:48:23 AM UTC 24
Peak memory 214348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1793406378 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1793406378
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.2371913869
Short name T1757
Test name
Test status
Simulation time 19868217 ps
CPU time 0.92 seconds
Started Aug 21 08:48:21 AM UTC 24
Finished Aug 21 08:48:23 AM UTC 24
Peak memory 214492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2371913869 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2371913869
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1102057112
Short name T1760
Test name
Test status
Simulation time 56019744 ps
CPU time 1.39 seconds
Started Aug 21 08:48:21 AM UTC 24
Finished Aug 21 08:48:23 AM UTC 24
Peak memory 214360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=110
2057112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_outs
tanding.1102057112
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.3672675450
Short name T172
Test name
Test status
Simulation time 893113072 ps
CPU time 1.89 seconds
Started Aug 21 08:48:21 AM UTC 24
Finished Aug 21 08:48:24 AM UTC 24
Peak memory 214636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3672675450 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3672675450
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4084752350
Short name T1765
Test name
Test status
Simulation time 108683785 ps
CPU time 0.92 seconds
Started Aug 21 08:48:24 AM UTC 24
Finished Aug 21 08:48:26 AM UTC 24
Peak memory 214740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=4084752350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.4084752350
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2649442861
Short name T1761
Test name
Test status
Simulation time 44804349 ps
CPU time 0.89 seconds
Started Aug 21 08:48:23 AM UTC 24
Finished Aug 21 08:48:24 AM UTC 24
Peak memory 214624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2649442861 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2649442861
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.3339286888
Short name T303
Test name
Test status
Simulation time 28593383 ps
CPU time 0.98 seconds
Started Aug 21 08:48:22 AM UTC 24
Finished Aug 21 08:48:24 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3339286888 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3339286888
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2294179154
Short name T1764
Test name
Test status
Simulation time 422298554 ps
CPU time 1.29 seconds
Started Aug 21 08:48:23 AM UTC 24
Finished Aug 21 08:48:25 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=229
4179154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outs
tanding.2294179154
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.1121720822
Short name T1768
Test name
Test status
Simulation time 73207889 ps
CPU time 2.62 seconds
Started Aug 21 08:48:22 AM UTC 24
Finished Aug 21 08:48:26 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1121720822 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1121720822
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.3820447708
Short name T229
Test name
Test status
Simulation time 166821604 ps
CPU time 1.61 seconds
Started Aug 21 08:48:22 AM UTC 24
Finished Aug 21 08:48:25 AM UTC 24
Peak memory 214668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3820447708 -
assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3820447708
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2223771732
Short name T1771
Test name
Test status
Simulation time 40710826 ps
CPU time 1.45 seconds
Started Aug 21 08:48:25 AM UTC 24
Finished Aug 21 08:48:28 AM UTC 24
Peak memory 214748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=2223771732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2223771732
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.298184698
Short name T1769
Test name
Test status
Simulation time 28036163 ps
CPU time 1.09 seconds
Started Aug 21 08:48:25 AM UTC 24
Finished Aug 21 08:48:27 AM UTC 24
Peak memory 214732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=298184698 -assert nop
ostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.298184698
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.2203614259
Short name T1766
Test name
Test status
Simulation time 34712136 ps
CPU time 0.98 seconds
Started Aug 21 08:48:24 AM UTC 24
Finished Aug 21 08:48:26 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2203614259 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2203614259
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.881726692
Short name T1782
Test name
Test status
Simulation time 1407251005 ps
CPU time 4.51 seconds
Started Aug 21 08:48:25 AM UTC 24
Finished Aug 21 08:48:31 AM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=881
726692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outst
anding.881726692
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.4046579480
Short name T1767
Test name
Test status
Simulation time 25574212 ps
CPU time 1.39 seconds
Started Aug 21 08:48:24 AM UTC 24
Finished Aug 21 08:48:26 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4046579480 -assert nopos
tproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.4046579480
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.3826933832
Short name T6
Test name
Test status
Simulation time 1111415915 ps
CPU time 5.36 seconds
Started Aug 21 08:21:59 AM UTC 24
Finished Aug 21 08:22:06 AM UTC 24
Peak memory 276620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3826933832 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.3826933832
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.2373953685
Short name T186
Test name
Test status
Simulation time 3209547079 ps
CPU time 88.95 seconds
Started Aug 21 08:22:01 AM UTC 24
Finished Aug 21 08:23:32 AM UTC 24
Peak memory 723220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2373953685 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2373953685
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.1365206222
Short name T39
Test name
Test status
Simulation time 5073300122 ps
CPU time 59.51 seconds
Started Aug 21 08:21:58 AM UTC 24
Finished Aug 21 08:22:59 AM UTC 24
Peak memory 790760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1365206222 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1365206222
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.1182235416
Short name T89
Test name
Test status
Simulation time 3997584556 ps
CPU time 85.49 seconds
Started Aug 21 08:21:58 AM UTC 24
Finished Aug 21 08:23:26 AM UTC 24
Peak memory 1140900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1182235416 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1182235416
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_override.2412589410
Short name T1
Test name
Test status
Simulation time 18498361 ps
CPU time 0.84 seconds
Started Aug 21 08:21:58 AM UTC 24
Finished Aug 21 08:22:00 AM UTC 24
Peak memory 215664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2412589410 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2412589410
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_perf.3179258379
Short name T96
Test name
Test status
Simulation time 7208711147 ps
CPU time 195.67 seconds
Started Aug 21 08:22:01 AM UTC 24
Finished Aug 21 08:25:20 AM UTC 24
Peak memory 1722528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3179258379 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3179258379
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.2787565445
Short name T3
Test name
Test status
Simulation time 101982859 ps
CPU time 1.4 seconds
Started Aug 21 08:22:01 AM UTC 24
Finished Aug 21 08:22:04 AM UTC 24
Peak memory 238332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2787565445 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.2787565445
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.1417995324
Short name T28
Test name
Test status
Simulation time 1748673779 ps
CPU time 24.56 seconds
Started Aug 21 08:21:57 AM UTC 24
Finished Aug 21 08:22:23 AM UTC 24
Peak memory 329828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1417995324 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1417995324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.1203359238
Short name T38
Test name
Test status
Simulation time 812456405 ps
CPU time 16.34 seconds
Started Aug 21 08:22:02 AM UTC 24
Finished Aug 21 08:22:21 AM UTC 24
Peak memory 226568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1203359238 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1203359238
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.3139530286
Short name T69
Test name
Test status
Simulation time 3184077658 ps
CPU time 6.71 seconds
Started Aug 21 08:22:05 AM UTC 24
Finished Aug 21 08:22:13 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3139530286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3139530286
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.49812053
Short name T10
Test name
Test status
Simulation time 220618677 ps
CPU time 2.22 seconds
Started Aug 21 08:22:05 AM UTC 24
Finished Aug 21 08:22:08 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=49812053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_fifo_reset_acq.49812053
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.2729869053
Short name T49
Test name
Test status
Simulation time 121823882 ps
CPU time 1.59 seconds
Started Aug 21 08:22:07 AM UTC 24
Finished Aug 21 08:22:10 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2729869053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.2729869053
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.1243686540
Short name T50
Test name
Test status
Simulation time 6007297548 ps
CPU time 5.99 seconds
Started Aug 21 08:22:02 AM UTC 24
Finished Aug 21 08:22:10 AM UTC 24
Peak memory 233508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1243686540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.1243686540
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.2662098721
Short name T66
Test name
Test status
Simulation time 493839756 ps
CPU time 3.8 seconds
Started Aug 21 08:22:07 AM UTC 24
Finished Aug 21 08:22:13 AM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2662098721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_nack_acqfull.2662098721
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.928131482
Short name T67
Test name
Test status
Simulation time 4172070235 ps
CPU time 3 seconds
Started Aug 21 08:22:09 AM UTC 24
Finished Aug 21 08:22:14 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=928131482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_nack_acqfull_addr.928131482
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_perf.1800767627
Short name T77
Test name
Test status
Simulation time 1339821243 ps
CPU time 8.3 seconds
Started Aug 21 08:22:05 AM UTC 24
Finished Aug 21 08:22:15 AM UTC 24
Peak memory 226656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1800767627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 0.i2c_target_perf.1800767627
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.455542594
Short name T78
Test name
Test status
Simulation time 2101480456 ps
CPU time 3.65 seconds
Started Aug 21 08:22:07 AM UTC 24
Finished Aug 21 08:22:12 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=455542594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 0.i2c_target_smbus_maxlen.455542594
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.1971720396
Short name T191
Test name
Test status
Simulation time 2157154967 ps
CPU time 10.97 seconds
Started Aug 21 08:22:02 AM UTC 24
Finished Aug 21 08:22:15 AM UTC 24
Peak memory 227140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1971720396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targe
t_smoke.1971720396
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.1871086255
Short name T632
Test name
Test status
Simulation time 24453564617 ps
CPU time 346.35 seconds
Started Aug 21 08:22:05 AM UTC 24
Finished Aug 21 08:27:56 AM UTC 24
Peak memory 5023924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1871086255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 0.i2c_target_stress_all.1871086255
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.433987275
Short name T8
Test name
Test status
Simulation time 2769744934 ps
CPU time 35.8 seconds
Started Aug 21 08:22:02 AM UTC 24
Finished Aug 21 08:22:40 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=433987275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stress_rd.433987275
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.3382242221
Short name T193
Test name
Test status
Simulation time 13547059171 ps
CPU time 15.8 seconds
Started Aug 21 08:22:02 AM UTC 24
Finished Aug 21 08:22:20 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3382242221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stress_wr.3382242221
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/0.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_alert_test.1689925661
Short name T104
Test name
Test status
Simulation time 40351842 ps
CPU time 0.84 seconds
Started Aug 21 08:22:24 AM UTC 24
Finished Aug 21 08:22:26 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1689925661 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1689925661
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.2289275437
Short name T17
Test name
Test status
Simulation time 204875027 ps
CPU time 2.04 seconds
Started Aug 21 08:22:14 AM UTC 24
Finished Aug 21 08:22:18 AM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2289275437 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2289275437
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.997032680
Short name T46
Test name
Test status
Simulation time 305258322 ps
CPU time 16.18 seconds
Started Aug 21 08:22:13 AM UTC 24
Finished Aug 21 08:22:30 AM UTC 24
Peak memory 276768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=997032680 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty.997032680
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.3136626179
Short name T489
Test name
Test status
Simulation time 14022184747 ps
CPU time 205.78 seconds
Started Aug 21 08:22:13 AM UTC 24
Finished Aug 21 08:25:42 AM UTC 24
Peak memory 778712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3136626179 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3136626179
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.2630651980
Short name T40
Test name
Test status
Simulation time 779075272 ps
CPU time 1.47 seconds
Started Aug 21 08:22:13 AM UTC 24
Finished Aug 21 08:22:15 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2630651980 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.2630651980
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.1628837015
Short name T559
Test name
Test status
Simulation time 9603677859 ps
CPU time 262.93 seconds
Started Aug 21 08:22:13 AM UTC 24
Finished Aug 21 08:26:40 AM UTC 24
Peak memory 1356096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1628837015 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1628837015
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.3049381651
Short name T12
Test name
Test status
Simulation time 2716387038 ps
CPU time 10.95 seconds
Started Aug 21 08:22:22 AM UTC 24
Finished Aug 21 08:22:34 AM UTC 24
Peak memory 216704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3049381651 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.3049381651
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_override.686840501
Short name T85
Test name
Test status
Simulation time 82345197 ps
CPU time 0.99 seconds
Started Aug 21 08:22:11 AM UTC 24
Finished Aug 21 08:22:13 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=686840501 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.686840501
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_perf.1831455941
Short name T19
Test name
Test status
Simulation time 1608187383 ps
CPU time 9.48 seconds
Started Aug 21 08:22:14 AM UTC 24
Finished Aug 21 08:22:25 AM UTC 24
Peak memory 262240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1831455941 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1831455941
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.4011654569
Short name T48
Test name
Test status
Simulation time 232241713 ps
CPU time 3.81 seconds
Started Aug 21 08:22:14 AM UTC 24
Finished Aug 21 08:22:19 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4011654569 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.4011654569
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.168840841
Short name T27
Test name
Test status
Simulation time 1438095014 ps
CPU time 28.78 seconds
Started Aug 21 08:22:11 AM UTC 24
Finished Aug 21 08:22:41 AM UTC 24
Peak memory 346200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=168840841 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.168840841
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.1942477902
Short name T217
Test name
Test status
Simulation time 284437987 ps
CPU time 1.24 seconds
Started Aug 21 08:22:24 AM UTC 24
Finished Aug 21 08:22:26 AM UTC 24
Peak memory 246684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1942477902 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1942477902
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.2742658221
Short name T70
Test name
Test status
Simulation time 620189581 ps
CPU time 4.13 seconds
Started Aug 21 08:22:20 AM UTC 24
Finished Aug 21 08:22:26 AM UTC 24
Peak memory 228924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=2742658221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2742658221
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.2898783560
Short name T109
Test name
Test status
Simulation time 2339085048 ps
CPU time 1.63 seconds
Started Aug 21 08:22:18 AM UTC 24
Finished Aug 21 08:22:21 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2898783560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_acq.2898783560
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.919577600
Short name T263
Test name
Test status
Simulation time 268545188 ps
CPU time 1.69 seconds
Started Aug 21 08:22:19 AM UTC 24
Finished Aug 21 08:22:22 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=919577600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_target_fifo_reset_tx.919577600
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.2673286218
Short name T208
Test name
Test status
Simulation time 667048409 ps
CPU time 2.73 seconds
Started Aug 21 08:22:22 AM UTC 24
Finished Aug 21 08:22:25 AM UTC 24
Peak memory 216332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2673286218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.2673286218
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.2410483890
Short name T206
Test name
Test status
Simulation time 250343397 ps
CPU time 1.75 seconds
Started Aug 21 08:22:22 AM UTC 24
Finished Aug 21 08:22:25 AM UTC 24
Peak memory 215128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2410483890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.2410483890
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.584205764
Short name T57
Test name
Test status
Simulation time 2074970474 ps
CPU time 12.05 seconds
Started Aug 21 08:22:14 AM UTC 24
Finished Aug 21 08:22:28 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=584205764 -ass
ert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.584205764
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_glitch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_hrst.1850928475
Short name T178
Test name
Test status
Simulation time 543070561 ps
CPU time 3.18 seconds
Started Aug 21 08:22:20 AM UTC 24
Finished Aug 21 08:22:25 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1850928475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 1.i2c_target_hrst.1850928475
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.3891632903
Short name T207
Test name
Test status
Simulation time 906475378 ps
CPU time 8.28 seconds
Started Aug 21 08:22:16 AM UTC 24
Finished Aug 21 08:22:25 AM UTC 24
Peak memory 231116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3891632903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.3891632903
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.4119141956
Short name T370
Test name
Test status
Simulation time 16745786396 ps
CPU time 74.82 seconds
Started Aug 21 08:22:16 AM UTC 24
Finished Aug 21 08:23:32 AM UTC 24
Peak memory 2101488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=4119141956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.4119141956
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.4015067628
Short name T68
Test name
Test status
Simulation time 784569253 ps
CPU time 2.99 seconds
Started Aug 21 08:22:23 AM UTC 24
Finished Aug 21 08:22:27 AM UTC 24
Peak memory 227072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4015067628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_target_nack_acqfull.4015067628
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.1563495483
Short name T72
Test name
Test status
Simulation time 445422236 ps
CPU time 2.99 seconds
Started Aug 21 08:22:23 AM UTC 24
Finished Aug 21 08:22:27 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1563495483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_nack_acqfull_addr.1563495483
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_perf.1958121278
Short name T315
Test name
Test status
Simulation time 1225173825 ps
CPU time 6.62 seconds
Started Aug 21 08:22:19 AM UTC 24
Finished Aug 21 08:22:27 AM UTC 24
Peak memory 228976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1958121278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 1.i2c_target_perf.1958121278
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.3726258168
Short name T318
Test name
Test status
Simulation time 3505355194 ps
CPU time 3.51 seconds
Started Aug 21 08:22:23 AM UTC 24
Finished Aug 21 08:22:27 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3726258168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_target_smbus_maxlen.3726258168
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.3393069257
Short name T241
Test name
Test status
Simulation time 395481433 ps
CPU time 5.26 seconds
Started Aug 21 08:22:14 AM UTC 24
Finished Aug 21 08:22:21 AM UTC 24
Peak memory 226852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3393069257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targe
t_smoke.3393069257
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.4063954481
Short name T266
Test name
Test status
Simulation time 66562217833 ps
CPU time 170.61 seconds
Started Aug 21 08:22:20 AM UTC 24
Finished Aug 21 08:25:14 AM UTC 24
Peak memory 1833172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=4063954481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 1.i2c_target_stress_all.4063954481
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.832646281
Short name T168
Test name
Test status
Simulation time 617585824 ps
CPU time 26.54 seconds
Started Aug 21 08:22:16 AM UTC 24
Finished Aug 21 08:22:43 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=832646281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stress_rd.832646281
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.139831135
Short name T1225
Test name
Test status
Simulation time 52604464155 ps
CPU time 929.17 seconds
Started Aug 21 08:22:16 AM UTC 24
Finished Aug 21 08:37:53 AM UTC 24
Peak memory 8638616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=139831135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stress_wr.139831135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.1724453129
Short name T409
Test name
Test status
Simulation time 4114126663 ps
CPU time 121.71 seconds
Started Aug 21 08:22:16 AM UTC 24
Finished Aug 21 08:24:20 AM UTC 24
Peak memory 1192144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1724453129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_stretch.1724453129
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.3349833320
Short name T80
Test name
Test status
Simulation time 1341216750 ps
CPU time 10.09 seconds
Started Aug 21 08:22:16 AM UTC 24
Finished Aug 21 08:22:27 AM UTC 24
Peak memory 230920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3349833320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_timeout.3349833320
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.2330651124
Short name T76
Test name
Test status
Simulation time 166351843 ps
CPU time 3.42 seconds
Started Aug 21 08:22:22 AM UTC 24
Finished Aug 21 08:22:26 AM UTC 24
Peak memory 232852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2330651124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.2330651124
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_alert_test.1102159718
Short name T469
Test name
Test status
Simulation time 21806884 ps
CPU time 0.97 seconds
Started Aug 21 08:25:20 AM UTC 24
Finished Aug 21 08:25:22 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1102159718 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1102159718
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_fmt_empty.2351950568
Short name T464
Test name
Test status
Simulation time 306238611 ps
CPU time 13.61 seconds
Started Aug 21 08:25:03 AM UTC 24
Finished Aug 21 08:25:17 AM UTC 24
Peak memory 276516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2351950568 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.2351950568
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_full.2103561071
Short name T639
Test name
Test status
Simulation time 19934166832 ps
CPU time 175.26 seconds
Started Aug 21 08:25:03 AM UTC 24
Finished Aug 21 08:28:01 AM UTC 24
Peak memory 737556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2103561071 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2103561071
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_overflow.1018785841
Short name T606
Test name
Test status
Simulation time 9849363737 ps
CPU time 152.65 seconds
Started Aug 21 08:25:02 AM UTC 24
Finished Aug 21 08:27:37 AM UTC 24
Peak memory 794896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1018785841 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1018785841
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.847615572
Short name T268
Test name
Test status
Simulation time 294028041 ps
CPU time 1.7 seconds
Started Aug 21 08:25:02 AM UTC 24
Finished Aug 21 08:25:04 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=847615572 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt.847615572
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_rx.1454275125
Short name T458
Test name
Test status
Simulation time 1000215290 ps
CPU time 6.44 seconds
Started Aug 21 08:25:03 AM UTC 24
Finished Aug 21 08:25:10 AM UTC 24
Peak memory 243860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1454275125 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.1454275125
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.341393690
Short name T120
Test name
Test status
Simulation time 4789147491 ps
CPU time 81.9 seconds
Started Aug 21 08:25:01 AM UTC 24
Finished Aug 21 08:26:25 AM UTC 24
Peak memory 1095964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=341393690 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.341393690
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.2594508420
Short name T278
Test name
Test status
Simulation time 334522834 ps
CPU time 5.44 seconds
Started Aug 21 08:25:15 AM UTC 24
Finished Aug 21 08:25:22 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2594508420 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2594508420
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_override.3975518204
Short name T450
Test name
Test status
Simulation time 90773769 ps
CPU time 1.06 seconds
Started Aug 21 08:25:00 AM UTC 24
Finished Aug 21 08:25:02 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3975518204 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3975518204
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_perf.2003139115
Short name T15
Test name
Test status
Simulation time 3063668719 ps
CPU time 29.37 seconds
Started Aug 21 08:25:03 AM UTC 24
Finished Aug 21 08:25:34 AM UTC 24
Peak memory 233632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2003139115 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.2003139115
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_perf_precise.153969470
Short name T457
Test name
Test status
Simulation time 456058449 ps
CPU time 4.68 seconds
Started Aug 21 08:25:04 AM UTC 24
Finished Aug 21 08:25:10 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=153969470 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.153969470
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_smoke.1667645396
Short name T512
Test name
Test status
Simulation time 1264464672 ps
CPU time 55.09 seconds
Started Aug 21 08:24:59 AM UTC 24
Finished Aug 21 08:25:56 AM UTC 24
Peak memory 315684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1667645396 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1667645396
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.1190392985
Short name T429
Test name
Test status
Simulation time 1749865829 ps
CPU time 13.73 seconds
Started Aug 21 08:25:04 AM UTC 24
Finished Aug 21 08:25:19 AM UTC 24
Peak memory 233832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1190392985 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1190392985
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_bad_addr.3617778548
Short name T475
Test name
Test status
Simulation time 1055871839 ps
CPU time 8.09 seconds
Started Aug 21 08:25:14 AM UTC 24
Finished Aug 21 08:25:23 AM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3617778548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3617778548
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_acq.3994305527
Short name T420
Test name
Test status
Simulation time 153775798 ps
CPU time 1.64 seconds
Started Aug 21 08:25:13 AM UTC 24
Finished Aug 21 08:25:16 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3994305527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_acq.3994305527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.1634026706
Short name T463
Test name
Test status
Simulation time 189195468 ps
CPU time 1.27 seconds
Started Aug 21 08:25:13 AM UTC 24
Finished Aug 21 08:25:15 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1634026706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_fifo_reset_tx.1634026706
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_acq.1025986441
Short name T470
Test name
Test status
Simulation time 420462955 ps
CPU time 4.5 seconds
Started Aug 21 08:25:16 AM UTC 24
Finished Aug 21 08:25:22 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1025986441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.1025986441
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_tx.3155169873
Short name T465
Test name
Test status
Simulation time 129675174 ps
CPU time 1.84 seconds
Started Aug 21 08:25:16 AM UTC 24
Finished Aug 21 08:25:19 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3155169873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.3155169873
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_intr_smoke.2084090153
Short name T423
Test name
Test status
Simulation time 2821528273 ps
CPU time 8.39 seconds
Started Aug 21 08:25:07 AM UTC 24
Finished Aug 21 08:25:17 AM UTC 24
Peak memory 233648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2084090153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.2084090153
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_intr_stress_wr.1514604768
Short name T491
Test name
Test status
Simulation time 9225049408 ps
CPU time 34.67 seconds
Started Aug 21 08:25:08 AM UTC 24
Finished Aug 21 08:25:44 AM UTC 24
Peak memory 655604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1514604768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1514604768
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull.2865675909
Short name T472
Test name
Test status
Simulation time 2624599475 ps
CPU time 2.77 seconds
Started Aug 21 08:25:19 AM UTC 24
Finished Aug 21 08:25:22 AM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2865675909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 10.i2c_target_nack_acqfull.2865675909
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull_addr.3240007602
Short name T474
Test name
Test status
Simulation time 1176522626 ps
CPU time 3.59 seconds
Started Aug 21 08:25:19 AM UTC 24
Finished Aug 21 08:25:23 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3240007602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_nack_acqfull_addr.3240007602
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_nack_txstretch.3429365813
Short name T471
Test name
Test status
Simulation time 271077530 ps
CPU time 2.27 seconds
Started Aug 21 08:25:19 AM UTC 24
Finished Aug 21 08:25:22 AM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3429365813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_nack_txstretch.3429365813
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_perf.1255125593
Short name T467
Test name
Test status
Simulation time 1134146223 ps
CPU time 6.52 seconds
Started Aug 21 08:25:14 AM UTC 24
Finished Aug 21 08:25:22 AM UTC 24
Peak memory 230860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1255125593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 10.i2c_target_perf.1255125593
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_smbus_maxlen.4137637508
Short name T476
Test name
Test status
Simulation time 1070167972 ps
CPU time 4.64 seconds
Started Aug 21 08:25:19 AM UTC 24
Finished Aug 21 08:25:24 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4137637508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 10.i2c_target_smbus_maxlen.4137637508
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_smoke.1959552242
Short name T417
Test name
Test status
Simulation time 2526942715 ps
CPU time 11.2 seconds
Started Aug 21 08:25:05 AM UTC 24
Finished Aug 21 08:25:18 AM UTC 24
Peak memory 226904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1959552242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_targ
et_smoke.1959552242
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.838557027
Short name T519
Test name
Test status
Simulation time 1459323469 ps
CPU time 60.13 seconds
Started Aug 21 08:25:05 AM UTC 24
Finished Aug 21 08:26:07 AM UTC 24
Peak memory 227136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=838557027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_t
arget_stress_rd.838557027
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_stress_wr.1390023782
Short name T635
Test name
Test status
Simulation time 31857037591 ps
CPU time 171.31 seconds
Started Aug 21 08:25:05 AM UTC 24
Finished Aug 21 08:27:59 AM UTC 24
Peak memory 3029280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1390023782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stress_wr.1390023782
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_stretch.2399106842
Short name T425
Test name
Test status
Simulation time 2607721952 ps
CPU time 10.53 seconds
Started Aug 21 08:25:06 AM UTC 24
Finished Aug 21 08:25:18 AM UTC 24
Peak memory 315608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2399106842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_stretch.2399106842
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_timeout.3141725740
Short name T461
Test name
Test status
Simulation time 3655492018 ps
CPU time 8.51 seconds
Started Aug 21 08:25:11 AM UTC 24
Finished Aug 21 08:25:20 AM UTC 24
Peak memory 231128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3141725740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_timeout.3141725740
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/10.i2c_target_tx_stretch_ctrl.1248975099
Short name T468
Test name
Test status
Simulation time 172384793 ps
CPU time 3.18 seconds
Started Aug 21 08:25:17 AM UTC 24
Finished Aug 21 08:25:22 AM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1248975099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.1248975099
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_alert_test.1260031955
Short name T500
Test name
Test status
Simulation time 18651634 ps
CPU time 0.97 seconds
Started Aug 21 08:25:47 AM UTC 24
Finished Aug 21 08:25:49 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1260031955 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1260031955
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.717862647
Short name T479
Test name
Test status
Simulation time 308804243 ps
CPU time 1.87 seconds
Started Aug 21 08:25:23 AM UTC 24
Finished Aug 21 08:25:26 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=717862647 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.717862647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_fmt_empty.1697634962
Short name T487
Test name
Test status
Simulation time 458120677 ps
CPU time 14.29 seconds
Started Aug 21 08:25:22 AM UTC 24
Finished Aug 21 08:25:38 AM UTC 24
Peak memory 262232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1697634962 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty.1697634962
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_full.4144637515
Short name T636
Test name
Test status
Simulation time 5037077381 ps
CPU time 153.13 seconds
Started Aug 21 08:25:23 AM UTC 24
Finished Aug 21 08:27:59 AM UTC 24
Peak memory 667636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4144637515 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.4144637515
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_overflow.2958866511
Short name T551
Test name
Test status
Simulation time 8342401790 ps
CPU time 70.65 seconds
Started Aug 21 08:25:22 AM UTC 24
Finished Aug 21 08:26:34 AM UTC 24
Peak memory 768284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2958866511 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2958866511
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.145609923
Short name T477
Test name
Test status
Simulation time 145489584 ps
CPU time 1.64 seconds
Started Aug 21 08:25:22 AM UTC 24
Finished Aug 21 08:25:25 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=145609923 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt.145609923
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.1050808746
Short name T483
Test name
Test status
Simulation time 258984311 ps
CPU time 9.65 seconds
Started Aug 21 08:25:23 AM UTC 24
Finished Aug 21 08:25:34 AM UTC 24
Peak memory 237672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1050808746 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.1050808746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_watermark.231594301
Short name T152
Test name
Test status
Simulation time 13108377052 ps
CPU time 112.14 seconds
Started Aug 21 08:25:21 AM UTC 24
Finished Aug 21 08:27:15 AM UTC 24
Peak memory 1390244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231594301 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.231594301
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.375996080
Short name T279
Test name
Test status
Simulation time 2889604346 ps
CPU time 8.46 seconds
Started Aug 21 08:25:39 AM UTC 24
Finished Aug 21 08:25:48 AM UTC 24
Peak memory 216916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=375996080 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.375996080
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_override.3540245382
Short name T473
Test name
Test status
Simulation time 275664579 ps
CPU time 0.95 seconds
Started Aug 21 08:25:21 AM UTC 24
Finished Aug 21 08:25:23 AM UTC 24
Peak memory 213456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3540245382 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3540245382
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_perf.4243238933
Short name T745
Test name
Test status
Simulation time 12495160705 ps
CPU time 252.89 seconds
Started Aug 21 08:25:23 AM UTC 24
Finished Aug 21 08:29:40 AM UTC 24
Peak memory 1919160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4243238933 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.4243238933
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_perf_precise.523494090
Short name T261
Test name
Test status
Simulation time 1851536106 ps
CPU time 9.87 seconds
Started Aug 21 08:25:23 AM UTC 24
Finished Aug 21 08:25:34 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=523494090 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.523494090
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_smoke.1325755915
Short name T484
Test name
Test status
Simulation time 5056328942 ps
CPU time 15.13 seconds
Started Aug 21 08:25:20 AM UTC 24
Finished Aug 21 08:25:36 AM UTC 24
Peak memory 266516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1325755915 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1325755915
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_host_stretch_timeout.3654414208
Short name T503
Test name
Test status
Simulation time 1551049264 ps
CPU time 25.32 seconds
Started Aug 21 08:25:23 AM UTC 24
Finished Aug 21 08:25:50 AM UTC 24
Peak memory 227096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3654414208 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3654414208
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_bad_addr.3372877728
Short name T490
Test name
Test status
Simulation time 1989228233 ps
CPU time 4.4 seconds
Started Aug 21 08:25:37 AM UTC 24
Finished Aug 21 08:25:43 AM UTC 24
Peak memory 228896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3372877728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3372877728
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_acq.2277992566
Short name T485
Test name
Test status
Simulation time 236831496 ps
CPU time 1.15 seconds
Started Aug 21 08:25:34 AM UTC 24
Finished Aug 21 08:25:37 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2277992566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_fifo_reset_acq.2277992566
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_tx.1490014319
Short name T488
Test name
Test status
Simulation time 379233184 ps
CPU time 1.58 seconds
Started Aug 21 08:25:35 AM UTC 24
Finished Aug 21 08:25:38 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1490014319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_fifo_reset_tx.1490014319
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_acq.2860920694
Short name T498
Test name
Test status
Simulation time 2253321882 ps
CPU time 5.21 seconds
Started Aug 21 08:25:43 AM UTC 24
Finished Aug 21 08:25:49 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2860920694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.2860920694
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_tx.3552139144
Short name T494
Test name
Test status
Simulation time 140315201 ps
CPU time 2 seconds
Started Aug 21 08:25:43 AM UTC 24
Finished Aug 21 08:25:46 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3552139144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.3552139144
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_intr_smoke.474586479
Short name T482
Test name
Test status
Simulation time 2031108788 ps
CPU time 5.51 seconds
Started Aug 21 08:25:27 AM UTC 24
Finished Aug 21 08:25:33 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=474586479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_intr_smoke.474586479
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_intr_stress_wr.2750895687
Short name T526
Test name
Test status
Simulation time 9477871977 ps
CPU time 38.66 seconds
Started Aug 21 08:25:31 AM UTC 24
Finished Aug 21 08:26:11 AM UTC 24
Peak memory 772336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2750895687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.2750895687
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull.1147313251
Short name T505
Test name
Test status
Simulation time 495379265 ps
CPU time 4.15 seconds
Started Aug 21 08:25:46 AM UTC 24
Finished Aug 21 08:25:51 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1147313251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_target_nack_acqfull.1147313251
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull_addr.2112690881
Short name T506
Test name
Test status
Simulation time 523877521 ps
CPU time 4.43 seconds
Started Aug 21 08:25:46 AM UTC 24
Finished Aug 21 08:25:51 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2112690881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_nack_acqfull_addr.2112690881
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_perf.3020407521
Short name T492
Test name
Test status
Simulation time 8863142902 ps
CPU time 8.22 seconds
Started Aug 21 08:25:35 AM UTC 24
Finished Aug 21 08:25:45 AM UTC 24
Peak memory 233748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3020407521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 11.i2c_target_perf.3020407521
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_smbus_maxlen.3018124433
Short name T502
Test name
Test status
Simulation time 1001344224 ps
CPU time 3.92 seconds
Started Aug 21 08:25:45 AM UTC 24
Finished Aug 21 08:25:50 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3018124433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_target_smbus_maxlen.3018124433
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_smoke.921312357
Short name T521
Test name
Test status
Simulation time 2552352967 ps
CPU time 42.23 seconds
Started Aug 21 08:25:25 AM UTC 24
Finished Aug 21 08:26:08 AM UTC 24
Peak memory 229316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=921312357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_targe
t_smoke.921312357
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_stress_all.2678800466
Short name T575
Test name
Test status
Simulation time 28716980697 ps
CPU time 75.84 seconds
Started Aug 21 08:25:37 AM UTC 24
Finished Aug 21 08:26:55 AM UTC 24
Peak memory 840100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2678800466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 11.i2c_target_stress_all.2678800466
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_stress_rd.2404027134
Short name T501
Test name
Test status
Simulation time 4559891657 ps
CPU time 22.14 seconds
Started Aug 21 08:25:26 AM UTC 24
Finished Aug 21 08:25:49 AM UTC 24
Peak memory 233684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2404027134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stress_rd.2404027134
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_stress_wr.2498135617
Short name T566
Test name
Test status
Simulation time 25002853587 ps
CPU time 77.11 seconds
Started Aug 21 08:25:26 AM UTC 24
Finished Aug 21 08:26:45 AM UTC 24
Peak memory 1257636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2498135617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stress_wr.2498135617
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_stretch.1694016133
Short name T480
Test name
Test status
Simulation time 200731179 ps
CPU time 2.17 seconds
Started Aug 21 08:25:27 AM UTC 24
Finished Aug 21 08:25:30 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1694016133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_stretch.1694016133
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_timeout.3442552576
Short name T493
Test name
Test status
Simulation time 1293897113 ps
CPU time 10.57 seconds
Started Aug 21 08:25:33 AM UTC 24
Finished Aug 21 08:25:45 AM UTC 24
Peak memory 232984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3442552576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_timeout.3442552576
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/11.i2c_target_tx_stretch_ctrl.236467406
Short name T511
Test name
Test status
Simulation time 396689044 ps
CPU time 10.71 seconds
Started Aug 21 08:25:44 AM UTC 24
Finished Aug 21 08:25:56 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=236467406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_tx_stretch_ctrl.236467406
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_alert_test.3456702590
Short name T499
Test name
Test status
Simulation time 54545450 ps
CPU time 0.84 seconds
Started Aug 21 08:26:12 AM UTC 24
Finished Aug 21 08:26:14 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3456702590 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3456702590
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.1924197518
Short name T510
Test name
Test status
Simulation time 76547578 ps
CPU time 2.44 seconds
Started Aug 21 08:25:52 AM UTC 24
Finished Aug 21 08:25:55 AM UTC 24
Peak memory 216668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1924197518 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.1924197518
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_fmt_empty.3404041800
Short name T515
Test name
Test status
Simulation time 1200357358 ps
CPU time 8.38 seconds
Started Aug 21 08:25:50 AM UTC 24
Finished Aug 21 08:26:00 AM UTC 24
Peak memory 278616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3404041800 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empty.3404041800
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_full.1194189925
Short name T576
Test name
Test status
Simulation time 3739740398 ps
CPU time 63.69 seconds
Started Aug 21 08:25:51 AM UTC 24
Finished Aug 21 08:26:56 AM UTC 24
Peak memory 539088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1194189925 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1194189925
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_overflow.3537899447
Short name T567
Test name
Test status
Simulation time 1875025192 ps
CPU time 54.53 seconds
Started Aug 21 08:25:49 AM UTC 24
Finished Aug 21 08:26:45 AM UTC 24
Peak memory 596116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3537899447 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3537899447
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_fmt.1117462786
Short name T508
Test name
Test status
Simulation time 446332724 ps
CPU time 1.49 seconds
Started Aug 21 08:25:50 AM UTC 24
Finished Aug 21 08:25:53 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1117462786 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt.1117462786
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_rx.3674778371
Short name T513
Test name
Test status
Simulation time 660204793 ps
CPU time 5.82 seconds
Started Aug 21 08:25:51 AM UTC 24
Finished Aug 21 08:25:57 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3674778371 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.3674778371
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_watermark.1997852421
Short name T121
Test name
Test status
Simulation time 10874978357 ps
CPU time 112.34 seconds
Started Aug 21 08:25:49 AM UTC 24
Finished Aug 21 08:27:44 AM UTC 24
Peak memory 1579172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1997852421 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1997852421
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.2526311679
Short name T531
Test name
Test status
Simulation time 695945834 ps
CPU time 3.24 seconds
Started Aug 21 08:26:08 AM UTC 24
Finished Aug 21 08:26:12 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2526311679 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.2526311679
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_override.2441227496
Short name T158
Test name
Test status
Simulation time 30667623 ps
CPU time 1.14 seconds
Started Aug 21 08:25:49 AM UTC 24
Finished Aug 21 08:25:51 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2441227496 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2441227496
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_perf.804988962
Short name T565
Test name
Test status
Simulation time 4699473392 ps
CPU time 49.92 seconds
Started Aug 21 08:25:51 AM UTC 24
Finished Aug 21 08:26:42 AM UTC 24
Peak memory 237396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=804988962 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.804988962
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_perf_precise.3583439015
Short name T509
Test name
Test status
Simulation time 42741444 ps
CPU time 1.89 seconds
Started Aug 21 08:25:52 AM UTC 24
Finished Aug 21 08:25:55 AM UTC 24
Peak memory 238336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3583439015 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.3583439015
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_smoke.119589648
Short name T529
Test name
Test status
Simulation time 2452059792 ps
CPU time 23.47 seconds
Started Aug 21 08:25:47 AM UTC 24
Finished Aug 21 08:26:12 AM UTC 24
Peak memory 342188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=119589648 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.119589648
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_stress_all.2049907472
Short name T271
Test name
Test status
Simulation time 15491174576 ps
CPU time 391.06 seconds
Started Aug 21 08:25:52 AM UTC 24
Finished Aug 21 08:32:28 AM UTC 24
Peak memory 3074276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2049907472 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.2049907472
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_host_stretch_timeout.4123137702
Short name T539
Test name
Test status
Simulation time 1172607385 ps
CPU time 27.63 seconds
Started Aug 21 08:25:52 AM UTC 24
Finished Aug 21 08:26:21 AM UTC 24
Peak memory 226880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4123137702 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.4123137702
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_bad_addr.3774435120
Short name T527
Test name
Test status
Simulation time 1441393892 ps
CPU time 7.34 seconds
Started Aug 21 08:26:03 AM UTC 24
Finished Aug 21 08:26:11 AM UTC 24
Peak memory 226780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3774435120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.3774435120
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_tx.1243774593
Short name T516
Test name
Test status
Simulation time 1641876477 ps
CPU time 1.73 seconds
Started Aug 21 08:26:01 AM UTC 24
Finished Aug 21 08:26:03 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1243774593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_fifo_reset_tx.1243774593
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_acq.956986542
Short name T533
Test name
Test status
Simulation time 1513911763 ps
CPU time 3.97 seconds
Started Aug 21 08:26:08 AM UTC 24
Finished Aug 21 08:26:13 AM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=956986542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.956986542
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_tx.722007125
Short name T528
Test name
Test status
Simulation time 1203696829 ps
CPU time 1.51 seconds
Started Aug 21 08:26:09 AM UTC 24
Finished Aug 21 08:26:12 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=722007125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.722007125
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.3770958442
Short name T518
Test name
Test status
Simulation time 3512904781 ps
CPU time 9.61 seconds
Started Aug 21 08:25:56 AM UTC 24
Finished Aug 21 08:26:07 AM UTC 24
Peak memory 227208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3770958442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.3770958442
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_intr_stress_wr.1939627579
Short name T594
Test name
Test status
Simulation time 21643477030 ps
CPU time 84.15 seconds
Started Aug 21 08:25:57 AM UTC 24
Finished Aug 21 08:27:23 AM UTC 24
Peak memory 1599652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1939627579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1939627579
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull.2224298372
Short name T537
Test name
Test status
Simulation time 536954337 ps
CPU time 4.23 seconds
Started Aug 21 08:26:10 AM UTC 24
Finished Aug 21 08:26:16 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2224298372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 12.i2c_target_nack_acqfull.2224298372
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull_addr.1781075486
Short name T538
Test name
Test status
Simulation time 542133349 ps
CPU time 4.98 seconds
Started Aug 21 08:26:10 AM UTC 24
Finished Aug 21 08:26:16 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1781075486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_nack_acqfull_addr.1781075486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_nack_txstretch.2909015776
Short name T536
Test name
Test status
Simulation time 143392989 ps
CPU time 2.54 seconds
Started Aug 21 08:26:11 AM UTC 24
Finished Aug 21 08:26:15 AM UTC 24
Peak memory 233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2909015776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_nack_txstretch.2909015776
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_perf.3810437595
Short name T520
Test name
Test status
Simulation time 515865311 ps
CPU time 5.52 seconds
Started Aug 21 08:26:02 AM UTC 24
Finished Aug 21 08:26:08 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3810437595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 12.i2c_target_perf.3810437595
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_smbus_maxlen.2677192400
Short name T496
Test name
Test status
Simulation time 1479834213 ps
CPU time 2.76 seconds
Started Aug 21 08:26:10 AM UTC 24
Finished Aug 21 08:26:14 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2677192400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 12.i2c_target_smbus_maxlen.2677192400
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_smoke.2406323896
Short name T522
Test name
Test status
Simulation time 4027488176 ps
CPU time 14.91 seconds
Started Aug 21 08:25:53 AM UTC 24
Finished Aug 21 08:26:09 AM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2406323896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_targ
et_smoke.2406323896
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_stress_rd.32967193
Short name T540
Test name
Test status
Simulation time 1447495703 ps
CPU time 24.91 seconds
Started Aug 21 08:25:55 AM UTC 24
Finished Aug 21 08:26:21 AM UTC 24
Peak memory 233640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=32967193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_stress_rd.32967193
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.1257574293
Short name T962
Test name
Test status
Simulation time 40878200724 ps
CPU time 442.02 seconds
Started Aug 21 08:25:54 AM UTC 24
Finished Aug 21 08:33:21 AM UTC 24
Peak memory 5429476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1257574293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stress_wr.1257574293
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_stretch.3751455093
Short name T524
Test name
Test status
Simulation time 714627858 ps
CPU time 12.37 seconds
Started Aug 21 08:25:56 AM UTC 24
Finished Aug 21 08:26:10 AM UTC 24
Peak memory 339992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3751455093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_stretch.3751455093
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_timeout.3697833116
Short name T523
Test name
Test status
Simulation time 2825486570 ps
CPU time 11.07 seconds
Started Aug 21 08:25:57 AM UTC 24
Finished Aug 21 08:26:10 AM UTC 24
Peak memory 244260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3697833116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_timeout.3697833116
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/12.i2c_target_tx_stretch_ctrl.3799048934
Short name T535
Test name
Test status
Simulation time 239402483 ps
CPU time 3.96 seconds
Started Aug 21 08:26:09 AM UTC 24
Finished Aug 21 08:26:14 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3799048934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.3799048934
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_alert_test.595284125
Short name T558
Test name
Test status
Simulation time 50975716 ps
CPU time 1 seconds
Started Aug 21 08:26:37 AM UTC 24
Finished Aug 21 08:26:39 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=595284125 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.595284125
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_error_intr.3524143775
Short name T486
Test name
Test status
Simulation time 475042940 ps
CPU time 2.87 seconds
Started Aug 21 08:26:15 AM UTC 24
Finished Aug 21 08:26:19 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3524143775 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3524143775
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_fmt_empty.2867043755
Short name T542
Test name
Test status
Simulation time 663570317 ps
CPU time 11.1 seconds
Started Aug 21 08:26:14 AM UTC 24
Finished Aug 21 08:26:26 AM UTC 24
Peak memory 252004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2867043755 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empty.2867043755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_full.2658599052
Short name T728
Test name
Test status
Simulation time 19934631778 ps
CPU time 192.08 seconds
Started Aug 21 08:26:14 AM UTC 24
Finished Aug 21 08:29:29 AM UTC 24
Peak memory 659664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2658599052 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2658599052
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_overflow.1557524178
Short name T655
Test name
Test status
Simulation time 1781541871 ps
CPU time 113.72 seconds
Started Aug 21 08:26:13 AM UTC 24
Finished Aug 21 08:28:09 AM UTC 24
Peak memory 663828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1557524178 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1557524178
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_fmt.947414094
Short name T530
Test name
Test status
Simulation time 160951612 ps
CPU time 1.44 seconds
Started Aug 21 08:26:14 AM UTC 24
Finished Aug 21 08:26:16 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=947414094 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fmt.947414094
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_rx.477644369
Short name T541
Test name
Test status
Simulation time 152280516 ps
CPU time 9.98 seconds
Started Aug 21 08:26:14 AM UTC 24
Finished Aug 21 08:26:25 AM UTC 24
Peak memory 216604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=477644369 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.477644369
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_watermark.4088763210
Short name T620
Test name
Test status
Simulation time 3455833261 ps
CPU time 91.04 seconds
Started Aug 21 08:26:13 AM UTC 24
Finished Aug 21 08:27:46 AM UTC 24
Peak memory 1069532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4088763210 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.4088763210
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_may_nack.2898761437
Short name T292
Test name
Test status
Simulation time 866727111 ps
CPU time 4.16 seconds
Started Aug 21 08:26:31 AM UTC 24
Finished Aug 21 08:26:37 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2898761437 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.2898761437
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_override.1609595745
Short name T525
Test name
Test status
Simulation time 19348739 ps
CPU time 0.93 seconds
Started Aug 21 08:26:13 AM UTC 24
Finished Aug 21 08:26:15 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1609595745 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1609595745
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_perf.2272747288
Short name T1741
Test name
Test status
Simulation time 74017838795 ps
CPU time 1751.29 seconds
Started Aug 21 08:26:15 AM UTC 24
Finished Aug 21 08:55:44 AM UTC 24
Peak memory 4067556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2272747288 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2272747288
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_perf_precise.2988471529
Short name T262
Test name
Test status
Simulation time 551542229 ps
CPU time 3.13 seconds
Started Aug 21 08:26:15 AM UTC 24
Finished Aug 21 08:26:19 AM UTC 24
Peak memory 216604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2988471529 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.2988471529
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_smoke.782073241
Short name T497
Test name
Test status
Simulation time 4115616335 ps
CPU time 14.36 seconds
Started Aug 21 08:26:13 AM UTC 24
Finished Aug 21 08:26:28 AM UTC 24
Peak memory 248028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=782073241 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.782073241
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_host_stretch_timeout.4292456718
Short name T549
Test name
Test status
Simulation time 1357542214 ps
CPU time 16.43 seconds
Started Aug 21 08:26:15 AM UTC 24
Finished Aug 21 08:26:33 AM UTC 24
Peak memory 226880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4292456718 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.4292456718
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_bad_addr.1805597264
Short name T561
Test name
Test status
Simulation time 970232809 ps
CPU time 7.84 seconds
Started Aug 21 08:26:30 AM UTC 24
Finished Aug 21 08:26:40 AM UTC 24
Peak memory 229148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1805597264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1805597264
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_acq.1942892154
Short name T544
Test name
Test status
Simulation time 389078158 ps
CPU time 1.68 seconds
Started Aug 21 08:26:26 AM UTC 24
Finished Aug 21 08:26:29 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1942892154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_acq.1942892154
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.2572583027
Short name T546
Test name
Test status
Simulation time 629952740 ps
CPU time 2.34 seconds
Started Aug 21 08:26:27 AM UTC 24
Finished Aug 21 08:26:30 AM UTC 24
Peak memory 218572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2572583027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_fifo_reset_tx.2572583027
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_acq.680336887
Short name T555
Test name
Test status
Simulation time 1041698722 ps
CPU time 2.16 seconds
Started Aug 21 08:26:33 AM UTC 24
Finished Aug 21 08:26:37 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=680336887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.680336887
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_tx.1565775703
Short name T307
Test name
Test status
Simulation time 143508448 ps
CPU time 1.6 seconds
Started Aug 21 08:26:33 AM UTC 24
Finished Aug 21 08:26:36 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1565775703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.1565775703
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_hrst.687532872
Short name T553
Test name
Test status
Simulation time 1193046342 ps
CPU time 3.74 seconds
Started Aug 21 08:26:30 AM UTC 24
Finished Aug 21 08:26:36 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=687532872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.i2c_target_hrst.687532872
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_intr_smoke.837749122
Short name T543
Test name
Test status
Simulation time 897994844 ps
CPU time 6.53 seconds
Started Aug 21 08:26:20 AM UTC 24
Finished Aug 21 08:26:27 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=837749122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_intr_smoke.837749122
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_intr_stress_wr.2423790611
Short name T548
Test name
Test status
Simulation time 9652085271 ps
CPU time 9.9 seconds
Started Aug 21 08:26:22 AM UTC 24
Finished Aug 21 08:26:33 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2423790611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2423790611
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull_addr.2927650374
Short name T560
Test name
Test status
Simulation time 1017290843 ps
CPU time 2.96 seconds
Started Aug 21 08:26:36 AM UTC 24
Finished Aug 21 08:26:40 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2927650374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_nack_acqfull_addr.2927650374
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_nack_txstretch.3004066564
Short name T562
Test name
Test status
Simulation time 311540187 ps
CPU time 2.25 seconds
Started Aug 21 08:26:37 AM UTC 24
Finished Aug 21 08:26:40 AM UTC 24
Peak memory 233548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3004066564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_nack_txstretch.3004066564
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_perf.1061267276
Short name T552
Test name
Test status
Simulation time 587821373 ps
CPU time 5.4 seconds
Started Aug 21 08:26:28 AM UTC 24
Finished Aug 21 08:26:35 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1061267276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 13.i2c_target_perf.1061267276
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_smbus_maxlen.2902309756
Short name T563
Test name
Test status
Simulation time 387347907 ps
CPU time 3.61 seconds
Started Aug 21 08:26:36 AM UTC 24
Finished Aug 21 08:26:41 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2902309756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 13.i2c_target_smbus_maxlen.2902309756
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_smoke.3942570172
Short name T554
Test name
Test status
Simulation time 2690850015 ps
CPU time 18.66 seconds
Started Aug 21 08:26:16 AM UTC 24
Finished Aug 21 08:26:36 AM UTC 24
Peak memory 227148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3942570172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_targ
et_smoke.3942570172
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.1879985085
Short name T843
Test name
Test status
Simulation time 53632783734 ps
CPU time 306.2 seconds
Started Aug 21 08:26:29 AM UTC 24
Finished Aug 21 08:31:39 AM UTC 24
Peak memory 4100332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1879985085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 13.i2c_target_stress_all.1879985085
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_stress_rd.4271423216
Short name T556
Test name
Test status
Simulation time 404147812 ps
CPU time 18.81 seconds
Started Aug 21 08:26:17 AM UTC 24
Finished Aug 21 08:26:37 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4271423216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stress_rd.4271423216
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_stress_wr.3688352066
Short name T571
Test name
Test status
Simulation time 17795258078 ps
CPU time 32.46 seconds
Started Aug 21 08:26:17 AM UTC 24
Finished Aug 21 08:26:51 AM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3688352066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stress_wr.3688352066
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_stretch.2538951086
Short name T145
Test name
Test status
Simulation time 2880857725 ps
CPU time 48 seconds
Started Aug 21 08:26:19 AM UTC 24
Finished Aug 21 08:27:09 AM UTC 24
Peak memory 516620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2538951086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_stretch.2538951086
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_timeout.803901199
Short name T547
Test name
Test status
Simulation time 11384207873 ps
CPU time 8.37 seconds
Started Aug 21 08:26:23 AM UTC 24
Finished Aug 21 08:26:32 AM UTC 24
Peak memory 243876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=803901199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_timeout.803901199
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/13.i2c_target_tx_stretch_ctrl.45053138
Short name T557
Test name
Test status
Simulation time 80683455 ps
CPU time 2.84 seconds
Started Aug 21 08:26:34 AM UTC 24
Finished Aug 21 08:26:38 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=45053138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_tx_stretch_ctrl.45053138
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_alert_test.42218339
Short name T587
Test name
Test status
Simulation time 17277529 ps
CPU time 0.85 seconds
Started Aug 21 08:27:05 AM UTC 24
Finished Aug 21 08:27:07 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42218339 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.42218339
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_error_intr.1299347100
Short name T569
Test name
Test status
Simulation time 692578270 ps
CPU time 4.75 seconds
Started Aug 21 08:26:42 AM UTC 24
Finished Aug 21 08:26:48 AM UTC 24
Peak memory 233644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1299347100 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1299347100
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_fmt_empty.1573734795
Short name T577
Test name
Test status
Simulation time 318510156 ps
CPU time 14.79 seconds
Started Aug 21 08:26:40 AM UTC 24
Finished Aug 21 08:26:56 AM UTC 24
Peak memory 286864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1573734795 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty.1573734795
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_full.2212419882
Short name T670
Test name
Test status
Simulation time 11524669156 ps
CPU time 102.65 seconds
Started Aug 21 08:26:41 AM UTC 24
Finished Aug 21 08:28:26 AM UTC 24
Peak memory 841932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212419882 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2212419882
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_overflow.995038278
Short name T574
Test name
Test status
Simulation time 7756839126 ps
CPU time 50.95 seconds
Started Aug 21 08:26:38 AM UTC 24
Finished Aug 21 08:27:31 AM UTC 24
Peak memory 752052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=995038278 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.995038278
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_fmt.1973705523
Short name T564
Test name
Test status
Simulation time 132199947 ps
CPU time 1.35 seconds
Started Aug 21 08:26:39 AM UTC 24
Finished Aug 21 08:26:41 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1973705523 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt.1973705523
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_rx.3087555972
Short name T570
Test name
Test status
Simulation time 477601415 ps
CPU time 9.41 seconds
Started Aug 21 08:26:40 AM UTC 24
Finished Aug 21 08:26:51 AM UTC 24
Peak memory 266392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3087555972 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.3087555972
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_watermark.2080452558
Short name T812
Test name
Test status
Simulation time 91862191680 ps
CPU time 262.05 seconds
Started Aug 21 08:26:38 AM UTC 24
Finished Aug 21 08:31:04 AM UTC 24
Peak memory 1392832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2080452558 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2080452558
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.2850646363
Short name T593
Test name
Test status
Simulation time 5507131213 ps
CPU time 23.62 seconds
Started Aug 21 08:26:58 AM UTC 24
Finished Aug 21 08:27:23 AM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2850646363 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2850646363
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_override.2609695324
Short name T159
Test name
Test status
Simulation time 44833958 ps
CPU time 0.99 seconds
Started Aug 21 08:26:38 AM UTC 24
Finished Aug 21 08:26:40 AM UTC 24
Peak memory 215068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2609695324 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.2609695324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_perf.3228237573
Short name T151
Test name
Test status
Simulation time 12650285149 ps
CPU time 30.33 seconds
Started Aug 21 08:26:41 AM UTC 24
Finished Aug 21 08:27:13 AM UTC 24
Peak memory 245968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3228237573 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3228237573
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_perf_precise.3305359960
Short name T568
Test name
Test status
Simulation time 684224082 ps
CPU time 3.79 seconds
Started Aug 21 08:26:41 AM UTC 24
Finished Aug 21 08:26:46 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3305359960 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.3305359960
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_smoke.473798849
Short name T596
Test name
Test status
Simulation time 1078354343 ps
CPU time 46.83 seconds
Started Aug 21 08:26:38 AM UTC 24
Finished Aug 21 08:27:26 AM UTC 24
Peak memory 292952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=473798849 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.473798849
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.406674127
Short name T572
Test name
Test status
Simulation time 7606834226 ps
CPU time 10.78 seconds
Started Aug 21 08:26:41 AM UTC 24
Finished Aug 21 08:26:54 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=406674127 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.406674127
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_bad_addr.1170971442
Short name T584
Test name
Test status
Simulation time 767433355 ps
CPU time 7.37 seconds
Started Aug 21 08:26:55 AM UTC 24
Finished Aug 21 08:27:04 AM UTC 24
Peak memory 227144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1170971442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1170971442
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.2261434136
Short name T578
Test name
Test status
Simulation time 296334586 ps
CPU time 3.57 seconds
Started Aug 21 08:26:52 AM UTC 24
Finished Aug 21 08:26:57 AM UTC 24
Peak memory 222708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2261434136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_acq.2261434136
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_tx.3248553504
Short name T579
Test name
Test status
Simulation time 217816468 ps
CPU time 2.12 seconds
Started Aug 21 08:26:54 AM UTC 24
Finished Aug 21 08:26:58 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3248553504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_fifo_reset_tx.3248553504
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_acq.2426109827
Short name T585
Test name
Test status
Simulation time 1213809340 ps
CPU time 4.53 seconds
Started Aug 21 08:26:59 AM UTC 24
Finished Aug 21 08:27:04 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2426109827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.2426109827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_tx.2826961642
Short name T581
Test name
Test status
Simulation time 2365969642 ps
CPU time 1.78 seconds
Started Aug 21 08:27:00 AM UTC 24
Finished Aug 21 08:27:03 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2826961642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.2826961642
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_intr_smoke.1129751581
Short name T573
Test name
Test status
Simulation time 2401962354 ps
CPU time 6.24 seconds
Started Aug 21 08:26:47 AM UTC 24
Finished Aug 21 08:26:55 AM UTC 24
Peak memory 231352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1129751581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.1129751581
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_intr_stress_wr.1486725790
Short name T600
Test name
Test status
Simulation time 18539383992 ps
CPU time 43.34 seconds
Started Aug 21 08:26:48 AM UTC 24
Finished Aug 21 08:27:33 AM UTC 24
Peak memory 739476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1486725790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1486725790
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull.2633884203
Short name T147
Test name
Test status
Simulation time 577623119 ps
CPU time 5.1 seconds
Started Aug 21 08:27:04 AM UTC 24
Finished Aug 21 08:27:10 AM UTC 24
Peak memory 226880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2633884203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 14.i2c_target_nack_acqfull.2633884203
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull_addr.3086949467
Short name T149
Test name
Test status
Simulation time 2105987269 ps
CPU time 4.26 seconds
Started Aug 21 08:27:05 AM UTC 24
Finished Aug 21 08:27:10 AM UTC 24
Peak memory 216456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3086949467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_nack_acqfull_addr.3086949467
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_nack_txstretch.336402281
Short name T589
Test name
Test status
Simulation time 462766771 ps
CPU time 1.97 seconds
Started Aug 21 08:27:05 AM UTC 24
Finished Aug 21 08:27:08 AM UTC 24
Peak memory 232680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=336402281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_nack_txstretch.336402281
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_perf.3379058388
Short name T586
Test name
Test status
Simulation time 16085891572 ps
CPU time 8.83 seconds
Started Aug 21 08:26:55 AM UTC 24
Finished Aug 21 08:27:05 AM UTC 24
Peak memory 231152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3379058388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 14.i2c_target_perf.3379058388
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_smbus_maxlen.1520528325
Short name T590
Test name
Test status
Simulation time 488967204 ps
CPU time 3.3 seconds
Started Aug 21 08:27:04 AM UTC 24
Finished Aug 21 08:27:08 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1520528325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 14.i2c_target_smbus_maxlen.1520528325
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_smoke.1762599624
Short name T588
Test name
Test status
Simulation time 6414011365 ps
CPU time 23.24 seconds
Started Aug 21 08:26:43 AM UTC 24
Finished Aug 21 08:27:07 AM UTC 24
Peak memory 227172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1762599624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_targ
et_smoke.1762599624
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_stress_all.2193293232
Short name T875
Test name
Test status
Simulation time 31116503461 ps
CPU time 312.52 seconds
Started Aug 21 08:26:55 AM UTC 24
Finished Aug 21 08:32:12 AM UTC 24
Peak memory 2564372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2193293232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 14.i2c_target_stress_all.2193293232
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_stress_rd.506578145
Short name T598
Test name
Test status
Simulation time 1198386064 ps
CPU time 39.53 seconds
Started Aug 21 08:26:46 AM UTC 24
Finished Aug 21 08:27:27 AM UTC 24
Peak memory 226880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=506578145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stress_rd.506578145
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.464013566
Short name T716
Test name
Test status
Simulation time 54103341131 ps
CPU time 145.88 seconds
Started Aug 21 08:26:43 AM UTC 24
Finished Aug 21 08:29:11 AM UTC 24
Peak memory 2240668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=464013566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stress_wr.464013566
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_stretch.379143985
Short name T582
Test name
Test status
Simulation time 4227682620 ps
CPU time 15.56 seconds
Started Aug 21 08:26:46 AM UTC 24
Finished Aug 21 08:27:03 AM UTC 24
Peak memory 452836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=379143985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_stretch.379143985
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/14.i2c_target_timeout.2523381061
Short name T580
Test name
Test status
Simulation time 10768104399 ps
CPU time 8.18 seconds
Started Aug 21 08:26:52 AM UTC 24
Finished Aug 21 08:27:02 AM UTC 24
Peak memory 227212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2523381061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_timeout.2523381061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/14.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_alert_test.2094340944
Short name T609
Test name
Test status
Simulation time 43713493 ps
CPU time 0.97 seconds
Started Aug 21 08:27:38 AM UTC 24
Finished Aug 21 08:27:40 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2094340944 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2094340944
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_error_intr.541448761
Short name T592
Test name
Test status
Simulation time 419351921 ps
CPU time 5.55 seconds
Started Aug 21 08:27:13 AM UTC 24
Finished Aug 21 08:27:20 AM UTC 24
Peak memory 233368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=541448761 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.541448761
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_fmt_empty.993639276
Short name T597
Test name
Test status
Simulation time 1045925251 ps
CPU time 15.98 seconds
Started Aug 21 08:27:10 AM UTC 24
Finished Aug 21 08:27:27 AM UTC 24
Peak memory 276516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=993639276 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty.993639276
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_full.3783817223
Short name T712
Test name
Test status
Simulation time 2027217994 ps
CPU time 115.68 seconds
Started Aug 21 08:27:11 AM UTC 24
Finished Aug 21 08:29:09 AM UTC 24
Peak memory 387152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3783817223 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3783817223
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_overflow.4021353
Short name T602
Test name
Test status
Simulation time 2303960456 ps
CPU time 76.57 seconds
Started Aug 21 08:27:09 AM UTC 24
Finished Aug 21 08:28:28 AM UTC 24
Peak memory 780460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4021353 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.4021353
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_fmt.1321275677
Short name T150
Test name
Test status
Simulation time 102812251 ps
CPU time 1.59 seconds
Started Aug 21 08:27:10 AM UTC 24
Finished Aug 21 08:27:12 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1321275677 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt.1321275677
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_rx.351688589
Short name T153
Test name
Test status
Simulation time 129024030 ps
CPU time 5.36 seconds
Started Aug 21 08:27:10 AM UTC 24
Finished Aug 21 08:27:16 AM UTC 24
Peak memory 235872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=351688589 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.351688589
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_watermark.3703877326
Short name T841
Test name
Test status
Simulation time 4118653786 ps
CPU time 266.51 seconds
Started Aug 21 08:27:08 AM UTC 24
Finished Aug 21 08:31:39 AM UTC 24
Peak memory 1269920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3703877326 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3703877326
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_may_nack.1871906816
Short name T626
Test name
Test status
Simulation time 340946522 ps
CPU time 14.24 seconds
Started Aug 21 08:27:34 AM UTC 24
Finished Aug 21 08:27:50 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1871906816 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1871906816
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_override.2080405166
Short name T148
Test name
Test status
Simulation time 131373857 ps
CPU time 1.09 seconds
Started Aug 21 08:27:08 AM UTC 24
Finished Aug 21 08:27:10 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2080405166 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2080405166
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_perf.3576971417
Short name T638
Test name
Test status
Simulation time 7226991166 ps
CPU time 48.45 seconds
Started Aug 21 08:27:11 AM UTC 24
Finished Aug 21 08:28:01 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3576971417 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3576971417
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_perf_precise.2753290906
Short name T591
Test name
Test status
Simulation time 221826542 ps
CPU time 4.94 seconds
Started Aug 21 08:27:11 AM UTC 24
Finished Aug 21 08:27:17 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2753290906 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.2753290906
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_smoke.3484505575
Short name T599
Test name
Test status
Simulation time 1823927922 ps
CPU time 28.28 seconds
Started Aug 21 08:27:06 AM UTC 24
Finished Aug 21 08:27:36 AM UTC 24
Peak memory 354444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3484505575 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3484505575
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_host_stretch_timeout.2575655467
Short name T595
Test name
Test status
Simulation time 3121778105 ps
CPU time 11.31 seconds
Started Aug 21 08:27:12 AM UTC 24
Finished Aug 21 08:27:24 AM UTC 24
Peak memory 233652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2575655467 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.2575655467
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_bad_addr.3376811535
Short name T607
Test name
Test status
Simulation time 5909014891 ps
CPU time 4.22 seconds
Started Aug 21 08:27:32 AM UTC 24
Finished Aug 21 08:27:37 AM UTC 24
Peak memory 231176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3376811535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3376811535
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_acq.3582766598
Short name T313
Test name
Test status
Simulation time 260206931 ps
CPU time 2.63 seconds
Started Aug 21 08:27:28 AM UTC 24
Finished Aug 21 08:27:31 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3582766598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_acq.3582766598
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_tx.1489929319
Short name T583
Test name
Test status
Simulation time 462429083 ps
CPU time 1.11 seconds
Started Aug 21 08:27:28 AM UTC 24
Finished Aug 21 08:27:30 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1489929319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_fifo_reset_tx.1489929319
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_acq.2934533618
Short name T613
Test name
Test status
Simulation time 371016100 ps
CPU time 4.01 seconds
Started Aug 21 08:27:37 AM UTC 24
Finished Aug 21 08:27:42 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2934533618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.2934533618
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_tx.1101269312
Short name T611
Test name
Test status
Simulation time 166854963 ps
CPU time 2.43 seconds
Started Aug 21 08:27:38 AM UTC 24
Finished Aug 21 08:27:41 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1101269312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.1101269312
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_intr_smoke.2996471197
Short name T146
Test name
Test status
Simulation time 2196268313 ps
CPU time 7.45 seconds
Started Aug 21 08:27:23 AM UTC 24
Finished Aug 21 08:27:32 AM UTC 24
Peak memory 227208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2996471197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.2996471197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_intr_stress_wr.2283243614
Short name T733
Test name
Test status
Simulation time 14440347691 ps
CPU time 126.31 seconds
Started Aug 21 08:27:24 AM UTC 24
Finished Aug 21 08:29:33 AM UTC 24
Peak memory 2029736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2283243614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2283243614
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull.4106213421
Short name T617
Test name
Test status
Simulation time 4512374922 ps
CPU time 3.35 seconds
Started Aug 21 08:27:38 AM UTC 24
Finished Aug 21 08:27:42 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4106213421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 15.i2c_target_nack_acqfull.4106213421
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull_addr.1856612971
Short name T615
Test name
Test status
Simulation time 517005161 ps
CPU time 2.87 seconds
Started Aug 21 08:27:38 AM UTC 24
Finished Aug 21 08:27:42 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1856612971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_nack_acqfull_addr.1856612971
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_nack_txstretch.4044404977
Short name T612
Test name
Test status
Simulation time 149211246 ps
CPU time 2.5 seconds
Started Aug 21 08:27:38 AM UTC 24
Finished Aug 21 08:27:41 AM UTC 24
Peak memory 233400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4044404977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_nack_txstretch.4044404977
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_smbus_maxlen.4196619370
Short name T618
Test name
Test status
Simulation time 2133540531 ps
CPU time 3.65 seconds
Started Aug 21 08:27:38 AM UTC 24
Finished Aug 21 08:27:42 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4196619370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 15.i2c_target_smbus_maxlen.4196619370
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_smoke.72786524
Short name T608
Test name
Test status
Simulation time 5868620164 ps
CPU time 21.1 seconds
Started Aug 21 08:27:16 AM UTC 24
Finished Aug 21 08:27:38 AM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=72786524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target
_smoke.72786524
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_stress_all.1287747843
Short name T688
Test name
Test status
Simulation time 45772425794 ps
CPU time 73.78 seconds
Started Aug 21 08:27:31 AM UTC 24
Finished Aug 21 08:28:46 AM UTC 24
Peak memory 772440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1287747843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 15.i2c_target_stress_all.1287747843
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_stress_rd.1096972962
Short name T604
Test name
Test status
Simulation time 408623642 ps
CPU time 17.61 seconds
Started Aug 21 08:27:18 AM UTC 24
Finished Aug 21 08:27:37 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1096972962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stress_rd.1096972962
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_stress_wr.2282812097
Short name T605
Test name
Test status
Simulation time 21126815219 ps
CPU time 18.69 seconds
Started Aug 21 08:27:17 AM UTC 24
Finished Aug 21 08:27:37 AM UTC 24
Peak memory 216704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2282812097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stress_wr.2282812097
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_stretch.1089739453
Short name T628
Test name
Test status
Simulation time 2411985201 ps
CPU time 29.61 seconds
Started Aug 21 08:27:20 AM UTC 24
Finished Aug 21 08:27:51 AM UTC 24
Peak memory 364752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1089739453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_stretch.1089739453
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_timeout.452431969
Short name T550
Test name
Test status
Simulation time 3144149932 ps
CPU time 7.9 seconds
Started Aug 21 08:27:26 AM UTC 24
Finished Aug 21 08:27:35 AM UTC 24
Peak memory 233884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=452431969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_timeout.452431969
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/15.i2c_target_tx_stretch_ctrl.2045703801
Short name T621
Test name
Test status
Simulation time 254893656 ps
CPU time 7.24 seconds
Started Aug 21 08:27:38 AM UTC 24
Finished Aug 21 08:27:46 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2045703801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.2045703801
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_alert_test.3937041612
Short name T647
Test name
Test status
Simulation time 50425396 ps
CPU time 0.88 seconds
Started Aug 21 08:28:02 AM UTC 24
Finished Aug 21 08:28:04 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3937041612 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3937041612
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_error_intr.3873286549
Short name T629
Test name
Test status
Simulation time 541087865 ps
CPU time 5.62 seconds
Started Aug 21 08:27:46 AM UTC 24
Finished Aug 21 08:27:52 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3873286549 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3873286549
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_fmt_empty.281480842
Short name T623
Test name
Test status
Simulation time 1035940230 ps
CPU time 4.04 seconds
Started Aug 21 08:27:42 AM UTC 24
Finished Aug 21 08:27:48 AM UTC 24
Peak memory 249788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=281480842 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empty.281480842
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_full.1528849006
Short name T708
Test name
Test status
Simulation time 5149580884 ps
CPU time 80.59 seconds
Started Aug 21 08:27:42 AM UTC 24
Finished Aug 21 08:29:05 AM UTC 24
Peak memory 559572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1528849006 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1528849006
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_overflow.161220302
Short name T787
Test name
Test status
Simulation time 5086044585 ps
CPU time 174.73 seconds
Started Aug 21 08:27:42 AM UTC 24
Finished Aug 21 08:30:40 AM UTC 24
Peak memory 854224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=161220302 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.161220302
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_fmt.3989390492
Short name T619
Test name
Test status
Simulation time 115622922 ps
CPU time 1.33 seconds
Started Aug 21 08:27:42 AM UTC 24
Finished Aug 21 08:27:45 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3989390492 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt.3989390492
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_rx.2248987602
Short name T624
Test name
Test status
Simulation time 531923145 ps
CPU time 5.1 seconds
Started Aug 21 08:27:42 AM UTC 24
Finished Aug 21 08:27:49 AM UTC 24
Peak memory 239704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2248987602 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.2248987602
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_watermark.654374576
Short name T847
Test name
Test status
Simulation time 20661819441 ps
CPU time 238.06 seconds
Started Aug 21 08:27:42 AM UTC 24
Finished Aug 21 08:31:44 AM UTC 24
Peak memory 1276356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=654374576 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.654374576
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_may_nack.416000973
Short name T645
Test name
Test status
Simulation time 1280627787 ps
CPU time 4.26 seconds
Started Aug 21 08:27:58 AM UTC 24
Finished Aug 21 08:28:03 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=416000973 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.416000973
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_mode_toggle.1090291165
Short name T84
Test name
Test status
Simulation time 299753124 ps
CPU time 1.69 seconds
Started Aug 21 08:27:57 AM UTC 24
Finished Aug 21 08:28:00 AM UTC 24
Peak memory 226440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1090291165 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1090291165
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_override.3594126140
Short name T616
Test name
Test status
Simulation time 84236440 ps
CPU time 1.01 seconds
Started Aug 21 08:27:40 AM UTC 24
Finished Aug 21 08:27:42 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3594126140 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.3594126140
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_perf.1273297156
Short name T648
Test name
Test status
Simulation time 5449939591 ps
CPU time 18.52 seconds
Started Aug 21 08:27:45 AM UTC 24
Finished Aug 21 08:28:04 AM UTC 24
Peak memory 245988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1273297156 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1273297156
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_perf_precise.3608598266
Short name T625
Test name
Test status
Simulation time 64053506 ps
CPU time 3.16 seconds
Started Aug 21 08:27:45 AM UTC 24
Finished Aug 21 08:27:49 AM UTC 24
Peak memory 233024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608598266 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.3608598266
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_smoke.1871647414
Short name T665
Test name
Test status
Simulation time 1800839111 ps
CPU time 39.66 seconds
Started Aug 21 08:27:40 AM UTC 24
Finished Aug 21 08:28:21 AM UTC 24
Peak memory 325720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1871647414 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1871647414
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_stress_all.1649410986
Short name T126
Test name
Test status
Simulation time 24677342354 ps
CPU time 472.65 seconds
Started Aug 21 08:27:46 AM UTC 24
Finished Aug 21 08:35:44 AM UTC 24
Peak memory 2357580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1649410986 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.1649410986
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_host_stretch_timeout.2471080379
Short name T674
Test name
Test status
Simulation time 1051538865 ps
CPU time 43.95 seconds
Started Aug 21 08:27:45 AM UTC 24
Finished Aug 21 08:28:30 AM UTC 24
Peak memory 226880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471080379 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2471080379
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_bad_addr.3531432996
Short name T642
Test name
Test status
Simulation time 4847059036 ps
CPU time 6.81 seconds
Started Aug 21 08:27:55 AM UTC 24
Finished Aug 21 08:28:03 AM UTC 24
Peak memory 233184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3531432996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3531432996
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_acq.455456367
Short name T630
Test name
Test status
Simulation time 176310710 ps
CPU time 1.96 seconds
Started Aug 21 08:27:50 AM UTC 24
Finished Aug 21 08:27:53 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=455456367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_fifo_reset_acq.455456367
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_tx.2661972641
Short name T634
Test name
Test status
Simulation time 1118721972 ps
CPU time 3.62 seconds
Started Aug 21 08:27:52 AM UTC 24
Finished Aug 21 08:27:57 AM UTC 24
Peak memory 233568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2661972641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_fifo_reset_tx.2661972641
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_acq.4031518063
Short name T641
Test name
Test status
Simulation time 508140500 ps
CPU time 2.91 seconds
Started Aug 21 08:27:58 AM UTC 24
Finished Aug 21 08:28:02 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4031518063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.4031518063
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_tx.2762327743
Short name T644
Test name
Test status
Simulation time 494117073 ps
CPU time 1.57 seconds
Started Aug 21 08:28:00 AM UTC 24
Finished Aug 21 08:28:03 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2762327743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.2762327743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_intr_smoke.3208342527
Short name T633
Test name
Test status
Simulation time 866986634 ps
CPU time 7.01 seconds
Started Aug 21 08:27:49 AM UTC 24
Finished Aug 21 08:27:57 AM UTC 24
Peak memory 233580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3208342527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.3208342527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_intr_stress_wr.1436132516
Short name T667
Test name
Test status
Simulation time 18877596828 ps
CPU time 32.71 seconds
Started Aug 21 08:27:49 AM UTC 24
Finished Aug 21 08:28:23 AM UTC 24
Peak memory 571632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1436132516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.1436132516
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull.2829065128
Short name T652
Test name
Test status
Simulation time 551467849 ps
CPU time 4.42 seconds
Started Aug 21 08:28:01 AM UTC 24
Finished Aug 21 08:28:07 AM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2829065128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 16.i2c_target_nack_acqfull.2829065128
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull_addr.1809379381
Short name T649
Test name
Test status
Simulation time 508943218 ps
CPU time 2.54 seconds
Started Aug 21 08:28:01 AM UTC 24
Finished Aug 21 08:28:05 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1809379381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_nack_acqfull_addr.1809379381
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_nack_txstretch.4235876729
Short name T650
Test name
Test status
Simulation time 455705525 ps
CPU time 1.57 seconds
Started Aug 21 08:28:02 AM UTC 24
Finished Aug 21 08:28:05 AM UTC 24
Peak memory 232576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4235876729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_nack_txstretch.4235876729
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_perf.2782510701
Short name T643
Test name
Test status
Simulation time 829008726 ps
CPU time 7.93 seconds
Started Aug 21 08:27:54 AM UTC 24
Finished Aug 21 08:28:03 AM UTC 24
Peak memory 230908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2782510701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 16.i2c_target_perf.2782510701
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_smbus_maxlen.992349882
Short name T651
Test name
Test status
Simulation time 485680389 ps
CPU time 3.63 seconds
Started Aug 21 08:28:00 AM UTC 24
Finished Aug 21 08:28:05 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=992349882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 16.i2c_target_smbus_maxlen.992349882
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_smoke.3747397765
Short name T646
Test name
Test status
Simulation time 2316378451 ps
CPU time 14.65 seconds
Started Aug 21 08:27:48 AM UTC 24
Finished Aug 21 08:28:04 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3747397765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_targ
et_smoke.3747397765
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_stress_all.1021114657
Short name T946
Test name
Test status
Simulation time 27068238684 ps
CPU time 332.41 seconds
Started Aug 21 08:27:55 AM UTC 24
Finished Aug 21 08:33:31 AM UTC 24
Peak memory 4106396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1021114657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 16.i2c_target_stress_all.1021114657
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_stress_rd.1335202876
Short name T653
Test name
Test status
Simulation time 1513666867 ps
CPU time 17.97 seconds
Started Aug 21 08:27:48 AM UTC 24
Finished Aug 21 08:28:07 AM UTC 24
Peak memory 233900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1335202876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stress_rd.1335202876
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_stress_wr.479530686
Short name T1216
Test name
Test status
Simulation time 46881256926 ps
CPU time 595.01 seconds
Started Aug 21 08:27:48 AM UTC 24
Finished Aug 21 08:37:49 AM UTC 24
Peak memory 7119000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=479530686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stress_wr.479530686
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_stretch.2061641546
Short name T659
Test name
Test status
Simulation time 1117743193 ps
CPU time 24.86 seconds
Started Aug 21 08:27:48 AM UTC 24
Finished Aug 21 08:28:14 AM UTC 24
Peak memory 301356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2061641546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_stretch.2061641546
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_timeout.2197138076
Short name T637
Test name
Test status
Simulation time 2823234398 ps
CPU time 9.55 seconds
Started Aug 21 08:27:49 AM UTC 24
Finished Aug 21 08:28:00 AM UTC 24
Peak memory 233668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2197138076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_timeout.2197138076
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/16.i2c_target_tx_stretch_ctrl.345186098
Short name T654
Test name
Test status
Simulation time 433374641 ps
CPU time 6.39 seconds
Started Aug 21 08:28:00 AM UTC 24
Finished Aug 21 08:28:08 AM UTC 24
Peak memory 216848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=345186098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_tx_stretch_ctrl.345186098
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_alert_test.3254363649
Short name T676
Test name
Test status
Simulation time 34904483 ps
CPU time 0.92 seconds
Started Aug 21 08:28:29 AM UTC 24
Finished Aug 21 08:28:31 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3254363649 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3254363649
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_error_intr.4071679884
Short name T658
Test name
Test status
Simulation time 165541671 ps
CPU time 3.28 seconds
Started Aug 21 08:28:07 AM UTC 24
Finished Aug 21 08:28:11 AM UTC 24
Peak memory 243532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4071679884 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.4071679884
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_fmt_empty.77948937
Short name T661
Test name
Test status
Simulation time 8877714137 ps
CPU time 12.55 seconds
Started Aug 21 08:28:05 AM UTC 24
Finished Aug 21 08:28:18 AM UTC 24
Peak memory 307364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=77948937 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty.77948937
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_full.3279931066
Short name T757
Test name
Test status
Simulation time 3664257389 ps
CPU time 111.52 seconds
Started Aug 21 08:28:06 AM UTC 24
Finished Aug 21 08:30:00 AM UTC 24
Peak memory 469228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3279931066 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3279931066
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_overflow.2776196527
Short name T721
Test name
Test status
Simulation time 27530742580 ps
CPU time 72.61 seconds
Started Aug 21 08:28:04 AM UTC 24
Finished Aug 21 08:29:18 AM UTC 24
Peak memory 745672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2776196527 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2776196527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_rx.1401370879
Short name T656
Test name
Test status
Simulation time 395046807 ps
CPU time 4.4 seconds
Started Aug 21 08:28:05 AM UTC 24
Finished Aug 21 08:28:10 AM UTC 24
Peak memory 216856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1401370879 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.1401370879
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_watermark.2596967031
Short name T853
Test name
Test status
Simulation time 3850385989 ps
CPU time 226.17 seconds
Started Aug 21 08:28:04 AM UTC 24
Finished Aug 21 08:31:53 AM UTC 24
Peak memory 1198420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2596967031 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2596967031
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_may_nack.3988609016
Short name T669
Test name
Test status
Simulation time 834291983 ps
CPU time 5.81 seconds
Started Aug 21 08:28:21 AM UTC 24
Finished Aug 21 08:28:28 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3988609016 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3988609016
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_override.2616448783
Short name T160
Test name
Test status
Simulation time 31875566 ps
CPU time 1.06 seconds
Started Aug 21 08:28:04 AM UTC 24
Finished Aug 21 08:28:06 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2616448783 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2616448783
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_perf_precise.2892320405
Short name T657
Test name
Test status
Simulation time 92719057 ps
CPU time 4.28 seconds
Started Aug 21 08:28:06 AM UTC 24
Finished Aug 21 08:28:11 AM UTC 24
Peak memory 235132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2892320405 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.2892320405
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_smoke.3343550072
Short name T702
Test name
Test status
Simulation time 1230714298 ps
CPU time 56.11 seconds
Started Aug 21 08:28:03 AM UTC 24
Finished Aug 21 08:29:01 AM UTC 24
Peak memory 325740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3343550072 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3343550072
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_stress_all.4087988516
Short name T299
Test name
Test status
Simulation time 28553816149 ps
CPU time 1197.27 seconds
Started Aug 21 08:28:07 AM UTC 24
Finished Aug 21 08:48:18 AM UTC 24
Peak memory 2531812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4087988516 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.4087988516
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_host_stretch_timeout.3339953480
Short name T684
Test name
Test status
Simulation time 3211004373 ps
CPU time 30.2 seconds
Started Aug 21 08:28:06 AM UTC 24
Finished Aug 21 08:28:38 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3339953480 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3339953480
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_bad_addr.2987739503
Short name T610
Test name
Test status
Simulation time 986816762 ps
CPU time 8.07 seconds
Started Aug 21 08:28:19 AM UTC 24
Finished Aug 21 08:28:28 AM UTC 24
Peak memory 226848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=2987739503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2987739503
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_tx.3956471137
Short name T664
Test name
Test status
Simulation time 262411106 ps
CPU time 2.01 seconds
Started Aug 21 08:28:17 AM UTC 24
Finished Aug 21 08:28:20 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3956471137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_fifo_reset_tx.3956471137
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_acq.3182643062
Short name T308
Test name
Test status
Simulation time 589720469 ps
CPU time 4.65 seconds
Started Aug 21 08:28:22 AM UTC 24
Finished Aug 21 08:28:29 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3182643062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.3182643062
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_tx.3215441104
Short name T671
Test name
Test status
Simulation time 1143977827 ps
CPU time 2.38 seconds
Started Aug 21 08:28:23 AM UTC 24
Finished Aug 21 08:28:27 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3215441104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.3215441104
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_hrst.2378751300
Short name T668
Test name
Test status
Simulation time 401524428 ps
CPU time 3.4 seconds
Started Aug 21 08:28:20 AM UTC 24
Finished Aug 21 08:28:25 AM UTC 24
Peak memory 228816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2378751300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 17.i2c_target_hrst.2378751300
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_intr_smoke.473514651
Short name T662
Test name
Test status
Simulation time 2386886729 ps
CPU time 6.65 seconds
Started Aug 21 08:28:11 AM UTC 24
Finished Aug 21 08:28:19 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=473514651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 17.i2c_target_intr_smoke.473514651
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_intr_stress_wr.3871758669
Short name T672
Test name
Test status
Simulation time 18272818663 ps
CPU time 14.38 seconds
Started Aug 21 08:28:13 AM UTC 24
Finished Aug 21 08:28:28 AM UTC 24
Peak memory 360660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3871758669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.3871758669
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull.412526222
Short name T678
Test name
Test status
Simulation time 3533929262 ps
CPU time 3.67 seconds
Started Aug 21 08:28:27 AM UTC 24
Finished Aug 21 08:28:32 AM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=412526222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 17.i2c_target_nack_acqfull.412526222
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_nack_txstretch.4131910190
Short name T679
Test name
Test status
Simulation time 158506308 ps
CPU time 2.56 seconds
Started Aug 21 08:28:28 AM UTC 24
Finished Aug 21 08:28:32 AM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4131910190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_nack_txstretch.4131910190
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_perf.2379599825
Short name T640
Test name
Test status
Simulation time 3879589318 ps
CPU time 8.92 seconds
Started Aug 21 08:28:18 AM UTC 24
Finished Aug 21 08:28:28 AM UTC 24
Peak memory 231248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2379599825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 17.i2c_target_perf.2379599825
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_smbus_maxlen.2744682581
Short name T675
Test name
Test status
Simulation time 9093139744 ps
CPU time 3.08 seconds
Started Aug 21 08:28:26 AM UTC 24
Finished Aug 21 08:28:30 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2744682581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 17.i2c_target_smbus_maxlen.2744682581
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_smoke.1628946624
Short name T295
Test name
Test status
Simulation time 1891678590 ps
CPU time 19.54 seconds
Started Aug 21 08:28:08 AM UTC 24
Finished Aug 21 08:28:29 AM UTC 24
Peak memory 227020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1628946624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_targ
et_smoke.1628946624
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_stress_all.85343967
Short name T744
Test name
Test status
Simulation time 66267389131 ps
CPU time 78.08 seconds
Started Aug 21 08:28:19 AM UTC 24
Finished Aug 21 08:29:39 AM UTC 24
Peak memory 299168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=85343967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_stress_all.85343967
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_stress_rd.3283035729
Short name T726
Test name
Test status
Simulation time 1762530027 ps
CPU time 74.69 seconds
Started Aug 21 08:28:08 AM UTC 24
Finished Aug 21 08:29:25 AM UTC 24
Peak memory 228864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3283035729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stress_rd.3283035729
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_stress_wr.1112583217
Short name T1626
Test name
Test status
Simulation time 56837498474 ps
CPU time 1099.62 seconds
Started Aug 21 08:28:08 AM UTC 24
Finished Aug 21 08:46:38 AM UTC 24
Peak memory 9662680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1112583217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stress_wr.1112583217
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_stretch.3228171930
Short name T660
Test name
Test status
Simulation time 3541286441 ps
CPU time 5.01 seconds
Started Aug 21 08:28:09 AM UTC 24
Finished Aug 21 08:28:16 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3228171930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_stretch.3228171930
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_timeout.4255088225
Short name T666
Test name
Test status
Simulation time 3199660723 ps
CPU time 9.07 seconds
Started Aug 21 08:28:13 AM UTC 24
Finished Aug 21 08:28:23 AM UTC 24
Peak memory 227264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4255088225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_timeout.4255088225
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/17.i2c_target_tx_stretch_ctrl.1988966968
Short name T681
Test name
Test status
Simulation time 437250151 ps
CPU time 8.48 seconds
Started Aug 21 08:28:24 AM UTC 24
Finished Aug 21 08:28:34 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1988966968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.1988966968
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_alert_test.9521849
Short name T703
Test name
Test status
Simulation time 31989683 ps
CPU time 0.89 seconds
Started Aug 21 08:29:00 AM UTC 24
Finished Aug 21 08:29:02 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=9521849 -assert nop
ostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.9521849
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_error_intr.2809340235
Short name T686
Test name
Test status
Simulation time 253995637 ps
CPU time 6.96 seconds
Started Aug 21 08:28:33 AM UTC 24
Finished Aug 21 08:28:41 AM UTC 24
Peak memory 260464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2809340235 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2809340235
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_fmt_empty.3580784473
Short name T685
Test name
Test status
Simulation time 1095651342 ps
CPU time 6.3 seconds
Started Aug 21 08:28:30 AM UTC 24
Finished Aug 21 08:28:38 AM UTC 24
Peak memory 266340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3580784473 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty.3580784473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_full.480764748
Short name T790
Test name
Test status
Simulation time 5722099619 ps
CPU time 128.29 seconds
Started Aug 21 08:28:31 AM UTC 24
Finished Aug 21 08:30:42 AM UTC 24
Peak memory 266520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=480764748 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.480764748
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_overflow.1556439314
Short name T752
Test name
Test status
Simulation time 20723571574 ps
CPU time 83.54 seconds
Started Aug 21 08:28:29 AM UTC 24
Finished Aug 21 08:29:55 AM UTC 24
Peak memory 587988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1556439314 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1556439314
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_fmt.2972886374
Short name T680
Test name
Test status
Simulation time 113357359 ps
CPU time 1.13 seconds
Started Aug 21 08:28:30 AM UTC 24
Finished Aug 21 08:28:33 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2972886374 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt.2972886374
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_rx.3402718622
Short name T683
Test name
Test status
Simulation time 579435205 ps
CPU time 5.01 seconds
Started Aug 21 08:28:31 AM UTC 24
Finished Aug 21 08:28:37 AM UTC 24
Peak memory 241616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3402718622 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.3402718622
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_watermark.2229506999
Short name T123
Test name
Test status
Simulation time 11033301240 ps
CPU time 136.25 seconds
Started Aug 21 08:28:29 AM UTC 24
Finished Aug 21 08:30:48 AM UTC 24
Peak memory 1517664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2229506999 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2229506999
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_may_nack.2400798615
Short name T701
Test name
Test status
Simulation time 613703922 ps
CPU time 5.84 seconds
Started Aug 21 08:28:54 AM UTC 24
Finished Aug 21 08:29:01 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2400798615 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2400798615
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_override.3524988701
Short name T677
Test name
Test status
Simulation time 36374016 ps
CPU time 0.91 seconds
Started Aug 21 08:28:29 AM UTC 24
Finished Aug 21 08:28:31 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3524988701 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.3524988701
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_perf.1466668887
Short name T714
Test name
Test status
Simulation time 2578480906 ps
CPU time 36.41 seconds
Started Aug 21 08:28:32 AM UTC 24
Finished Aug 21 08:29:10 AM UTC 24
Peak memory 252068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1466668887 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1466668887
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_perf_precise.1183750628
Short name T682
Test name
Test status
Simulation time 238377781 ps
CPU time 2.15 seconds
Started Aug 21 08:28:32 AM UTC 24
Finished Aug 21 08:28:36 AM UTC 24
Peak memory 239072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1183750628 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.1183750628
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_smoke.2761050994
Short name T603
Test name
Test status
Simulation time 6647295881 ps
CPU time 69.85 seconds
Started Aug 21 08:28:29 AM UTC 24
Finished Aug 21 08:29:41 AM UTC 24
Peak memory 338092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2761050994 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2761050994
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_host_stretch_timeout.2931377609
Short name T698
Test name
Test status
Simulation time 829039089 ps
CPU time 24.28 seconds
Started Aug 21 08:28:33 AM UTC 24
Finished Aug 21 08:28:58 AM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2931377609 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.2931377609
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_bad_addr.1157903715
Short name T697
Test name
Test status
Simulation time 3830514011 ps
CPU time 7.15 seconds
Started Aug 21 08:28:49 AM UTC 24
Finished Aug 21 08:28:58 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1157903715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.1157903715
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_acq.3433820630
Short name T689
Test name
Test status
Simulation time 434124062 ps
CPU time 1.88 seconds
Started Aug 21 08:28:44 AM UTC 24
Finished Aug 21 08:28:47 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3433820630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_acq.3433820630
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_tx.2885491656
Short name T691
Test name
Test status
Simulation time 120052955 ps
CPU time 1.74 seconds
Started Aug 21 08:28:46 AM UTC 24
Finished Aug 21 08:28:50 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2885491656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_fifo_reset_tx.2885491656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_acq.1481483087
Short name T700
Test name
Test status
Simulation time 334342799 ps
CPU time 3.75 seconds
Started Aug 21 08:28:55 AM UTC 24
Finished Aug 21 08:29:00 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1481483087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.1481483087
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_tx.1602248239
Short name T699
Test name
Test status
Simulation time 331617962 ps
CPU time 2.44 seconds
Started Aug 21 08:28:55 AM UTC 24
Finished Aug 21 08:28:58 AM UTC 24
Peak memory 216436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1602248239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.1602248239
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_hrst.1968995615
Short name T694
Test name
Test status
Simulation time 378245866 ps
CPU time 2.03 seconds
Started Aug 21 08:28:51 AM UTC 24
Finished Aug 21 08:28:54 AM UTC 24
Peak memory 227092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1968995615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 18.i2c_target_hrst.1968995615
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_intr_smoke.2360493244
Short name T693
Test name
Test status
Simulation time 5090049618 ps
CPU time 12.4 seconds
Started Aug 21 08:28:39 AM UTC 24
Finished Aug 21 08:28:53 AM UTC 24
Peak memory 244124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2360493244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_intr_smoke.2360493244
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_intr_stress_wr.1549984942
Short name T1079
Test name
Test status
Simulation time 25337487881 ps
CPU time 403.59 seconds
Started Aug 21 08:28:39 AM UTC 24
Finished Aug 21 08:35:27 AM UTC 24
Peak memory 6207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1549984942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.1549984942
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull.374077202
Short name T710
Test name
Test status
Simulation time 682454458 ps
CPU time 5.32 seconds
Started Aug 21 08:28:59 AM UTC 24
Finished Aug 21 08:29:05 AM UTC 24
Peak memory 226736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=374077202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 18.i2c_target_nack_acqfull.374077202
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull_addr.3042712119
Short name T709
Test name
Test status
Simulation time 6774125794 ps
CPU time 5.06 seconds
Started Aug 21 08:28:59 AM UTC 24
Finished Aug 21 08:29:05 AM UTC 24
Peak memory 216720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3042712119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_nack_acqfull_addr.3042712119
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_nack_txstretch.3473698444
Short name T706
Test name
Test status
Simulation time 524456747 ps
CPU time 2.45 seconds
Started Aug 21 08:28:59 AM UTC 24
Finished Aug 21 08:29:03 AM UTC 24
Peak memory 233756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3473698444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_nack_txstretch.3473698444
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_perf.4288967580
Short name T696
Test name
Test status
Simulation time 799881491 ps
CPU time 7.14 seconds
Started Aug 21 08:28:47 AM UTC 24
Finished Aug 21 08:28:56 AM UTC 24
Peak memory 233684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4288967580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 18.i2c_target_perf.4288967580
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_smbus_maxlen.1124246764
Short name T704
Test name
Test status
Simulation time 569927819 ps
CPU time 4.23 seconds
Started Aug 21 08:28:57 AM UTC 24
Finished Aug 21 08:29:02 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1124246764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 18.i2c_target_smbus_maxlen.1124246764
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_smoke.1479165468
Short name T690
Test name
Test status
Simulation time 3605628990 ps
CPU time 13.7 seconds
Started Aug 21 08:28:34 AM UTC 24
Finished Aug 21 08:28:49 AM UTC 24
Peak memory 226972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1479165468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_targ
et_smoke.1479165468
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.3541618673
Short name T719
Test name
Test status
Simulation time 14756588325 ps
CPU time 26.26 seconds
Started Aug 21 08:28:48 AM UTC 24
Finished Aug 21 08:29:16 AM UTC 24
Peak memory 246008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3541618673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 18.i2c_target_stress_all.3541618673
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_stress_rd.4060858547
Short name T692
Test name
Test status
Simulation time 2707292688 ps
CPU time 12.94 seconds
Started Aug 21 08:28:37 AM UTC 24
Finished Aug 21 08:28:51 AM UTC 24
Peak memory 229060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4060858547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stress_rd.4060858547
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_stress_wr.3579538070
Short name T715
Test name
Test status
Simulation time 14570527015 ps
CPU time 34.77 seconds
Started Aug 21 08:28:35 AM UTC 24
Finished Aug 21 08:29:11 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3579538070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stress_wr.3579538070
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_stretch.652642967
Short name T687
Test name
Test status
Simulation time 582844650 ps
CPU time 3.44 seconds
Started Aug 21 08:28:38 AM UTC 24
Finished Aug 21 08:28:42 AM UTC 24
Peak memory 228984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=652642967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_tar
get_stretch.652642967
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_timeout.2750158089
Short name T695
Test name
Test status
Simulation time 1358246447 ps
CPU time 11.74 seconds
Started Aug 21 08:28:41 AM UTC 24
Finished Aug 21 08:28:54 AM UTC 24
Peak memory 243744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2750158089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_timeout.2750158089
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/18.i2c_target_tx_stretch_ctrl.805159971
Short name T705
Test name
Test status
Simulation time 160441485 ps
CPU time 4.69 seconds
Started Aug 21 08:28:57 AM UTC 24
Finished Aug 21 08:29:03 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=805159971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_tx_stretch_ctrl.805159971
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_alert_test.2197107716
Short name T739
Test name
Test status
Simulation time 196189218 ps
CPU time 0.97 seconds
Started Aug 21 08:29:35 AM UTC 24
Finished Aug 21 08:29:37 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2197107716 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2197107716
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_error_intr.4060312411
Short name T717
Test name
Test status
Simulation time 395178132 ps
CPU time 2.44 seconds
Started Aug 21 08:29:09 AM UTC 24
Finished Aug 21 08:29:12 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4060312411 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.4060312411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_fmt_empty.1720809252
Short name T720
Test name
Test status
Simulation time 267069174 ps
CPU time 12.75 seconds
Started Aug 21 08:29:04 AM UTC 24
Finished Aug 21 08:29:18 AM UTC 24
Peak memory 262252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1720809252 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty.1720809252
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_full.3333851961
Short name T758
Test name
Test status
Simulation time 5249166198 ps
CPU time 52.75 seconds
Started Aug 21 08:29:06 AM UTC 24
Finished Aug 21 08:30:00 AM UTC 24
Peak memory 467376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3333851961 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3333851961
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_overflow.2460064407
Short name T820
Test name
Test status
Simulation time 11764738789 ps
CPU time 128.77 seconds
Started Aug 21 08:29:04 AM UTC 24
Finished Aug 21 08:31:15 AM UTC 24
Peak memory 758180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2460064407 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2460064407
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_fmt.1636118567
Short name T711
Test name
Test status
Simulation time 122736457 ps
CPU time 1.5 seconds
Started Aug 21 08:29:04 AM UTC 24
Finished Aug 21 08:29:06 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1636118567 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fmt.1636118567
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_rx.2575186685
Short name T718
Test name
Test status
Simulation time 281265693 ps
CPU time 9.3 seconds
Started Aug 21 08:29:06 AM UTC 24
Finished Aug 21 08:29:16 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2575186685 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.2575186685
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_watermark.1919692167
Short name T122
Test name
Test status
Simulation time 4697726421 ps
CPU time 90.19 seconds
Started Aug 21 08:29:03 AM UTC 24
Finished Aug 21 08:30:36 AM UTC 24
Peak memory 1341712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1919692167 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1919692167
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_may_nack.3446677575
Short name T738
Test name
Test status
Simulation time 535680589 ps
CPU time 5.3 seconds
Started Aug 21 08:29:30 AM UTC 24
Finished Aug 21 08:29:37 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3446677575 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3446677575
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_override.1872019373
Short name T707
Test name
Test status
Simulation time 17386315 ps
CPU time 0.99 seconds
Started Aug 21 08:29:02 AM UTC 24
Finished Aug 21 08:29:04 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1872019373 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1872019373
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_perf.739779689
Short name T713
Test name
Test status
Simulation time 737976924 ps
CPU time 2.77 seconds
Started Aug 21 08:29:06 AM UTC 24
Finished Aug 21 08:29:10 AM UTC 24
Peak memory 239320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=739779689 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.739779689
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_perf_precise.512387991
Short name T775
Test name
Test status
Simulation time 6125305392 ps
CPU time 66.62 seconds
Started Aug 21 08:29:07 AM UTC 24
Finished Aug 21 08:30:15 AM UTC 24
Peak memory 583892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=512387991 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.512387991
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_smoke.1816432207
Short name T614
Test name
Test status
Simulation time 2186766667 ps
CPU time 42.19 seconds
Started Aug 21 08:29:01 AM UTC 24
Finished Aug 21 08:29:45 AM UTC 24
Peak memory 397584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1816432207 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1816432207
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_host_stretch_timeout.1255524697
Short name T735
Test name
Test status
Simulation time 816352452 ps
CPU time 27.42 seconds
Started Aug 21 08:29:07 AM UTC 24
Finished Aug 21 08:29:36 AM UTC 24
Peak memory 226904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1255524697 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1255524697
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_bad_addr.702084528
Short name T732
Test name
Test status
Simulation time 2359880272 ps
CPU time 4.09 seconds
Started Aug 21 08:29:26 AM UTC 24
Finished Aug 21 08:29:31 AM UTC 24
Peak memory 233296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=702084528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_bad_addr.702084528
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_acq.3009982440
Short name T724
Test name
Test status
Simulation time 279891785 ps
CPU time 2.05 seconds
Started Aug 21 08:29:21 AM UTC 24
Finished Aug 21 08:29:24 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3009982440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_fifo_reset_acq.3009982440
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_tx.3491842869
Short name T725
Test name
Test status
Simulation time 216486369 ps
CPU time 2.09 seconds
Started Aug 21 08:29:22 AM UTC 24
Finished Aug 21 08:29:25 AM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3491842869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_fifo_reset_tx.3491842869
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_acq.2073292954
Short name T736
Test name
Test status
Simulation time 549335844 ps
CPU time 3.81 seconds
Started Aug 21 08:29:31 AM UTC 24
Finished Aug 21 08:29:36 AM UTC 24
Peak memory 230972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2073292954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.2073292954
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_tx.1046042839
Short name T734
Test name
Test status
Simulation time 243379541 ps
CPU time 1.14 seconds
Started Aug 21 08:29:31 AM UTC 24
Finished Aug 21 08:29:33 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1046042839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.1046042839
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_intr_smoke.651860717
Short name T727
Test name
Test status
Simulation time 4845933509 ps
CPU time 10.21 seconds
Started Aug 21 08:29:16 AM UTC 24
Finished Aug 21 08:29:28 AM UTC 24
Peak memory 233716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=651860717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_intr_smoke.651860717
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_intr_stress_wr.2660590632
Short name T780
Test name
Test status
Simulation time 19967244635 ps
CPU time 62.47 seconds
Started Aug 21 08:29:17 AM UTC 24
Finished Aug 21 08:30:22 AM UTC 24
Peak memory 848388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2660590632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2660590632
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull.69948151
Short name T742
Test name
Test status
Simulation time 1923190598 ps
CPU time 4.29 seconds
Started Aug 21 08:29:33 AM UTC 24
Finished Aug 21 08:29:38 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=69948151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_nack_acqfull.69948151
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull_addr.4267427347
Short name T53
Test name
Test status
Simulation time 508233097 ps
CPU time 4.58 seconds
Started Aug 21 08:29:33 AM UTC 24
Finished Aug 21 08:29:38 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4267427347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_nack_acqfull_addr.4267427347
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_nack_txstretch.2813044099
Short name T741
Test name
Test status
Simulation time 206935185 ps
CPU time 2.95 seconds
Started Aug 21 08:29:34 AM UTC 24
Finished Aug 21 08:29:38 AM UTC 24
Peak memory 233668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2813044099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_nack_txstretch.2813044099
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_perf.732292108
Short name T731
Test name
Test status
Simulation time 2186780076 ps
CPU time 6.97 seconds
Started Aug 21 08:29:23 AM UTC 24
Finished Aug 21 08:29:31 AM UTC 24
Peak memory 233884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=732292108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 19.i2c_target_perf.732292108
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_smbus_maxlen.3235560457
Short name T740
Test name
Test status
Simulation time 868553262 ps
CPU time 4.03 seconds
Started Aug 21 08:29:32 AM UTC 24
Finished Aug 21 08:29:37 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3235560457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 19.i2c_target_smbus_maxlen.3235560457
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_smoke.3964733986
Short name T730
Test name
Test status
Simulation time 928626709 ps
CPU time 18 seconds
Started Aug 21 08:29:11 AM UTC 24
Finished Aug 21 08:29:30 AM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3964733986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_targ
et_smoke.3964733986
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_stress_all.108947061
Short name T813
Test name
Test status
Simulation time 40404682819 ps
CPU time 98.74 seconds
Started Aug 21 08:29:25 AM UTC 24
Finished Aug 21 08:31:06 AM UTC 24
Peak memory 1190160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=108947061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_stress_all.108947061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_stress_rd.1565290654
Short name T750
Test name
Test status
Simulation time 7250647891 ps
CPU time 38.29 seconds
Started Aug 21 08:29:12 AM UTC 24
Finished Aug 21 08:29:52 AM UTC 24
Peak memory 244148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1565290654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stress_rd.1565290654
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.3549803493
Short name T722
Test name
Test status
Simulation time 14512253226 ps
CPU time 6.19 seconds
Started Aug 21 08:29:12 AM UTC 24
Finished Aug 21 08:29:19 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3549803493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stress_wr.3549803493
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_stretch.3458769849
Short name T749
Test name
Test status
Simulation time 1914550766 ps
CPU time 33.99 seconds
Started Aug 21 08:29:13 AM UTC 24
Finished Aug 21 08:29:49 AM UTC 24
Peak memory 655392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3458769849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_stretch.3458769849
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_timeout.26272927
Short name T729
Test name
Test status
Simulation time 17370041750 ps
CPU time 10.33 seconds
Started Aug 21 08:29:19 AM UTC 24
Finished Aug 21 08:29:30 AM UTC 24
Peak memory 227104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=26272927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_timeout.26272927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/19.i2c_target_tx_stretch_ctrl.2834159000
Short name T737
Test name
Test status
Simulation time 155572402 ps
CPU time 3.74 seconds
Started Aug 21 08:29:31 AM UTC 24
Finished Aug 21 08:29:36 AM UTC 24
Peak memory 216792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2834159000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.2834159000
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_alert_test.1858849492
Short name T105
Test name
Test status
Simulation time 15968588 ps
CPU time 0.92 seconds
Started Aug 21 08:22:37 AM UTC 24
Finished Aug 21 08:22:40 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1858849492 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.1858849492
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.422168235
Short name T22
Test name
Test status
Simulation time 231001671 ps
CPU time 1.94 seconds
Started Aug 21 08:22:27 AM UTC 24
Finished Aug 21 08:22:30 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=422168235 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.422168235
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.194715310
Short name T166
Test name
Test status
Simulation time 330200753 ps
CPU time 15.9 seconds
Started Aug 21 08:22:25 AM UTC 24
Finished Aug 21 08:22:43 AM UTC 24
Peak memory 289116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=194715310 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.194715310
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.1874284475
Short name T189
Test name
Test status
Simulation time 2116728271 ps
CPU time 119.3 seconds
Started Aug 21 08:22:27 AM UTC 24
Finished Aug 21 08:24:29 AM UTC 24
Peak memory 481616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1874284475 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.1874284475
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.3628298007
Short name T108
Test name
Test status
Simulation time 10932277326 ps
CPU time 67.93 seconds
Started Aug 21 08:22:25 AM UTC 24
Finished Aug 21 08:23:35 AM UTC 24
Peak memory 887016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3628298007 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3628298007
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.3969616098
Short name T41
Test name
Test status
Simulation time 335324197 ps
CPU time 1.61 seconds
Started Aug 21 08:22:25 AM UTC 24
Finished Aug 21 08:22:28 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3969616098 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt.3969616098
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.2518444547
Short name T87
Test name
Test status
Simulation time 123272198 ps
CPU time 4.06 seconds
Started Aug 21 08:22:27 AM UTC 24
Finished Aug 21 08:22:32 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2518444547 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.2518444547
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.1138205197
Short name T504
Test name
Test status
Simulation time 15502057799 ps
CPU time 201.86 seconds
Started Aug 21 08:22:25 AM UTC 24
Finished Aug 21 08:25:50 AM UTC 24
Peak memory 1181964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1138205197 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1138205197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.3691002142
Short name T13
Test name
Test status
Simulation time 250740574 ps
CPU time 11.13 seconds
Started Aug 21 08:22:33 AM UTC 24
Finished Aug 21 08:22:45 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3691002142 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3691002142
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_mode_toggle.825200158
Short name T18
Test name
Test status
Simulation time 164544381 ps
CPU time 1.55 seconds
Started Aug 21 08:22:32 AM UTC 24
Finished Aug 21 08:22:34 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=825200158 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.825200158
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_override.275716634
Short name T106
Test name
Test status
Simulation time 29030166 ps
CPU time 0.78 seconds
Started Aug 21 08:22:25 AM UTC 24
Finished Aug 21 08:22:27 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=275716634 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.275716634
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_perf.977098691
Short name T14
Test name
Test status
Simulation time 5126324526 ps
CPU time 54.29 seconds
Started Aug 21 08:22:27 AM UTC 24
Finished Aug 21 08:23:23 AM UTC 24
Peak memory 375016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=977098691 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.977098691
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.161587114
Short name T4
Test name
Test status
Simulation time 741831766 ps
CPU time 7.8 seconds
Started Aug 21 08:22:27 AM UTC 24
Finished Aug 21 08:22:36 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=161587114 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.161587114
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.1993232071
Short name T305
Test name
Test status
Simulation time 7027892352 ps
CPU time 24.82 seconds
Started Aug 21 08:22:25 AM UTC 24
Finished Aug 21 08:22:51 AM UTC 24
Peak memory 329960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1993232071 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1993232071
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.3079376670
Short name T173
Test name
Test status
Simulation time 797445579 ps
CPU time 5.63 seconds
Started Aug 21 08:22:27 AM UTC 24
Finished Aug 21 08:22:34 AM UTC 24
Peak memory 233540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3079376670 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3079376670
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.4250718148
Short name T218
Test name
Test status
Simulation time 134583242 ps
CPU time 1.29 seconds
Started Aug 21 08:22:37 AM UTC 24
Finished Aug 21 08:22:40 AM UTC 24
Peak memory 246684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4250718148 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.4250718148
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.134617058
Short name T319
Test name
Test status
Simulation time 652818480 ps
CPU time 2.23 seconds
Started Aug 21 08:22:28 AM UTC 24
Finished Aug 21 08:22:32 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=134617058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_fifo_reset_acq.134617058
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.1838880059
Short name T267
Test name
Test status
Simulation time 292527089 ps
CPU time 1.28 seconds
Started Aug 21 08:22:28 AM UTC 24
Finished Aug 21 08:22:31 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1838880059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_fifo_reset_tx.1838880059
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.1881628991
Short name T298
Test name
Test status
Simulation time 1437386553 ps
CPU time 3.6 seconds
Started Aug 21 08:22:33 AM UTC 24
Finished Aug 21 08:22:38 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1881628991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.1881628991
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.586863344
Short name T192
Test name
Test status
Simulation time 181162989 ps
CPU time 1.57 seconds
Started Aug 21 08:22:33 AM UTC 24
Finished Aug 21 08:22:36 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=586863344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.586863344
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_hrst.320870826
Short name T179
Test name
Test status
Simulation time 3775661469 ps
CPU time 3.29 seconds
Started Aug 21 08:22:31 AM UTC 24
Finished Aug 21 08:22:35 AM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=320870826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.i2c_target_hrst.320870826
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.1450999492
Short name T320
Test name
Test status
Simulation time 3819785243 ps
CPU time 7.67 seconds
Started Aug 21 08:22:28 AM UTC 24
Finished Aug 21 08:22:37 AM UTC 24
Peak memory 233756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1450999492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_intr_smoke.1450999492
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.3720187006
Short name T170
Test name
Test status
Simulation time 7523522415 ps
CPU time 15.16 seconds
Started Aug 21 08:22:28 AM UTC 24
Finished Aug 21 08:22:45 AM UTC 24
Peak memory 216972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3720187006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3720187006
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.3770315149
Short name T164
Test name
Test status
Simulation time 1901761675 ps
CPU time 3.45 seconds
Started Aug 21 08:22:35 AM UTC 24
Finished Aug 21 08:22:40 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3770315149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 2.i2c_target_nack_acqfull.3770315149
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.369765018
Short name T64
Test name
Test status
Simulation time 136026920 ps
CPU time 2.19 seconds
Started Aug 21 08:22:36 AM UTC 24
Finished Aug 21 08:22:40 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=369765018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_nack_txstretch.369765018
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_perf.2593923697
Short name T316
Test name
Test status
Simulation time 6571112432 ps
CPU time 10.11 seconds
Started Aug 21 08:22:29 AM UTC 24
Finished Aug 21 08:22:41 AM UTC 24
Peak memory 243868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2593923697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 2.i2c_target_perf.2593923697
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.1395935503
Short name T321
Test name
Test status
Simulation time 1633067007 ps
CPU time 2.16 seconds
Started Aug 21 08:22:35 AM UTC 24
Finished Aug 21 08:22:39 AM UTC 24
Peak memory 216292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1395935503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 2.i2c_target_smbus_maxlen.1395935503
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.402010060
Short name T317
Test name
Test status
Simulation time 1287262938 ps
CPU time 14.15 seconds
Started Aug 21 08:22:27 AM UTC 24
Finished Aug 21 08:22:42 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=402010060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target
_smoke.402010060
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.2009756433
Short name T264
Test name
Test status
Simulation time 5762273635 ps
CPU time 37.54 seconds
Started Aug 21 08:22:29 AM UTC 24
Finished Aug 21 08:23:09 AM UTC 24
Peak memory 246256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2009756433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.i2c_target_stress_all.2009756433
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.1075743778
Short name T341
Test name
Test status
Simulation time 11912882298 ps
CPU time 29.68 seconds
Started Aug 21 08:22:28 AM UTC 24
Finished Aug 21 08:22:59 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1075743778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stress_wr.1075743778
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.616919113
Short name T340
Test name
Test status
Simulation time 3358054803 ps
CPU time 27.86 seconds
Started Aug 21 08:22:28 AM UTC 24
Finished Aug 21 08:22:57 AM UTC 24
Peak memory 784536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=616919113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targ
et_stretch.616919113
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.4067943225
Short name T81
Test name
Test status
Simulation time 1414111878 ps
CPU time 7.27 seconds
Started Aug 21 08:22:28 AM UTC 24
Finished Aug 21 08:22:37 AM UTC 24
Peak memory 231064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4067943225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_timeout.4067943225
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.443926090
Short name T310
Test name
Test status
Simulation time 155316535 ps
CPU time 4.38 seconds
Started Aug 21 08:22:34 AM UTC 24
Finished Aug 21 08:22:40 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=443926090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_tx_stretch_ctrl.443926090
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_alert_test.1089077605
Short name T766
Test name
Test status
Simulation time 26363867 ps
CPU time 0.91 seconds
Started Aug 21 08:30:07 AM UTC 24
Finished Aug 21 08:30:09 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1089077605 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1089077605
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_error_intr.4028856871
Short name T747
Test name
Test status
Simulation time 133778973 ps
CPU time 3.06 seconds
Started Aug 21 08:29:40 AM UTC 24
Finished Aug 21 08:29:45 AM UTC 24
Peak memory 232988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4028856871 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.4028856871
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_fmt_empty.3543524891
Short name T748
Test name
Test status
Simulation time 471732479 ps
CPU time 6.58 seconds
Started Aug 21 08:29:38 AM UTC 24
Finished Aug 21 08:29:46 AM UTC 24
Peak memory 294952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3543524891 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty.3543524891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_full.4044810118
Short name T791
Test name
Test status
Simulation time 13204534604 ps
CPU time 62.2 seconds
Started Aug 21 08:29:39 AM UTC 24
Finished Aug 21 08:30:43 AM UTC 24
Peak memory 375280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4044810118 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.4044810118
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_overflow.3450373158
Short name T783
Test name
Test status
Simulation time 5513718424 ps
CPU time 50.28 seconds
Started Aug 21 08:29:38 AM UTC 24
Finished Aug 21 08:30:30 AM UTC 24
Peak memory 539084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3450373158 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3450373158
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_fmt.4243032061
Short name T746
Test name
Test status
Simulation time 112400094 ps
CPU time 1.18 seconds
Started Aug 21 08:29:38 AM UTC 24
Finished Aug 21 08:29:40 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4243032061 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt.4243032061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_rx.1713678269
Short name T673
Test name
Test status
Simulation time 682896806 ps
CPU time 5.75 seconds
Started Aug 21 08:29:38 AM UTC 24
Finished Aug 21 08:29:45 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1713678269 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.1713678269
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_watermark.4179947266
Short name T876
Test name
Test status
Simulation time 21520937530 ps
CPU time 152.44 seconds
Started Aug 21 08:29:37 AM UTC 24
Finished Aug 21 08:32:12 AM UTC 24
Peak memory 1568912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4179947266 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.4179947266
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_may_nack.7243557
Short name T770
Test name
Test status
Simulation time 8648205578 ps
CPU time 8.85 seconds
Started Aug 21 08:30:00 AM UTC 24
Finished Aug 21 08:30:10 AM UTC 24
Peak memory 216904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=7243557 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.7243557
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_mode_toggle.979762471
Short name T762
Test name
Test status
Simulation time 535684365 ps
CPU time 5.67 seconds
Started Aug 21 08:29:58 AM UTC 24
Finished Aug 21 08:30:05 AM UTC 24
Peak memory 226716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=979762471 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.979762471
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_override.1829867
Short name T743
Test name
Test status
Simulation time 26983173 ps
CPU time 1.04 seconds
Started Aug 21 08:29:37 AM UTC 24
Finished Aug 21 08:29:39 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1829867 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1829867
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_perf.3318732875
Short name T849
Test name
Test status
Simulation time 2857560511 ps
CPU time 124.05 seconds
Started Aug 21 08:29:39 AM UTC 24
Finished Aug 21 08:31:46 AM UTC 24
Peak memory 237200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3318732875 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3318732875
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_perf_precise.342854009
Short name T803
Test name
Test status
Simulation time 24875086169 ps
CPU time 72.37 seconds
Started Aug 21 08:29:39 AM UTC 24
Finished Aug 21 08:30:53 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=342854009 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.342854009
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_smoke.3076987026
Short name T773
Test name
Test status
Simulation time 6953024935 ps
CPU time 33.12 seconds
Started Aug 21 08:29:37 AM UTC 24
Finished Aug 21 08:30:11 AM UTC 24
Peak memory 332196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3076987026 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3076987026
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_host_stretch_timeout.2909780869
Short name T751
Test name
Test status
Simulation time 920238689 ps
CPU time 12.91 seconds
Started Aug 21 08:29:40 AM UTC 24
Finished Aug 21 08:29:54 AM UTC 24
Peak memory 230916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2909780869 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2909780869
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_bad_addr.2375870666
Short name T765
Test name
Test status
Simulation time 3349282321 ps
CPU time 7 seconds
Started Aug 21 08:29:58 AM UTC 24
Finished Aug 21 08:30:06 AM UTC 24
Peak memory 233760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=2375870666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2375870666
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_acq.1004172889
Short name T754
Test name
Test status
Simulation time 780502230 ps
CPU time 1.66 seconds
Started Aug 21 08:29:55 AM UTC 24
Finished Aug 21 08:29:58 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1004172889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_acq.1004172889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_tx.262420023
Short name T756
Test name
Test status
Simulation time 247300847 ps
CPU time 1.14 seconds
Started Aug 21 08:29:56 AM UTC 24
Finished Aug 21 08:29:58 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=262420023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 20.i2c_target_fifo_reset_tx.262420023
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_acq.1246216693
Short name T763
Test name
Test status
Simulation time 395036237 ps
CPU time 3.57 seconds
Started Aug 21 08:30:01 AM UTC 24
Finished Aug 21 08:30:05 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1246216693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.1246216693
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_tx.3151184653
Short name T759
Test name
Test status
Simulation time 302506079 ps
CPU time 1.54 seconds
Started Aug 21 08:30:01 AM UTC 24
Finished Aug 21 08:30:03 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3151184653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.3151184653
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_intr_smoke.3907234848
Short name T753
Test name
Test status
Simulation time 2323440175 ps
CPU time 10.82 seconds
Started Aug 21 08:29:46 AM UTC 24
Finished Aug 21 08:29:58 AM UTC 24
Peak memory 231064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3907234848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.3907234848
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_intr_stress_wr.1381352348
Short name T844
Test name
Test status
Simulation time 33708608352 ps
CPU time 112.3 seconds
Started Aug 21 08:29:47 AM UTC 24
Finished Aug 21 08:31:41 AM UTC 24
Peak memory 1872044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1381352348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.1381352348
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull.3220319164
Short name T772
Test name
Test status
Simulation time 10283578173 ps
CPU time 4.15 seconds
Started Aug 21 08:30:06 AM UTC 24
Finished Aug 21 08:30:11 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3220319164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 20.i2c_target_nack_acqfull.3220319164
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull_addr.1667845731
Short name T771
Test name
Test status
Simulation time 3513535153 ps
CPU time 3.74 seconds
Started Aug 21 08:30:06 AM UTC 24
Finished Aug 21 08:30:11 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1667845731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_nack_acqfull_addr.1667845731
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_nack_txstretch.850076964
Short name T767
Test name
Test status
Simulation time 333314827 ps
CPU time 2.08 seconds
Started Aug 21 08:30:06 AM UTC 24
Finished Aug 21 08:30:09 AM UTC 24
Peak memory 233548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=850076964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_nack_txstretch.850076964
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_perf.2593145953
Short name T761
Test name
Test status
Simulation time 2510668422 ps
CPU time 7.88 seconds
Started Aug 21 08:29:56 AM UTC 24
Finished Aug 21 08:30:05 AM UTC 24
Peak memory 230956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2593145953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 20.i2c_target_perf.2593145953
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_smbus_maxlen.2110640759
Short name T769
Test name
Test status
Simulation time 529833036 ps
CPU time 3.63 seconds
Started Aug 21 08:30:05 AM UTC 24
Finished Aug 21 08:30:10 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2110640759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 20.i2c_target_smbus_maxlen.2110640759
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_smoke.4048761130
Short name T94
Test name
Test status
Simulation time 3758246682 ps
CPU time 14.28 seconds
Started Aug 21 08:29:42 AM UTC 24
Finished Aug 21 08:29:57 AM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4048761130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_targ
et_smoke.4048761130
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_stress_all.3283314148
Short name T866
Test name
Test status
Simulation time 19740074413 ps
CPU time 123.83 seconds
Started Aug 21 08:29:57 AM UTC 24
Finished Aug 21 08:32:03 AM UTC 24
Peak memory 1702228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3283314148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 20.i2c_target_stress_all.3283314148
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_stress_rd.266706410
Short name T760
Test name
Test status
Simulation time 812645121 ps
CPU time 17.24 seconds
Started Aug 21 08:29:46 AM UTC 24
Finished Aug 21 08:30:04 AM UTC 24
Peak memory 233576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=266706410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stress_rd.266706410
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.3239796685
Short name T917
Test name
Test status
Simulation time 49809627482 ps
CPU time 182.26 seconds
Started Aug 21 08:29:42 AM UTC 24
Finished Aug 21 08:32:46 AM UTC 24
Peak memory 2640096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3239796685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stress_wr.3239796685
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_stretch.1942947623
Short name T764
Test name
Test status
Simulation time 2586258272 ps
CPU time 19.11 seconds
Started Aug 21 08:29:46 AM UTC 24
Finished Aug 21 08:30:06 AM UTC 24
Peak memory 266396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1942947623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_stretch.1942947623
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_timeout.1570195974
Short name T755
Test name
Test status
Simulation time 4854919047 ps
CPU time 7.97 seconds
Started Aug 21 08:29:49 AM UTC 24
Finished Aug 21 08:29:58 AM UTC 24
Peak memory 233708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1570195974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_timeout.1570195974
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/20.i2c_target_tx_stretch_ctrl.3300146381
Short name T776
Test name
Test status
Simulation time 482531094 ps
CPU time 10.76 seconds
Started Aug 21 08:30:04 AM UTC 24
Finished Aug 21 08:30:16 AM UTC 24
Peak memory 232980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3300146381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.3300146381
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_alert_test.4082862576
Short name T799
Test name
Test status
Simulation time 18329369 ps
CPU time 1.02 seconds
Started Aug 21 08:30:49 AM UTC 24
Finished Aug 21 08:30:51 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4082862576 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.4082862576
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_error_intr.2155184428
Short name T778
Test name
Test status
Simulation time 171923838 ps
CPU time 2.53 seconds
Started Aug 21 08:30:16 AM UTC 24
Finished Aug 21 08:30:20 AM UTC 24
Peak memory 233572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2155184428 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2155184428
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_fmt_empty.3905840605
Short name T782
Test name
Test status
Simulation time 295349776 ps
CPU time 13.67 seconds
Started Aug 21 08:30:11 AM UTC 24
Finished Aug 21 08:30:27 AM UTC 24
Peak memory 274580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3905840605 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty.3905840605
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.1967844963
Short name T819
Test name
Test status
Simulation time 2143807757 ps
CPU time 60.7 seconds
Started Aug 21 08:30:12 AM UTC 24
Finished Aug 21 08:31:15 AM UTC 24
Peak memory 309540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1967844963 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1967844963
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_overflow.2816113610
Short name T806
Test name
Test status
Simulation time 10699058264 ps
CPU time 43.41 seconds
Started Aug 21 08:30:10 AM UTC 24
Finished Aug 21 08:30:56 AM UTC 24
Peak memory 608532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2816113610 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2816113610
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_fmt.3136037563
Short name T774
Test name
Test status
Simulation time 709589991 ps
CPU time 2.18 seconds
Started Aug 21 08:30:10 AM UTC 24
Finished Aug 21 08:30:14 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3136037563 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt.3136037563
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_rx.262269545
Short name T777
Test name
Test status
Simulation time 324088845 ps
CPU time 6.46 seconds
Started Aug 21 08:30:11 AM UTC 24
Finished Aug 21 08:30:19 AM UTC 24
Peak memory 241748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=262269545 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.262269545
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.2900447578
Short name T1020
Test name
Test status
Simulation time 4897861867 ps
CPU time 248.88 seconds
Started Aug 21 08:30:10 AM UTC 24
Finished Aug 21 08:34:23 AM UTC 24
Peak memory 1323232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2900447578 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2900447578
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_may_nack.3518129758
Short name T275
Test name
Test status
Simulation time 961285622 ps
CPU time 10.22 seconds
Started Aug 21 08:30:41 AM UTC 24
Finished Aug 21 08:30:52 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3518129758 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3518129758
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_override.1155335904
Short name T768
Test name
Test status
Simulation time 38115389 ps
CPU time 0.93 seconds
Started Aug 21 08:30:07 AM UTC 24
Finished Aug 21 08:30:09 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1155335904 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1155335904
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_perf.2590822884
Short name T781
Test name
Test status
Simulation time 684647650 ps
CPU time 9.94 seconds
Started Aug 21 08:30:13 AM UTC 24
Finished Aug 21 08:30:24 AM UTC 24
Peak memory 233500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590822884 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2590822884
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_perf_precise.1206779704
Short name T908
Test name
Test status
Simulation time 25373841977 ps
CPU time 145.38 seconds
Started Aug 21 08:30:13 AM UTC 24
Finished Aug 21 08:32:41 AM UTC 24
Peak memory 852236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1206779704 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.1206779704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_smoke.460889800
Short name T789
Test name
Test status
Simulation time 7838365875 ps
CPU time 32.77 seconds
Started Aug 21 08:30:07 AM UTC 24
Finished Aug 21 08:30:41 AM UTC 24
Peak memory 375108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=460889800 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.460889800
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_stress_all.739739649
Short name T181
Test name
Test status
Simulation time 26655853812 ps
CPU time 148.5 seconds
Started Aug 21 08:30:17 AM UTC 24
Finished Aug 21 08:32:48 AM UTC 24
Peak memory 1001696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=739739649 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.739739649
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_host_stretch_timeout.2758600141
Short name T809
Test name
Test status
Simulation time 3847565998 ps
CPU time 44.65 seconds
Started Aug 21 08:30:15 AM UTC 24
Finished Aug 21 08:31:01 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2758600141 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2758600141
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_bad_addr.1549926503
Short name T796
Test name
Test status
Simulation time 5231105513 ps
CPU time 6.62 seconds
Started Aug 21 08:30:40 AM UTC 24
Finished Aug 21 08:30:48 AM UTC 24
Peak memory 233356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1549926503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1549926503
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_acq.2416531965
Short name T786
Test name
Test status
Simulation time 522344275 ps
CPU time 1.93 seconds
Started Aug 21 08:30:37 AM UTC 24
Finished Aug 21 08:30:40 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2416531965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_acq.2416531965
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_tx.3316207782
Short name T785
Test name
Test status
Simulation time 161322259 ps
CPU time 1.48 seconds
Started Aug 21 08:30:37 AM UTC 24
Finished Aug 21 08:30:39 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3316207782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_fifo_reset_tx.3316207782
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_acq.415859042
Short name T792
Test name
Test status
Simulation time 394703300 ps
CPU time 3.23 seconds
Started Aug 21 08:30:42 AM UTC 24
Finished Aug 21 08:30:46 AM UTC 24
Peak memory 216684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=415859042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.415859042
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_tx.1391491412
Short name T794
Test name
Test status
Simulation time 191145203 ps
CPU time 2.19 seconds
Started Aug 21 08:30:43 AM UTC 24
Finished Aug 21 08:30:46 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1391491412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.1391491412
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_hrst.4053791365
Short name T793
Test name
Test status
Simulation time 700671860 ps
CPU time 4.31 seconds
Started Aug 21 08:30:41 AM UTC 24
Finished Aug 21 08:30:46 AM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4053791365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 21.i2c_target_hrst.4053791365
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_intr_smoke.3908994352
Short name T784
Test name
Test status
Simulation time 980250943 ps
CPU time 10.44 seconds
Started Aug 21 08:30:24 AM UTC 24
Finished Aug 21 08:30:36 AM UTC 24
Peak memory 232916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3908994352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_intr_smoke.3908994352
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.2537195896
Short name T815
Test name
Test status
Simulation time 10955716755 ps
CPU time 37.62 seconds
Started Aug 21 08:30:27 AM UTC 24
Finished Aug 21 08:31:07 AM UTC 24
Peak memory 626860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2537195896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2537195896
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull.2406182321
Short name T804
Test name
Test status
Simulation time 509430073 ps
CPU time 4.81 seconds
Started Aug 21 08:30:47 AM UTC 24
Finished Aug 21 08:30:53 AM UTC 24
Peak memory 226772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2406182321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_target_nack_acqfull.2406182321
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull_addr.690301683
Short name T802
Test name
Test status
Simulation time 2812564856 ps
CPU time 4.4 seconds
Started Aug 21 08:30:47 AM UTC 24
Finished Aug 21 08:30:53 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=690301683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_nack_acqfull_addr.690301683
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_nack_txstretch.96074883
Short name T798
Test name
Test status
Simulation time 138565687 ps
CPU time 2.05 seconds
Started Aug 21 08:30:48 AM UTC 24
Finished Aug 21 08:30:51 AM UTC 24
Peak memory 233496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=96074883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_target_nack_txstretch.96074883
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_perf.1853051199
Short name T795
Test name
Test status
Simulation time 1297611457 ps
CPU time 8.62 seconds
Started Aug 21 08:30:37 AM UTC 24
Finished Aug 21 08:30:47 AM UTC 24
Peak memory 233156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1853051199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 21.i2c_target_perf.1853051199
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_smbus_maxlen.2062706021
Short name T801
Test name
Test status
Simulation time 529562340 ps
CPU time 2.95 seconds
Started Aug 21 08:30:47 AM UTC 24
Finished Aug 21 08:30:51 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2062706021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 21.i2c_target_smbus_maxlen.2062706021
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_smoke.3821933053
Short name T797
Test name
Test status
Simulation time 849146135 ps
CPU time 28.31 seconds
Started Aug 21 08:30:20 AM UTC 24
Finished Aug 21 08:30:50 AM UTC 24
Peak memory 227100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3821933053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_targ
et_smoke.3821933053
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_stress_all.1459637900
Short name T1266
Test name
Test status
Simulation time 33800593919 ps
CPU time 473.23 seconds
Started Aug 21 08:30:38 AM UTC 24
Finished Aug 21 08:38:36 AM UTC 24
Peak memory 4571300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1459637900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 21.i2c_target_stress_all.1459637900
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_stress_rd.3408893181
Short name T808
Test name
Test status
Simulation time 1598838118 ps
CPU time 37.43 seconds
Started Aug 21 08:30:22 AM UTC 24
Finished Aug 21 08:31:01 AM UTC 24
Peak memory 245908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3408893181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stress_rd.3408893181
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.4216829711
Short name T879
Test name
Test status
Simulation time 33963613935 ps
CPU time 114.72 seconds
Started Aug 21 08:30:21 AM UTC 24
Finished Aug 21 08:32:18 AM UTC 24
Peak memory 1884252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4216829711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stress_wr.4216829711
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_timeout.3525258724
Short name T788
Test name
Test status
Simulation time 12096275835 ps
CPU time 8.21 seconds
Started Aug 21 08:30:30 AM UTC 24
Finished Aug 21 08:30:40 AM UTC 24
Peak memory 227144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3525258724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_timeout.3525258724
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/21.i2c_target_tx_stretch_ctrl.679505736
Short name T800
Test name
Test status
Simulation time 149143174 ps
CPU time 5.6 seconds
Started Aug 21 08:30:44 AM UTC 24
Finished Aug 21 08:30:51 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=679505736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_tx_stretch_ctrl.679505736
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_alert_test.754685770
Short name T830
Test name
Test status
Simulation time 55723911 ps
CPU time 0.99 seconds
Started Aug 21 08:31:21 AM UTC 24
Finished Aug 21 08:31:23 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=754685770 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.754685770
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_error_intr.2859267182
Short name T807
Test name
Test status
Simulation time 670380576 ps
CPU time 2.24 seconds
Started Aug 21 08:30:54 AM UTC 24
Finished Aug 21 08:30:58 AM UTC 24
Peak memory 228940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2859267182 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2859267182
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_fmt_empty.2476544540
Short name T823
Test name
Test status
Simulation time 2864568763 ps
CPU time 25.37 seconds
Started Aug 21 08:30:52 AM UTC 24
Finished Aug 21 08:31:19 AM UTC 24
Peak memory 303264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2476544540 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.2476544540
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.2274614909
Short name T891
Test name
Test status
Simulation time 3182047302 ps
CPU time 97.76 seconds
Started Aug 21 08:30:53 AM UTC 24
Finished Aug 21 08:32:33 AM UTC 24
Peak memory 463048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2274614909 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2274614909
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.2971787824
Short name T861
Test name
Test status
Simulation time 17452242467 ps
CPU time 67.39 seconds
Started Aug 21 08:30:52 AM UTC 24
Finished Aug 21 08:32:01 AM UTC 24
Peak memory 630996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2971787824 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2971787824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_fmt.2552686988
Short name T805
Test name
Test status
Simulation time 170503585 ps
CPU time 1.46 seconds
Started Aug 21 08:30:52 AM UTC 24
Finished Aug 21 08:30:54 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2552686988 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt.2552686988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_rx.3526046229
Short name T810
Test name
Test status
Simulation time 356604570 ps
CPU time 9.21 seconds
Started Aug 21 08:30:52 AM UTC 24
Finished Aug 21 08:31:02 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3526046229 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.3526046229
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.3620293784
Short name T961
Test name
Test status
Simulation time 15876146813 ps
CPU time 147.63 seconds
Started Aug 21 08:30:51 AM UTC 24
Finished Aug 21 08:33:21 AM UTC 24
Peak memory 864496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3620293784 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3620293784
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.3516444618
Short name T829
Test name
Test status
Simulation time 1232317493 ps
CPU time 5.79 seconds
Started Aug 21 08:31:15 AM UTC 24
Finished Aug 21 08:31:22 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3516444618 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3516444618
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_mode_toggle.2693539214
Short name T828
Test name
Test status
Simulation time 585518429 ps
CPU time 5.47 seconds
Started Aug 21 08:31:15 AM UTC 24
Finished Aug 21 08:31:21 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2693539214 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2693539214
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_override.948892614
Short name T161
Test name
Test status
Simulation time 99022234 ps
CPU time 1.07 seconds
Started Aug 21 08:30:50 AM UTC 24
Finished Aug 21 08:30:52 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=948892614 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.948892614
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_perf.945656367
Short name T1720
Test name
Test status
Simulation time 26777463908 ps
CPU time 1046.11 seconds
Started Aug 21 08:30:53 AM UTC 24
Finished Aug 21 08:48:30 AM UTC 24
Peak memory 3901772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=945656367 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.945656367
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_perf_precise.2298150371
Short name T814
Test name
Test status
Simulation time 2497533405 ps
CPU time 18.67 seconds
Started Aug 21 08:30:54 AM UTC 24
Finished Aug 21 08:31:14 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2298150371 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.2298150371
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_smoke.3157571606
Short name T873
Test name
Test status
Simulation time 13611510566 ps
CPU time 76.84 seconds
Started Aug 21 08:30:50 AM UTC 24
Finished Aug 21 08:32:08 AM UTC 24
Peak memory 376992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3157571606 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3157571606
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_host_stretch_timeout.1530435478
Short name T816
Test name
Test status
Simulation time 2540600279 ps
CPU time 13.74 seconds
Started Aug 21 08:30:54 AM UTC 24
Finished Aug 21 08:31:09 AM UTC 24
Peak memory 229208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1530435478 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.1530435478
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_bad_addr.1623820158
Short name T827
Test name
Test status
Simulation time 4706088099 ps
CPU time 8.18 seconds
Started Aug 21 08:31:12 AM UTC 24
Finished Aug 21 08:31:21 AM UTC 24
Peak memory 233916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1623820158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1623820158
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_acq.3468733882
Short name T818
Test name
Test status
Simulation time 200940326 ps
CPU time 2.28 seconds
Started Aug 21 08:31:07 AM UTC 24
Finished Aug 21 08:31:11 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3468733882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_acq.3468733882
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_tx.3257618809
Short name T817
Test name
Test status
Simulation time 546733760 ps
CPU time 2.03 seconds
Started Aug 21 08:31:07 AM UTC 24
Finished Aug 21 08:31:10 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3257618809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_fifo_reset_tx.3257618809
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_acq.3566070944
Short name T826
Test name
Test status
Simulation time 391094275 ps
CPU time 3.65 seconds
Started Aug 21 08:31:16 AM UTC 24
Finished Aug 21 08:31:21 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3566070944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.3566070944
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_tx.84454177
Short name T824
Test name
Test status
Simulation time 623159652 ps
CPU time 2.4 seconds
Started Aug 21 08:31:16 AM UTC 24
Finished Aug 21 08:31:19 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=84454177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.84454177
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_intr_smoke.4163585269
Short name T821
Test name
Test status
Simulation time 6253710156 ps
CPU time 11.68 seconds
Started Aug 21 08:31:03 AM UTC 24
Finished Aug 21 08:31:16 AM UTC 24
Peak memory 227200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=4163585269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.4163585269
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_intr_stress_wr.2417401600
Short name T941
Test name
Test status
Simulation time 10269954421 ps
CPU time 115.64 seconds
Started Aug 21 08:31:04 AM UTC 24
Finished Aug 21 08:33:02 AM UTC 24
Peak memory 2642216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2417401600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2417401600
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull.1713094483
Short name T836
Test name
Test status
Simulation time 518799482 ps
CPU time 4.65 seconds
Started Aug 21 08:31:20 AM UTC 24
Finished Aug 21 08:31:26 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1713094483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 22.i2c_target_nack_acqfull.1713094483
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.1624035824
Short name T835
Test name
Test status
Simulation time 539807414 ps
CPU time 4.13 seconds
Started Aug 21 08:31:20 AM UTC 24
Finished Aug 21 08:31:25 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1624035824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_nack_acqfull_addr.1624035824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_nack_txstretch.4171368507
Short name T833
Test name
Test status
Simulation time 518815895 ps
CPU time 1.65 seconds
Started Aug 21 08:31:21 AM UTC 24
Finished Aug 21 08:31:24 AM UTC 24
Peak memory 232580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4171368507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_nack_txstretch.4171368507
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_perf.1926326915
Short name T822
Test name
Test status
Simulation time 595203156 ps
CPU time 7.43 seconds
Started Aug 21 08:31:09 AM UTC 24
Finished Aug 21 08:31:18 AM UTC 24
Peak memory 233776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1926326915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 22.i2c_target_perf.1926326915
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_smbus_maxlen.3168665889
Short name T832
Test name
Test status
Simulation time 485898281 ps
CPU time 3.78 seconds
Started Aug 21 08:31:19 AM UTC 24
Finished Aug 21 08:31:24 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3168665889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 22.i2c_target_smbus_maxlen.3168665889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_smoke.1357232481
Short name T831
Test name
Test status
Simulation time 3440648935 ps
CPU time 25.79 seconds
Started Aug 21 08:30:57 AM UTC 24
Finished Aug 21 08:31:24 AM UTC 24
Peak memory 233720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1357232481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_targ
et_smoke.1357232481
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.3577412336
Short name T1113
Test name
Test status
Simulation time 58265928217 ps
CPU time 285.32 seconds
Started Aug 21 08:31:10 AM UTC 24
Finished Aug 21 08:35:59 AM UTC 24
Peak memory 3914264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3577412336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 22.i2c_target_stress_all.3577412336
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_stress_rd.818315383
Short name T846
Test name
Test status
Simulation time 1593259789 ps
CPU time 40.35 seconds
Started Aug 21 08:31:02 AM UTC 24
Finished Aug 21 08:31:44 AM UTC 24
Peak memory 227128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=818315383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_t
arget_stress_rd.818315383
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_stress_wr.1574529898
Short name T840
Test name
Test status
Simulation time 19187752518 ps
CPU time 34.77 seconds
Started Aug 21 08:30:59 AM UTC 24
Finished Aug 21 08:31:35 AM UTC 24
Peak memory 216700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1574529898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stress_wr.1574529898
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_stretch.3060680295
Short name T901
Test name
Test status
Simulation time 4471986470 ps
CPU time 92.88 seconds
Started Aug 21 08:31:02 AM UTC 24
Finished Aug 21 08:32:37 AM UTC 24
Peak memory 1194188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3060680295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_stretch.3060680295
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_timeout.1950192865
Short name T811
Test name
Test status
Simulation time 5004293819 ps
CPU time 7.28 seconds
Started Aug 21 08:31:05 AM UTC 24
Finished Aug 21 08:31:13 AM UTC 24
Peak memory 250004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1950192865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_timeout.1950192865
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/22.i2c_target_tx_stretch_ctrl.3334398286
Short name T838
Test name
Test status
Simulation time 630611302 ps
CPU time 10.85 seconds
Started Aug 21 08:31:17 AM UTC 24
Finished Aug 21 08:31:29 AM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3334398286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.3334398286
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_alert_test.2685661800
Short name T868
Test name
Test status
Simulation time 46398369 ps
CPU time 0.97 seconds
Started Aug 21 08:32:02 AM UTC 24
Finished Aug 21 08:32:04 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2685661800 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2685661800
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.3087530631
Short name T845
Test name
Test status
Simulation time 302048362 ps
CPU time 11.82 seconds
Started Aug 21 08:31:30 AM UTC 24
Finished Aug 21 08:31:43 AM UTC 24
Peak memory 250036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3087530631 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3087530631
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.3218655882
Short name T839
Test name
Test status
Simulation time 390071674 ps
CPU time 6.95 seconds
Started Aug 21 08:31:25 AM UTC 24
Finished Aug 21 08:31:33 AM UTC 24
Peak memory 299304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3218655882 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.3218655882
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.4040912940
Short name T885
Test name
Test status
Simulation time 8377841484 ps
CPU time 56.86 seconds
Started Aug 21 08:31:26 AM UTC 24
Finished Aug 21 08:32:24 AM UTC 24
Peak memory 575852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4040912940 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.4040912940
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.1130489873
Short name T914
Test name
Test status
Simulation time 2483227151 ps
CPU time 78.55 seconds
Started Aug 21 08:31:24 AM UTC 24
Finished Aug 21 08:32:44 AM UTC 24
Peak memory 815264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1130489873 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1130489873
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_fmt.2023611818
Short name T837
Test name
Test status
Simulation time 267159892 ps
CPU time 1.68 seconds
Started Aug 21 08:31:25 AM UTC 24
Finished Aug 21 08:31:27 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2023611818 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fmt.2023611818
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_rx.1740921368
Short name T842
Test name
Test status
Simulation time 385244518 ps
CPU time 13.5 seconds
Started Aug 21 08:31:25 AM UTC 24
Finished Aug 21 08:31:39 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1740921368 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.1740921368
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.2174284027
Short name T887
Test name
Test status
Simulation time 11371448933 ps
CPU time 60.86 seconds
Started Aug 21 08:31:22 AM UTC 24
Finished Aug 21 08:32:25 AM UTC 24
Peak memory 913552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2174284027 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2174284027
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.3568807517
Short name T865
Test name
Test status
Simulation time 545818693 ps
CPU time 7.35 seconds
Started Aug 21 08:31:54 AM UTC 24
Finished Aug 21 08:32:03 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3568807517 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.3568807517
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_override.2130381440
Short name T834
Test name
Test status
Simulation time 125740993 ps
CPU time 1.06 seconds
Started Aug 21 08:31:22 AM UTC 24
Finished Aug 21 08:31:25 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2130381440 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2130381440
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_perf.709119715
Short name T909
Test name
Test status
Simulation time 6651419783 ps
CPU time 73.43 seconds
Started Aug 21 08:31:26 AM UTC 24
Finished Aug 21 08:32:41 AM UTC 24
Peak memory 297440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=709119715 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.709119715
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.262934654
Short name T1013
Test name
Test status
Simulation time 6156892413 ps
CPU time 166.74 seconds
Started Aug 21 08:31:27 AM UTC 24
Finished Aug 21 08:34:17 AM UTC 24
Peak memory 696588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=262934654 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.262934654
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.2188782630
Short name T877
Test name
Test status
Simulation time 8330067411 ps
CPU time 52.01 seconds
Started Aug 21 08:31:21 AM UTC 24
Finished Aug 21 08:32:15 AM UTC 24
Peak memory 489804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2188782630 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2188782630
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_stress_all.1296138890
Short name T1745
Test name
Test status
Simulation time 36766388905 ps
CPU time 1781.22 seconds
Started Aug 21 08:31:33 AM UTC 24
Finished Aug 21 09:01:32 AM UTC 24
Peak memory 2275756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1296138890 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1296138890
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.3214815389
Short name T848
Test name
Test status
Simulation time 2696880900 ps
CPU time 15.91 seconds
Started Aug 21 08:31:28 AM UTC 24
Finished Aug 21 08:31:45 AM UTC 24
Peak memory 227072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3214815389 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3214815389
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.3771382306
Short name T857
Test name
Test status
Simulation time 799716926 ps
CPU time 5.45 seconds
Started Aug 21 08:31:50 AM UTC 24
Finished Aug 21 08:31:57 AM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3771382306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.3771382306
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.3728406669
Short name T850
Test name
Test status
Simulation time 988907642 ps
CPU time 1.84 seconds
Started Aug 21 08:31:46 AM UTC 24
Finished Aug 21 08:31:49 AM UTC 24
Peak memory 232392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3728406669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_acq.3728406669
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.4140484369
Short name T851
Test name
Test status
Simulation time 175956955 ps
CPU time 1.79 seconds
Started Aug 21 08:31:47 AM UTC 24
Finished Aug 21 08:31:50 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4140484369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_fifo_reset_tx.4140484369
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.2159878875
Short name T860
Test name
Test status
Simulation time 385924738 ps
CPU time 3.15 seconds
Started Aug 21 08:31:55 AM UTC 24
Finished Aug 21 08:32:00 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2159878875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.2159878875
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.1158337814
Short name T859
Test name
Test status
Simulation time 589894364 ps
CPU time 1.92 seconds
Started Aug 21 08:31:57 AM UTC 24
Finished Aug 21 08:32:00 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1158337814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.1158337814
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.1131497747
Short name T856
Test name
Test status
Simulation time 2559052928 ps
CPU time 11.72 seconds
Started Aug 21 08:31:43 AM UTC 24
Finished Aug 21 08:31:55 AM UTC 24
Peak memory 233452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1131497747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.1131497747
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.755260383
Short name T864
Test name
Test status
Simulation time 5678353720 ps
CPU time 17.92 seconds
Started Aug 21 08:31:44 AM UTC 24
Finished Aug 21 08:32:03 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=755260383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.755260383
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.615497351
Short name T863
Test name
Test status
Simulation time 560316144 ps
CPU time 3.84 seconds
Started Aug 21 08:31:58 AM UTC 24
Finished Aug 21 08:32:03 AM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=615497351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 23.i2c_target_nack_acqfull.615497351
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.594660926
Short name T870
Test name
Test status
Simulation time 1092905283 ps
CPU time 3.79 seconds
Started Aug 21 08:32:00 AM UTC 24
Finished Aug 21 08:32:05 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=594660926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_nack_acqfull_addr.594660926
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_nack_txstretch.462228742
Short name T867
Test name
Test status
Simulation time 546678258 ps
CPU time 2.04 seconds
Started Aug 21 08:32:01 AM UTC 24
Finished Aug 21 08:32:04 AM UTC 24
Peak memory 233760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=462228742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_nack_txstretch.462228742
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_perf.168249537
Short name T858
Test name
Test status
Simulation time 811909027 ps
CPU time 7.87 seconds
Started Aug 21 08:31:48 AM UTC 24
Finished Aug 21 08:31:57 AM UTC 24
Peak memory 222708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=168249537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.i2c_target_perf.168249537
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.1590140977
Short name T862
Test name
Test status
Simulation time 425665310 ps
CPU time 3.1 seconds
Started Aug 21 08:31:58 AM UTC 24
Finished Aug 21 08:32:02 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1590140977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 23.i2c_target_smbus_maxlen.1590140977
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.1703568373
Short name T852
Test name
Test status
Simulation time 764029847 ps
CPU time 13.42 seconds
Started Aug 21 08:31:35 AM UTC 24
Finished Aug 21 08:31:50 AM UTC 24
Peak memory 226776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1703568373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_targ
et_smoke.1703568373
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.2442576196
Short name T992
Test name
Test status
Simulation time 120704414630 ps
CPU time 129.48 seconds
Started Aug 21 08:31:49 AM UTC 24
Finished Aug 21 08:34:01 AM UTC 24
Peak memory 1286256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2442576196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 23.i2c_target_stress_all.2442576196
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.4204658515
Short name T883
Test name
Test status
Simulation time 926316462 ps
CPU time 41.95 seconds
Started Aug 21 08:31:40 AM UTC 24
Finished Aug 21 08:32:24 AM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4204658515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stress_rd.4204658515
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.4238248032
Short name T1066
Test name
Test status
Simulation time 60493374252 ps
CPU time 203.37 seconds
Started Aug 21 08:31:39 AM UTC 24
Finished Aug 21 08:35:06 AM UTC 24
Peak memory 2668772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4238248032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stress_wr.4238248032
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.3064770114
Short name T854
Test name
Test status
Simulation time 1378064901 ps
CPU time 11.9 seconds
Started Aug 21 08:31:41 AM UTC 24
Finished Aug 21 08:31:53 AM UTC 24
Peak memory 266344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3064770114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_stretch.3064770114
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.829736632
Short name T855
Test name
Test status
Simulation time 2012061051 ps
CPU time 8.54 seconds
Started Aug 21 08:31:45 AM UTC 24
Finished Aug 21 08:31:54 AM UTC 24
Peak memory 233812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=829736632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_timeout.829736632
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.3997139162
Short name T869
Test name
Test status
Simulation time 294503206 ps
CPU time 6.12 seconds
Started Aug 21 08:31:58 AM UTC 24
Finished Aug 21 08:32:05 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3997139162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.3997139162
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_alert_test.2754127233
Short name T898
Test name
Test status
Simulation time 17546976 ps
CPU time 1.01 seconds
Started Aug 21 08:32:34 AM UTC 24
Finished Aug 21 08:32:36 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2754127233 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2754127233
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.1734633616
Short name T890
Test name
Test status
Simulation time 1194200092 ps
CPU time 24.97 seconds
Started Aug 21 08:32:05 AM UTC 24
Finished Aug 21 08:32:32 AM UTC 24
Peak memory 321876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1734633616 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty.1734633616
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.4168465476
Short name T1064
Test name
Test status
Simulation time 3222289418 ps
CPU time 175.72 seconds
Started Aug 21 08:32:05 AM UTC 24
Finished Aug 21 08:35:04 AM UTC 24
Peak memory 483532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4168465476 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.4168465476
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.908245798
Short name T931
Test name
Test status
Simulation time 7711636005 ps
CPU time 49.77 seconds
Started Aug 21 08:32:04 AM UTC 24
Finished Aug 21 08:32:55 AM UTC 24
Peak memory 688264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=908245798 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.908245798
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.281996478
Short name T872
Test name
Test status
Simulation time 293995630 ps
CPU time 1.45 seconds
Started Aug 21 08:32:04 AM UTC 24
Finished Aug 21 08:32:07 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=281996478 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fmt.281996478
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.2347923094
Short name T878
Test name
Test status
Simulation time 288837867 ps
CPU time 9.17 seconds
Started Aug 21 08:32:05 AM UTC 24
Finished Aug 21 08:32:16 AM UTC 24
Peak memory 243864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347923094 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.2347923094
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.1559229602
Short name T1107
Test name
Test status
Simulation time 15962198960 ps
CPU time 228.95 seconds
Started Aug 21 08:32:03 AM UTC 24
Finished Aug 21 08:35:55 AM UTC 24
Peak memory 1202268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1559229602 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1559229602
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.3454854790
Short name T272
Test name
Test status
Simulation time 1142336257 ps
CPU time 4.73 seconds
Started Aug 21 08:32:28 AM UTC 24
Finished Aug 21 08:32:34 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3454854790 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3454854790
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_override.1286286808
Short name T871
Test name
Test status
Simulation time 25692432 ps
CPU time 1.02 seconds
Started Aug 21 08:32:03 AM UTC 24
Finished Aug 21 08:32:05 AM UTC 24
Peak memory 212212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1286286808 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1286286808
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_perf.1129631090
Short name T874
Test name
Test status
Simulation time 438375711 ps
CPU time 2.89 seconds
Started Aug 21 08:32:05 AM UTC 24
Finished Aug 21 08:32:09 AM UTC 24
Peak memory 237120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1129631090 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1129631090
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.1339367411
Short name T911
Test name
Test status
Simulation time 794063667 ps
CPU time 34.5 seconds
Started Aug 21 08:32:07 AM UTC 24
Finished Aug 21 08:32:43 AM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1339367411 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.1339367411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.907568926
Short name T904
Test name
Test status
Simulation time 1592147000 ps
CPU time 32.82 seconds
Started Aug 21 08:32:03 AM UTC 24
Finished Aug 21 08:32:37 AM UTC 24
Peak memory 313468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=907568926 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.907568926
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.2850189470
Short name T910
Test name
Test status
Simulation time 2759123186 ps
CPU time 32.43 seconds
Started Aug 21 08:32:08 AM UTC 24
Finished Aug 21 08:32:41 AM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2850189470 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.2850189470
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_bad_addr.3449794058
Short name T895
Test name
Test status
Simulation time 3514941945 ps
CPU time 7.32 seconds
Started Aug 21 08:32:26 AM UTC 24
Finished Aug 21 08:32:34 AM UTC 24
Peak memory 227160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3449794058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3449794058
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_acq.791853365
Short name T888
Test name
Test status
Simulation time 344660391 ps
CPU time 1.64 seconds
Started Aug 21 08:32:24 AM UTC 24
Finished Aug 21 08:32:26 AM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=791853365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_fifo_reset_acq.791853365
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.4219208931
Short name T889
Test name
Test status
Simulation time 547777997 ps
CPU time 1.2 seconds
Started Aug 21 08:32:25 AM UTC 24
Finished Aug 21 08:32:27 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4219208931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 24.i2c_target_fifo_reset_tx.4219208931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.14463948
Short name T896
Test name
Test status
Simulation time 445795986 ps
CPU time 3.83 seconds
Started Aug 21 08:32:29 AM UTC 24
Finished Aug 21 08:32:35 AM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=14463948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.14463948
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.4218155400
Short name T892
Test name
Test status
Simulation time 199621919 ps
CPU time 2.34 seconds
Started Aug 21 08:32:29 AM UTC 24
Finished Aug 21 08:32:33 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4218155400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.4218155400
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.1510115249
Short name T881
Test name
Test status
Simulation time 765214034 ps
CPU time 4.79 seconds
Started Aug 21 08:32:16 AM UTC 24
Finished Aug 21 08:32:22 AM UTC 24
Peak memory 226904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1510115249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.1510115249
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.3329021974
Short name T1105
Test name
Test status
Simulation time 25714366182 ps
CPU time 209.39 seconds
Started Aug 21 08:32:19 AM UTC 24
Finished Aug 21 08:35:52 AM UTC 24
Peak memory 3033328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3329021974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.3329021974
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.439628749
Short name T906
Test name
Test status
Simulation time 591059241 ps
CPU time 4.98 seconds
Started Aug 21 08:32:31 AM UTC 24
Finished Aug 21 08:32:38 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=439628749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 24.i2c_target_nack_acqfull.439628749
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.3874008581
Short name T907
Test name
Test status
Simulation time 2199669301 ps
CPU time 5.55 seconds
Started Aug 21 08:32:32 AM UTC 24
Finished Aug 21 08:32:39 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3874008581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_nack_acqfull_addr.3874008581
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_perf.2904287814
Short name T825
Test name
Test status
Simulation time 3546976243 ps
CPU time 7.85 seconds
Started Aug 21 08:32:25 AM UTC 24
Finished Aug 21 08:32:34 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2904287814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 24.i2c_target_perf.2904287814
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.302012091
Short name T897
Test name
Test status
Simulation time 1534079481 ps
CPU time 3.23 seconds
Started Aug 21 08:32:30 AM UTC 24
Finished Aug 21 08:32:35 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=302012091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 24.i2c_target_smbus_maxlen.302012091
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.2030600155
Short name T886
Test name
Test status
Simulation time 792255886 ps
CPU time 10.42 seconds
Started Aug 21 08:32:13 AM UTC 24
Finished Aug 21 08:32:24 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2030600155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_targ
et_smoke.2030600155
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.4211531589
Short name T1528
Test name
Test status
Simulation time 57927043047 ps
CPU time 734.32 seconds
Started Aug 21 08:32:26 AM UTC 24
Finished Aug 21 08:44:47 AM UTC 24
Peak memory 7557396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=4211531589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 24.i2c_target_stress_all.4211531589
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_stress_rd.2859923755
Short name T915
Test name
Test status
Simulation time 5754064624 ps
CPU time 29.96 seconds
Started Aug 21 08:32:13 AM UTC 24
Finished Aug 21 08:32:44 AM UTC 24
Peak memory 243924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2859923755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stress_rd.2859923755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.193652821
Short name T882
Test name
Test status
Simulation time 13184741970 ps
CPU time 8.34 seconds
Started Aug 21 08:32:13 AM UTC 24
Finished Aug 21 08:32:22 AM UTC 24
Peak memory 216708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=193652821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_t
arget_stress_wr.193652821
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_stretch.2742586842
Short name T884
Test name
Test status
Simulation time 1915527403 ps
CPU time 6.85 seconds
Started Aug 21 08:32:16 AM UTC 24
Finished Aug 21 08:32:24 AM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2742586842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_stretch.2742586842
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.2048369020
Short name T894
Test name
Test status
Simulation time 6167232171 ps
CPU time 13.37 seconds
Started Aug 21 08:32:19 AM UTC 24
Finished Aug 21 08:32:34 AM UTC 24
Peak memory 233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2048369020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_timeout.2048369020
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.2408936
Short name T902
Test name
Test status
Simulation time 277597704 ps
CPU time 5.09 seconds
Started Aug 21 08:32:30 AM UTC 24
Finished Aug 21 08:32:37 AM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2408936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 24.i2c_target_tx_stretch_ctrl.2408936
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_alert_test.4201503969
Short name T934
Test name
Test status
Simulation time 59701454 ps
CPU time 0.99 seconds
Started Aug 21 08:32:54 AM UTC 24
Finished Aug 21 08:32:56 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4201503969 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.4201503969
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_error_intr.1285863355
Short name T913
Test name
Test status
Simulation time 395366976 ps
CPU time 4.28 seconds
Started Aug 21 08:32:38 AM UTC 24
Finished Aug 21 08:32:44 AM UTC 24
Peak memory 233784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1285863355 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1285863355
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.1515337
Short name T928
Test name
Test status
Simulation time 1386440956 ps
CPU time 16.46 seconds
Started Aug 21 08:32:36 AM UTC 24
Finished Aug 21 08:32:54 AM UTC 24
Peak memory 274480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1515337 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty.1515337
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.3447653696
Short name T980
Test name
Test status
Simulation time 19545727251 ps
CPU time 69.6 seconds
Started Aug 21 08:32:37 AM UTC 24
Finished Aug 21 08:33:48 AM UTC 24
Peak memory 577972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447653696 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3447653696
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.3129064821
Short name T955
Test name
Test status
Simulation time 1448718997 ps
CPU time 41.01 seconds
Started Aug 21 08:32:35 AM UTC 24
Finished Aug 21 08:33:17 AM UTC 24
Peak memory 577684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3129064821 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3129064821
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.4244704271
Short name T905
Test name
Test status
Simulation time 82969060 ps
CPU time 1.47 seconds
Started Aug 21 08:32:35 AM UTC 24
Finished Aug 21 08:32:37 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4244704271 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt.4244704271
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.3766948027
Short name T916
Test name
Test status
Simulation time 273309132 ps
CPU time 8.68 seconds
Started Aug 21 08:32:36 AM UTC 24
Finished Aug 21 08:32:46 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3766948027 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.3766948027
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_watermark.3012450293
Short name T1035
Test name
Test status
Simulation time 16207520174 ps
CPU time 119.69 seconds
Started Aug 21 08:32:35 AM UTC 24
Finished Aug 21 08:34:37 AM UTC 24
Peak memory 1253576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3012450293 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3012450293
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.162143234
Short name T947
Test name
Test status
Simulation time 2380505836 ps
CPU time 17.5 seconds
Started Aug 21 08:32:49 AM UTC 24
Finished Aug 21 08:33:07 AM UTC 24
Peak memory 216972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=162143234 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.162143234
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_override.2409151308
Short name T900
Test name
Test status
Simulation time 34343138 ps
CPU time 0.94 seconds
Started Aug 21 08:32:35 AM UTC 24
Finished Aug 21 08:32:37 AM UTC 24
Peak memory 215036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2409151308 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2409151308
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_perf.3876021902
Short name T923
Test name
Test status
Simulation time 3071865553 ps
CPU time 12.9 seconds
Started Aug 21 08:32:37 AM UTC 24
Finished Aug 21 08:32:51 AM UTC 24
Peak memory 241928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3876021902 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3876021902
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.2222893849
Short name T912
Test name
Test status
Simulation time 758591447 ps
CPU time 3.52 seconds
Started Aug 21 08:32:38 AM UTC 24
Finished Aug 21 08:32:43 AM UTC 24
Peak memory 216608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2222893849 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.2222893849
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.3089659388
Short name T922
Test name
Test status
Simulation time 1133192891 ps
CPU time 53.48 seconds
Started Aug 21 08:32:35 AM UTC 24
Finished Aug 21 08:33:30 AM UTC 24
Peak memory 325392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3089659388 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3089659388
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.3368826648
Short name T921
Test name
Test status
Simulation time 1352328226 ps
CPU time 9.77 seconds
Started Aug 21 08:32:38 AM UTC 24
Finished Aug 21 08:32:49 AM UTC 24
Peak memory 233544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3368826648 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3368826648
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.3365563934
Short name T930
Test name
Test status
Simulation time 1613556663 ps
CPU time 5.63 seconds
Started Aug 21 08:32:47 AM UTC 24
Finished Aug 21 08:32:54 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3365563934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.3365563934
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.2918680204
Short name T919
Test name
Test status
Simulation time 294890539 ps
CPU time 1.73 seconds
Started Aug 21 08:32:45 AM UTC 24
Finished Aug 21 08:32:48 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2918680204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_fifo_reset_acq.2918680204
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.3401912484
Short name T918
Test name
Test status
Simulation time 171508050 ps
CPU time 1.35 seconds
Started Aug 21 08:32:45 AM UTC 24
Finished Aug 21 08:32:48 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3401912484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_fifo_reset_tx.3401912484
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.273418884
Short name T927
Test name
Test status
Simulation time 384536824 ps
CPU time 3.53 seconds
Started Aug 21 08:32:49 AM UTC 24
Finished Aug 21 08:32:53 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=273418884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.273418884
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.3838230197
Short name T926
Test name
Test status
Simulation time 165341941 ps
CPU time 2.44 seconds
Started Aug 21 08:32:50 AM UTC 24
Finished Aug 21 08:32:53 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3838230197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.3838230197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.3752419343
Short name T920
Test name
Test status
Simulation time 3519487452 ps
CPU time 5.82 seconds
Started Aug 21 08:32:42 AM UTC 24
Finished Aug 21 08:32:49 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3752419343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.3752419343
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.953355253
Short name T1050
Test name
Test status
Simulation time 12057314632 ps
CPU time 131.85 seconds
Started Aug 21 08:32:42 AM UTC 24
Finished Aug 21 08:34:57 AM UTC 24
Peak memory 2101672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=953355253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.953355253
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.4036204763
Short name T937
Test name
Test status
Simulation time 545934182 ps
CPU time 4.12 seconds
Started Aug 21 08:32:52 AM UTC 24
Finished Aug 21 08:32:57 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4036204763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 25.i2c_target_nack_acqfull.4036204763
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.3721483435
Short name T938
Test name
Test status
Simulation time 880267706 ps
CPU time 4.33 seconds
Started Aug 21 08:32:53 AM UTC 24
Finished Aug 21 08:32:58 AM UTC 24
Peak memory 216552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3721483435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_nack_acqfull_addr.3721483435
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_perf.1199482342
Short name T929
Test name
Test status
Simulation time 2303251487 ps
CPU time 7.43 seconds
Started Aug 21 08:32:45 AM UTC 24
Finished Aug 21 08:32:54 AM UTC 24
Peak memory 233516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1199482342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 25.i2c_target_perf.1199482342
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.1327319369
Short name T933
Test name
Test status
Simulation time 740375173 ps
CPU time 3.01 seconds
Started Aug 21 08:32:52 AM UTC 24
Finished Aug 21 08:32:56 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1327319369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 25.i2c_target_smbus_maxlen.1327319369
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.291549972
Short name T924
Test name
Test status
Simulation time 825393276 ps
CPU time 12.46 seconds
Started Aug 21 08:32:39 AM UTC 24
Finished Aug 21 08:32:52 AM UTC 24
Peak memory 227140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=291549972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_targe
t_smoke.291549972
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.637028858
Short name T985
Test name
Test status
Simulation time 31780512033 ps
CPU time 67.71 seconds
Started Aug 21 08:32:46 AM UTC 24
Finished Aug 21 08:33:56 AM UTC 24
Peak memory 819420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=637028858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_stress_all.637028858
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.4182114928
Short name T959
Test name
Test status
Simulation time 1515573990 ps
CPU time 38.74 seconds
Started Aug 21 08:32:40 AM UTC 24
Finished Aug 21 08:33:20 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4182114928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stress_rd.4182114928
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_stress_wr.1221433521
Short name T954
Test name
Test status
Simulation time 22467247641 ps
CPU time 36.49 seconds
Started Aug 21 08:32:39 AM UTC 24
Finished Aug 21 08:33:16 AM UTC 24
Peak memory 348320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1221433521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stress_wr.1221433521
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_stretch.4095430764
Short name T1012
Test name
Test status
Simulation time 5182900529 ps
CPU time 91.88 seconds
Started Aug 21 08:32:42 AM UTC 24
Finished Aug 21 08:34:16 AM UTC 24
Peak memory 1505696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4095430764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_stretch.4095430764
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.1328001476
Short name T925
Test name
Test status
Simulation time 8286782787 ps
CPU time 7.93 seconds
Started Aug 21 08:32:43 AM UTC 24
Finished Aug 21 08:32:52 AM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1328001476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_timeout.1328001476
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.792447016
Short name T940
Test name
Test status
Simulation time 650424781 ps
CPU time 9.65 seconds
Started Aug 21 08:32:50 AM UTC 24
Finished Aug 21 08:33:01 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=792447016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_tx_stretch_ctrl.792447016
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_alert_test.890746816
Short name T969
Test name
Test status
Simulation time 18576350 ps
CPU time 0.92 seconds
Started Aug 21 08:33:23 AM UTC 24
Finished Aug 21 08:33:25 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=890746816 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.890746816
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.2941002405
Short name T942
Test name
Test status
Simulation time 257513089 ps
CPU time 2.38 seconds
Started Aug 21 08:33:00 AM UTC 24
Finished Aug 21 08:33:04 AM UTC 24
Peak memory 233144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2941002405 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.2941002405
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.3647832357
Short name T943
Test name
Test status
Simulation time 1420826428 ps
CPU time 6.9 seconds
Started Aug 21 08:32:57 AM UTC 24
Finished Aug 21 08:33:05 AM UTC 24
Peak memory 296996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3647832357 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.3647832357
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_full.2497131853
Short name T1039
Test name
Test status
Simulation time 3340562684 ps
CPU time 102.59 seconds
Started Aug 21 08:32:58 AM UTC 24
Finished Aug 21 08:34:43 AM UTC 24
Peak memory 569508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2497131853 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2497131853
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.1031581152
Short name T989
Test name
Test status
Simulation time 8555780236 ps
CPU time 62.38 seconds
Started Aug 21 08:32:55 AM UTC 24
Finished Aug 21 08:34:00 AM UTC 24
Peak memory 739600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1031581152 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1031581152
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.3334332124
Short name T939
Test name
Test status
Simulation time 497839514 ps
CPU time 1.93 seconds
Started Aug 21 08:32:57 AM UTC 24
Finished Aug 21 08:33:00 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3334332124 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt.3334332124
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.69388515
Short name T944
Test name
Test status
Simulation time 143661724 ps
CPU time 7.75 seconds
Started Aug 21 08:32:58 AM UTC 24
Finished Aug 21 08:33:07 AM UTC 24
Peak memory 239764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=69388515 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.69388515
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.549407786
Short name T125
Test name
Test status
Simulation time 6544117863 ps
CPU time 67.01 seconds
Started Aug 21 08:32:54 AM UTC 24
Finished Aug 21 08:34:03 AM UTC 24
Peak memory 1051108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=549407786 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.549407786
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.1433891392
Short name T973
Test name
Test status
Simulation time 654229785 ps
CPU time 9.97 seconds
Started Aug 21 08:33:18 AM UTC 24
Finished Aug 21 08:33:29 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1433891392 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.1433891392
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_override.4188684071
Short name T935
Test name
Test status
Simulation time 43094094 ps
CPU time 1.01 seconds
Started Aug 21 08:32:54 AM UTC 24
Finished Aug 21 08:32:56 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4188684071 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.4188684071
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_perf.3370883376
Short name T1160
Test name
Test status
Simulation time 5857975287 ps
CPU time 230.67 seconds
Started Aug 21 08:32:58 AM UTC 24
Finished Aug 21 08:36:52 AM UTC 24
Peak memory 551312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3370883376 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3370883376
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.1505637201
Short name T951
Test name
Test status
Simulation time 541539807 ps
CPU time 14.04 seconds
Started Aug 21 08:32:58 AM UTC 24
Finished Aug 21 08:33:13 AM UTC 24
Peak memory 274548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1505637201 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.1505637201
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.2815312493
Short name T960
Test name
Test status
Simulation time 3345230913 ps
CPU time 37.9 seconds
Started Aug 21 08:32:54 AM UTC 24
Finished Aug 21 08:33:34 AM UTC 24
Peak memory 368812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2815312493 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.2815312493
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.3575561434
Short name T948
Test name
Test status
Simulation time 2208876563 ps
CPU time 8.72 seconds
Started Aug 21 08:32:59 AM UTC 24
Finished Aug 21 08:33:09 AM UTC 24
Peak memory 229080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3575561434 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3575561434
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.556011242
Short name T971
Test name
Test status
Simulation time 914771647 ps
CPU time 8.76 seconds
Started Aug 21 08:33:16 AM UTC 24
Finished Aug 21 08:33:26 AM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=556011242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_bad_addr.556011242
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.300189276
Short name T952
Test name
Test status
Simulation time 229604632 ps
CPU time 2.37 seconds
Started Aug 21 08:33:12 AM UTC 24
Finished Aug 21 08:33:15 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=300189276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_fifo_reset_acq.300189276
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.1483088825
Short name T953
Test name
Test status
Simulation time 896888890 ps
CPU time 1.7 seconds
Started Aug 21 08:33:13 AM UTC 24
Finished Aug 21 08:33:16 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1483088825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_fifo_reset_tx.1483088825
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.1186211676
Short name T967
Test name
Test status
Simulation time 1755589860 ps
CPU time 3.65 seconds
Started Aug 21 08:33:19 AM UTC 24
Finished Aug 21 08:33:24 AM UTC 24
Peak memory 216636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1186211676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.1186211676
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.2375880648
Short name T965
Test name
Test status
Simulation time 253788972 ps
CPU time 1.78 seconds
Started Aug 21 08:33:21 AM UTC 24
Finished Aug 21 08:33:23 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2375880648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.2375880648
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_hrst.2351218520
Short name T957
Test name
Test status
Simulation time 459652130 ps
CPU time 2.35 seconds
Started Aug 21 08:33:16 AM UTC 24
Finished Aug 21 08:33:20 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2351218520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 26.i2c_target_hrst.2351218520
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.4121736528
Short name T958
Test name
Test status
Simulation time 3510720061 ps
CPU time 11.22 seconds
Started Aug 21 08:33:08 AM UTC 24
Finished Aug 21 08:33:20 AM UTC 24
Peak memory 243952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=4121736528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.4121736528
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.1019545467
Short name T986
Test name
Test status
Simulation time 22277059169 ps
CPU time 47.45 seconds
Started Aug 21 08:33:09 AM UTC 24
Finished Aug 21 08:33:57 AM UTC 24
Peak memory 1204464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1019545467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1019545467
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.3362365231
Short name T899
Test name
Test status
Simulation time 545561862 ps
CPU time 3.44 seconds
Started Aug 21 08:33:22 AM UTC 24
Finished Aug 21 08:33:26 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3362365231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 26.i2c_target_nack_acqfull.3362365231
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.1091217937
Short name T936
Test name
Test status
Simulation time 2168135182 ps
CPU time 4.26 seconds
Started Aug 21 08:33:22 AM UTC 24
Finished Aug 21 08:33:27 AM UTC 24
Peak memory 216908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1091217937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_nack_acqfull_addr.1091217937
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_nack_txstretch.261930552
Short name T970
Test name
Test status
Simulation time 646242289 ps
CPU time 2.08 seconds
Started Aug 21 08:33:22 AM UTC 24
Finished Aug 21 08:33:25 AM UTC 24
Peak memory 233500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=261930552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_nack_txstretch.261930552
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_perf.2009334082
Short name T963
Test name
Test status
Simulation time 590442778 ps
CPU time 6.97 seconds
Started Aug 21 08:33:14 AM UTC 24
Finished Aug 21 08:33:22 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2009334082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 26.i2c_target_perf.2009334082
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.3519988584
Short name T968
Test name
Test status
Simulation time 1789471650 ps
CPU time 3.12 seconds
Started Aug 21 08:33:21 AM UTC 24
Finished Aug 21 08:33:25 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3519988584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 26.i2c_target_smbus_maxlen.3519988584
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.663282824
Short name T964
Test name
Test status
Simulation time 5608813777 ps
CPU time 19.89 seconds
Started Aug 21 08:33:02 AM UTC 24
Finished Aug 21 08:33:23 AM UTC 24
Peak memory 233760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=663282824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_targe
t_smoke.663282824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.1466150940
Short name T1072
Test name
Test status
Simulation time 174947640809 ps
CPU time 117.85 seconds
Started Aug 21 08:33:14 AM UTC 24
Finished Aug 21 08:35:14 AM UTC 24
Peak memory 897252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1466150940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 26.i2c_target_stress_all.1466150940
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.2469331694
Short name T974
Test name
Test status
Simulation time 2466621225 ps
CPU time 27.9 seconds
Started Aug 21 08:33:05 AM UTC 24
Finished Aug 21 08:33:35 AM UTC 24
Peak memory 233644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2469331694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stress_rd.2469331694
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.690159979
Short name T1176
Test name
Test status
Simulation time 47373165260 ps
CPU time 251.16 seconds
Started Aug 21 08:33:04 AM UTC 24
Finished Aug 21 08:37:19 AM UTC 24
Peak memory 3619300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=690159979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_t
arget_stress_wr.690159979
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.2325390496
Short name T949
Test name
Test status
Simulation time 1457547979 ps
CPU time 3.15 seconds
Started Aug 21 08:33:07 AM UTC 24
Finished Aug 21 08:33:12 AM UTC 24
Peak memory 237668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2325390496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_stretch.2325390496
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.2601440214
Short name T956
Test name
Test status
Simulation time 11098139430 ps
CPU time 8.36 seconds
Started Aug 21 08:33:09 AM UTC 24
Finished Aug 21 08:33:18 AM UTC 24
Peak memory 233924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2601440214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_timeout.2601440214
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.1755852372
Short name T966
Test name
Test status
Simulation time 121705276 ps
CPU time 2.17 seconds
Started Aug 21 08:33:21 AM UTC 24
Finished Aug 21 08:33:24 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1755852372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.1755852372
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_alert_test.4131457486
Short name T998
Test name
Test status
Simulation time 49508178 ps
CPU time 0.99 seconds
Started Aug 21 08:34:00 AM UTC 24
Finished Aug 21 08:34:02 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4131457486 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.4131457486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.921795957
Short name T893
Test name
Test status
Simulation time 230007353 ps
CPU time 4.38 seconds
Started Aug 21 08:33:29 AM UTC 24
Finished Aug 21 08:33:34 AM UTC 24
Peak memory 243812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=921795957 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.921795957
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.3840524038
Short name T975
Test name
Test status
Simulation time 1965373943 ps
CPU time 11.74 seconds
Started Aug 21 08:33:25 AM UTC 24
Finished Aug 21 08:33:38 AM UTC 24
Peak memory 309328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3840524038 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty.3840524038
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.2847966733
Short name T1069
Test name
Test status
Simulation time 2134018803 ps
CPU time 102.09 seconds
Started Aug 21 08:33:27 AM UTC 24
Finished Aug 21 08:35:12 AM UTC 24
Peak memory 383052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2847966733 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.2847966733
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.4173157278
Short name T996
Test name
Test status
Simulation time 2953293695 ps
CPU time 35.05 seconds
Started Aug 21 08:33:25 AM UTC 24
Finished Aug 21 08:34:02 AM UTC 24
Peak memory 555212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4173157278 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.4173157278
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.381511988
Short name T903
Test name
Test status
Simulation time 102423469 ps
CPU time 1.41 seconds
Started Aug 21 08:33:25 AM UTC 24
Finished Aug 21 08:33:28 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=381511988 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt.381511988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.912458661
Short name T950
Test name
Test status
Simulation time 407726161 ps
CPU time 6.74 seconds
Started Aug 21 08:33:26 AM UTC 24
Finished Aug 21 08:33:34 AM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=912458661 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.912458661
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.1532742234
Short name T1217
Test name
Test status
Simulation time 9317713069 ps
CPU time 261.24 seconds
Started Aug 21 08:33:24 AM UTC 24
Finished Aug 21 08:37:49 AM UTC 24
Peak memory 1344000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1532742234 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1532742234
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_override.1271944042
Short name T972
Test name
Test status
Simulation time 92869294 ps
CPU time 1.04 seconds
Started Aug 21 08:33:24 AM UTC 24
Finished Aug 21 08:33:26 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1271944042 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1271944042
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_perf.2497992798
Short name T995
Test name
Test status
Simulation time 2592590166 ps
CPU time 32.8 seconds
Started Aug 21 08:33:27 AM UTC 24
Finished Aug 21 08:34:02 AM UTC 24
Peak memory 241820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2497992798 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2497992798
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.764825254
Short name T932
Test name
Test status
Simulation time 288026523 ps
CPU time 4.44 seconds
Started Aug 21 08:33:27 AM UTC 24
Finished Aug 21 08:33:33 AM UTC 24
Peak memory 233536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=764825254 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.764825254
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.2583534293
Short name T1004
Test name
Test status
Simulation time 21062022237 ps
CPU time 39.78 seconds
Started Aug 21 08:33:24 AM UTC 24
Finished Aug 21 08:34:05 AM UTC 24
Peak memory 364884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2583534293 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2583534293
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.2656223314
Short name T1001
Test name
Test status
Simulation time 1695673800 ps
CPU time 34.58 seconds
Started Aug 21 08:33:28 AM UTC 24
Finished Aug 21 08:34:04 AM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2656223314 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2656223314
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.1576804901
Short name T984
Test name
Test status
Simulation time 617361622 ps
CPU time 5.82 seconds
Started Aug 21 08:33:48 AM UTC 24
Finished Aug 21 08:33:55 AM UTC 24
Peak memory 230980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1576804901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1576804901
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.3383421958
Short name T978
Test name
Test status
Simulation time 229384120 ps
CPU time 2.36 seconds
Started Aug 21 08:33:42 AM UTC 24
Finished Aug 21 08:33:46 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3383421958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_acq.3383421958
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.3958692272
Short name T979
Test name
Test status
Simulation time 824902983 ps
CPU time 1.71 seconds
Started Aug 21 08:33:44 AM UTC 24
Finished Aug 21 08:33:47 AM UTC 24
Peak memory 218572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3958692272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_fifo_reset_tx.3958692272
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.526884181
Short name T991
Test name
Test status
Simulation time 1177210630 ps
CPU time 4.98 seconds
Started Aug 21 08:33:54 AM UTC 24
Finished Aug 21 08:34:00 AM UTC 24
Peak memory 216712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=526884181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.526884181
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.2827673033
Short name T987
Test name
Test status
Simulation time 119919100 ps
CPU time 1.54 seconds
Started Aug 21 08:33:55 AM UTC 24
Finished Aug 21 08:33:58 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2827673033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.2827673033
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.2533647285
Short name T976
Test name
Test status
Simulation time 1386872937 ps
CPU time 7.19 seconds
Started Aug 21 08:33:35 AM UTC 24
Finished Aug 21 08:33:43 AM UTC 24
Peak memory 233676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2533647285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_intr_smoke.2533647285
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.59819802
Short name T1040
Test name
Test status
Simulation time 9040400194 ps
CPU time 65.94 seconds
Started Aug 21 08:33:35 AM UTC 24
Finished Aug 21 08:34:43 AM UTC 24
Peak memory 1515948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=59819802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_intr_stress_wr.59819802
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.763970311
Short name T994
Test name
Test status
Simulation time 1489599271 ps
CPU time 3.73 seconds
Started Aug 21 08:33:56 AM UTC 24
Finished Aug 21 08:34:01 AM UTC 24
Peak memory 226772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=763970311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 27.i2c_target_nack_acqfull.763970311
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.3818286701
Short name T1000
Test name
Test status
Simulation time 455028950 ps
CPU time 3.51 seconds
Started Aug 21 08:33:58 AM UTC 24
Finished Aug 21 08:34:03 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3818286701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_nack_acqfull_addr.3818286701
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_nack_txstretch.3429921716
Short name T997
Test name
Test status
Simulation time 136018241 ps
CPU time 2.2 seconds
Started Aug 21 08:33:58 AM UTC 24
Finished Aug 21 08:34:02 AM UTC 24
Peak memory 233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3429921716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_nack_txstretch.3429921716
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_perf.3495879095
Short name T983
Test name
Test status
Simulation time 810307870 ps
CPU time 8.55 seconds
Started Aug 21 08:33:45 AM UTC 24
Finished Aug 21 08:33:54 AM UTC 24
Peak memory 233580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3495879095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 27.i2c_target_perf.3495879095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.2229609742
Short name T993
Test name
Test status
Simulation time 1699301530 ps
CPU time 3.84 seconds
Started Aug 21 08:33:56 AM UTC 24
Finished Aug 21 08:34:01 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2229609742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 27.i2c_target_smbus_maxlen.2229609742
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.1143276308
Short name T977
Test name
Test status
Simulation time 2571913223 ps
CPU time 11.98 seconds
Started Aug 21 08:33:31 AM UTC 24
Finished Aug 21 08:33:44 AM UTC 24
Peak memory 233632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1143276308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_targ
et_smoke.1143276308
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.3252396754
Short name T1323
Test name
Test status
Simulation time 35419403290 ps
CPU time 342.38 seconds
Started Aug 21 08:33:47 AM UTC 24
Finished Aug 21 08:39:33 AM UTC 24
Peak memory 4391392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3252396754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 27.i2c_target_stress_all.3252396754
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.2617577821
Short name T982
Test name
Test status
Simulation time 5473934787 ps
CPU time 17.72 seconds
Started Aug 21 08:33:34 AM UTC 24
Finished Aug 21 08:33:53 AM UTC 24
Peak memory 233904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2617577821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stress_rd.2617577821
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.1129073375
Short name T988
Test name
Test status
Simulation time 35976422220 ps
CPU time 26.22 seconds
Started Aug 21 08:33:32 AM UTC 24
Finished Aug 21 08:33:59 AM UTC 24
Peak memory 710812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1129073375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stress_wr.1129073375
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_stretch.3021467641
Short name T990
Test name
Test status
Simulation time 5291658002 ps
CPU time 23.62 seconds
Started Aug 21 08:33:35 AM UTC 24
Finished Aug 21 08:34:00 AM UTC 24
Peak memory 671980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3021467641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_stretch.3021467641
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.1790749621
Short name T981
Test name
Test status
Simulation time 5747878164 ps
CPU time 12.68 seconds
Started Aug 21 08:33:35 AM UTC 24
Finished Aug 21 08:33:49 AM UTC 24
Peak memory 234008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1790749621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_timeout.1790749621
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.3562839228
Short name T1005
Test name
Test status
Simulation time 811868683 ps
CPU time 11.5 seconds
Started Aug 21 08:33:55 AM UTC 24
Finished Aug 21 08:34:08 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3562839228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.3562839228
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_alert_test.2121867060
Short name T1026
Test name
Test status
Simulation time 25700498 ps
CPU time 0.91 seconds
Started Aug 21 08:34:25 AM UTC 24
Finished Aug 21 08:34:27 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2121867060 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2121867060
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.410774103
Short name T1011
Test name
Test status
Simulation time 200040015 ps
CPU time 9.85 seconds
Started Aug 21 08:34:04 AM UTC 24
Finished Aug 21 08:34:15 AM UTC 24
Peak memory 247904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=410774103 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.410774103
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.1322188744
Short name T1008
Test name
Test status
Simulation time 191458615 ps
CPU time 10.51 seconds
Started Aug 21 08:34:02 AM UTC 24
Finished Aug 21 08:34:13 AM UTC 24
Peak memory 247912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1322188744 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty.1322188744
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.3686638148
Short name T1134
Test name
Test status
Simulation time 9966913131 ps
CPU time 138.48 seconds
Started Aug 21 08:34:03 AM UTC 24
Finished Aug 21 08:36:24 AM UTC 24
Peak memory 540876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3686638148 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3686638148
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.3131298656
Short name T1049
Test name
Test status
Simulation time 1979092191 ps
CPU time 51.67 seconds
Started Aug 21 08:34:02 AM UTC 24
Finished Aug 21 08:34:55 AM UTC 24
Peak memory 643168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3131298656 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3131298656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.2931532095
Short name T1003
Test name
Test status
Simulation time 1223611545 ps
CPU time 1.81 seconds
Started Aug 21 08:34:02 AM UTC 24
Finished Aug 21 08:34:05 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2931532095 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.2931532095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.372498393
Short name T1007
Test name
Test status
Simulation time 597586486 ps
CPU time 6.21 seconds
Started Aug 21 08:34:03 AM UTC 24
Finished Aug 21 08:34:10 AM UTC 24
Peak memory 241748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=372498393 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.372498393
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_watermark.3213483150
Short name T1052
Test name
Test status
Simulation time 20708720663 ps
CPU time 123.48 seconds
Started Aug 21 08:34:01 AM UTC 24
Finished Aug 21 08:36:06 AM UTC 24
Peak memory 1497488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3213483150 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3213483150
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.3471870650
Short name T273
Test name
Test status
Simulation time 1227630769 ps
CPU time 5.16 seconds
Started Aug 21 08:34:17 AM UTC 24
Finished Aug 21 08:34:24 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3471870650 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3471870650
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_override.3039809683
Short name T999
Test name
Test status
Simulation time 28800320 ps
CPU time 1.13 seconds
Started Aug 21 08:34:01 AM UTC 24
Finished Aug 21 08:34:03 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3039809683 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3039809683
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_perf.1432823072
Short name T1647
Test name
Test status
Simulation time 27963366484 ps
CPU time 763.89 seconds
Started Aug 21 08:34:03 AM UTC 24
Finished Aug 21 08:46:55 AM UTC 24
Peak memory 2359616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1432823072 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1432823072
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.16939726
Short name T1006
Test name
Test status
Simulation time 104403769 ps
CPU time 5.69 seconds
Started Aug 21 08:34:03 AM UTC 24
Finished Aug 21 08:34:10 AM UTC 24
Peak memory 241116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16939726 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.16939726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.3547593563
Short name T1023
Test name
Test status
Simulation time 9558653471 ps
CPU time 22.31 seconds
Started Aug 21 08:34:01 AM UTC 24
Finished Aug 21 08:34:24 AM UTC 24
Peak memory 293092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3547593563 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3547593563
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.351221572
Short name T1038
Test name
Test status
Simulation time 691168977 ps
CPU time 34.54 seconds
Started Aug 21 08:34:04 AM UTC 24
Finished Aug 21 08:34:40 AM UTC 24
Peak memory 226708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=351221572 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.351221572
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_bad_addr.1331108624
Short name T1021
Test name
Test status
Simulation time 2686694416 ps
CPU time 5.86 seconds
Started Aug 21 08:34:16 AM UTC 24
Finished Aug 21 08:34:23 AM UTC 24
Peak memory 227256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1331108624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1331108624
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.2345490462
Short name T1014
Test name
Test status
Simulation time 142090405 ps
CPU time 1.71 seconds
Started Aug 21 08:34:14 AM UTC 24
Finished Aug 21 08:34:17 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2345490462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_acq.2345490462
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.3672801302
Short name T1016
Test name
Test status
Simulation time 243964132 ps
CPU time 2.8 seconds
Started Aug 21 08:34:15 AM UTC 24
Finished Aug 21 08:34:19 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3672801302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_fifo_reset_tx.3672801302
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.3429367522
Short name T1019
Test name
Test status
Simulation time 166974900 ps
CPU time 2.24 seconds
Started Aug 21 08:34:19 AM UTC 24
Finished Aug 21 08:34:23 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3429367522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.3429367522
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.1087895191
Short name T1024
Test name
Test status
Simulation time 162167444 ps
CPU time 2.39 seconds
Started Aug 21 08:34:22 AM UTC 24
Finished Aug 21 08:34:25 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1087895191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.1087895191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.2720821083
Short name T1015
Test name
Test status
Simulation time 1220392233 ps
CPU time 9.09 seconds
Started Aug 21 08:34:07 AM UTC 24
Finished Aug 21 08:34:17 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2720821083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.2720821083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.811367558
Short name T1143
Test name
Test status
Simulation time 15509537514 ps
CPU time 147.68 seconds
Started Aug 21 08:34:09 AM UTC 24
Finished Aug 21 08:36:39 AM UTC 24
Peak memory 2244712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=811367558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.811367558
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.850504982
Short name T1030
Test name
Test status
Simulation time 7728745199 ps
CPU time 4.95 seconds
Started Aug 21 08:34:24 AM UTC 24
Finished Aug 21 08:34:30 AM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=850504982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 28.i2c_target_nack_acqfull.850504982
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.3133631299
Short name T1029
Test name
Test status
Simulation time 436720588 ps
CPU time 4.7 seconds
Started Aug 21 08:34:24 AM UTC 24
Finished Aug 21 08:34:30 AM UTC 24
Peak memory 216392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3133631299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_nack_acqfull_addr.3133631299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_perf.2257424321
Short name T1022
Test name
Test status
Simulation time 1878558507 ps
CPU time 7.63 seconds
Started Aug 21 08:34:15 AM UTC 24
Finished Aug 21 08:34:24 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2257424321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 28.i2c_target_perf.2257424321
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.1223092291
Short name T1028
Test name
Test status
Simulation time 3650709564 ps
CPU time 3.53 seconds
Started Aug 21 08:34:23 AM UTC 24
Finished Aug 21 08:34:27 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1223092291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 28.i2c_target_smbus_maxlen.1223092291
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.1130618319
Short name T1010
Test name
Test status
Simulation time 3583874732 ps
CPU time 9.16 seconds
Started Aug 21 08:34:04 AM UTC 24
Finished Aug 21 08:34:15 AM UTC 24
Peak memory 233908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1130618319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_targ
et_smoke.1130618319
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.2148114233
Short name T1742
Test name
Test status
Simulation time 55490361047 ps
CPU time 1362.35 seconds
Started Aug 21 08:34:16 AM UTC 24
Finished Aug 21 08:57:12 AM UTC 24
Peak memory 10395784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2148114233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 28.i2c_target_stress_all.2148114233
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.1720478600
Short name T1033
Test name
Test status
Simulation time 2960789723 ps
CPU time 24.8 seconds
Started Aug 21 08:34:06 AM UTC 24
Finished Aug 21 08:34:32 AM UTC 24
Peak memory 260268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1720478600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stress_rd.1720478600
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.1170225247
Short name T1031
Test name
Test status
Simulation time 39389864466 ps
CPU time 25.26 seconds
Started Aug 21 08:34:04 AM UTC 24
Finished Aug 21 08:34:31 AM UTC 24
Peak memory 546960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1170225247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stress_wr.1170225247
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_stretch.939503328
Short name T1017
Test name
Test status
Simulation time 3785830570 ps
CPU time 14.71 seconds
Started Aug 21 08:34:06 AM UTC 24
Finished Aug 21 08:34:21 AM UTC 24
Peak memory 420008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=939503328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_tar
get_stretch.939503328
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.1757707047
Short name T1018
Test name
Test status
Simulation time 5381051746 ps
CPU time 9.94 seconds
Started Aug 21 08:34:11 AM UTC 24
Finished Aug 21 08:34:22 AM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1757707047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_timeout.1757707047
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.2574164559
Short name T1043
Test name
Test status
Simulation time 1177782114 ps
CPU time 20.91 seconds
Started Aug 21 08:34:23 AM UTC 24
Finished Aug 21 08:34:45 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2574164559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.2574164559
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_alert_test.2415028583
Short name T1056
Test name
Test status
Simulation time 18917069 ps
CPU time 1.03 seconds
Started Aug 21 08:34:59 AM UTC 24
Finished Aug 21 08:35:01 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2415028583 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2415028583
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_error_intr.2626779495
Short name T1034
Test name
Test status
Simulation time 196556983 ps
CPU time 3.92 seconds
Started Aug 21 08:34:32 AM UTC 24
Finished Aug 21 08:34:37 AM UTC 24
Peak memory 228892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2626779495 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2626779495
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.2495487562
Short name T1037
Test name
Test status
Simulation time 1831359932 ps
CPU time 9.93 seconds
Started Aug 21 08:34:28 AM UTC 24
Finished Aug 21 08:34:40 AM UTC 24
Peak memory 325864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2495487562 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty.2495487562
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.4263430512
Short name T1082
Test name
Test status
Simulation time 2775060920 ps
CPU time 59.04 seconds
Started Aug 21 08:34:29 AM UTC 24
Finished Aug 21 08:35:29 AM UTC 24
Peak memory 454888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4263430512 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.4263430512
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.3628488592
Short name T1106
Test name
Test status
Simulation time 1427344726 ps
CPU time 85.03 seconds
Started Aug 21 08:34:26 AM UTC 24
Finished Aug 21 08:35:53 AM UTC 24
Peak memory 530552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3628488592 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3628488592
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.4101245327
Short name T1032
Test name
Test status
Simulation time 91568193 ps
CPU time 1.67 seconds
Started Aug 21 08:34:28 AM UTC 24
Finished Aug 21 08:34:31 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4101245327 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt.4101245327
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.352156991
Short name T1036
Test name
Test status
Simulation time 243224169 ps
CPU time 8.16 seconds
Started Aug 21 08:34:28 AM UTC 24
Finished Aug 21 08:34:38 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=352156991 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.352156991
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.3229670505
Short name T1201
Test name
Test status
Simulation time 19586141883 ps
CPU time 188.05 seconds
Started Aug 21 08:34:26 AM UTC 24
Finished Aug 21 08:37:37 AM UTC 24
Peak memory 1019876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3229670505 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3229670505
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.4247882358
Short name T283
Test name
Test status
Simulation time 1276120248 ps
CPU time 9.45 seconds
Started Aug 21 08:34:55 AM UTC 24
Finished Aug 21 08:35:06 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4247882358 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.4247882358
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_override.2337579359
Short name T1027
Test name
Test status
Simulation time 87130593 ps
CPU time 0.93 seconds
Started Aug 21 08:34:25 AM UTC 24
Finished Aug 21 08:34:27 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2337579359 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.2337579359
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_perf.2346767447
Short name T1042
Test name
Test status
Simulation time 235142603 ps
CPU time 11.34 seconds
Started Aug 21 08:34:31 AM UTC 24
Finished Aug 21 08:34:43 AM UTC 24
Peak memory 237364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2346767447 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2346767447
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.3532498969
Short name T1062
Test name
Test status
Simulation time 2867503012 ps
CPU time 30.27 seconds
Started Aug 21 08:34:31 AM UTC 24
Finished Aug 21 08:35:02 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3532498969 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.3532498969
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_smoke.691150986
Short name T1073
Test name
Test status
Simulation time 1122159918 ps
CPU time 47.68 seconds
Started Aug 21 08:34:25 AM UTC 24
Finished Aug 21 08:35:14 AM UTC 24
Peak memory 299312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=691150986 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.691150986
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.2414506110
Short name T1047
Test name
Test status
Simulation time 1031184245 ps
CPU time 21.63 seconds
Started Aug 21 08:34:32 AM UTC 24
Finished Aug 21 08:34:55 AM UTC 24
Peak memory 230936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2414506110 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2414506110
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_bad_addr.3033349125
Short name T1051
Test name
Test status
Simulation time 793286862 ps
CPU time 6.87 seconds
Started Aug 21 08:34:50 AM UTC 24
Finished Aug 21 08:34:58 AM UTC 24
Peak memory 227028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3033349125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3033349125
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.1891084661
Short name T1044
Test name
Test status
Simulation time 298661067 ps
CPU time 1.35 seconds
Started Aug 21 08:34:44 AM UTC 24
Finished Aug 21 08:34:46 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1891084661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_acq.1891084661
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.3488506801
Short name T1045
Test name
Test status
Simulation time 313030037 ps
CPU time 1.95 seconds
Started Aug 21 08:34:46 AM UTC 24
Finished Aug 21 08:34:49 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3488506801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_fifo_reset_tx.3488506801
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.4166717798
Short name T1055
Test name
Test status
Simulation time 447027440 ps
CPU time 4.41 seconds
Started Aug 21 08:34:55 AM UTC 24
Finished Aug 21 08:35:01 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4166717798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.4166717798
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.3713914032
Short name T1054
Test name
Test status
Simulation time 450249107 ps
CPU time 1.81 seconds
Started Aug 21 08:34:55 AM UTC 24
Finished Aug 21 08:34:58 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3713914032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.3713914032
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_hrst.1189118584
Short name T1025
Test name
Test status
Simulation time 286401785 ps
CPU time 2.88 seconds
Started Aug 21 08:34:50 AM UTC 24
Finished Aug 21 08:34:54 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1189118584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.i2c_target_hrst.1189118584
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.2388661217
Short name T1046
Test name
Test status
Simulation time 4535559276 ps
CPU time 9.24 seconds
Started Aug 21 08:34:41 AM UTC 24
Finished Aug 21 08:34:52 AM UTC 24
Peak memory 233648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2388661217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.2388661217
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.1345302482
Short name T1002
Test name
Test status
Simulation time 4755564982 ps
CPU time 4.47 seconds
Started Aug 21 08:34:43 AM UTC 24
Finished Aug 21 08:34:49 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1345302482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.1345302482
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.3704513510
Short name T1061
Test name
Test status
Simulation time 2750821036 ps
CPU time 4.53 seconds
Started Aug 21 08:34:57 AM UTC 24
Finished Aug 21 08:35:02 AM UTC 24
Peak memory 226964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3704513510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_target_nack_acqfull.3704513510
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.265625800
Short name T1063
Test name
Test status
Simulation time 559242442 ps
CPU time 4.56 seconds
Started Aug 21 08:34:58 AM UTC 24
Finished Aug 21 08:35:03 AM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=265625800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_nack_acqfull_addr.265625800
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_nack_txstretch.1668375482
Short name T1060
Test name
Test status
Simulation time 134903162 ps
CPU time 2.18 seconds
Started Aug 21 08:34:59 AM UTC 24
Finished Aug 21 08:35:02 AM UTC 24
Peak memory 233496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1668375482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_nack_txstretch.1668375482
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_perf.1005520878
Short name T1048
Test name
Test status
Simulation time 1246091269 ps
CPU time 7.06 seconds
Started Aug 21 08:34:47 AM UTC 24
Finished Aug 21 08:34:55 AM UTC 24
Peak memory 228816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1005520878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 29.i2c_target_perf.1005520878
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.1160457763
Short name T1057
Test name
Test status
Simulation time 493746162 ps
CPU time 3.51 seconds
Started Aug 21 08:34:56 AM UTC 24
Finished Aug 21 08:35:01 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1160457763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 29.i2c_target_smbus_maxlen.1160457763
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.3219465838
Short name T1059
Test name
Test status
Simulation time 1556057619 ps
CPU time 22.37 seconds
Started Aug 21 08:34:38 AM UTC 24
Finished Aug 21 08:35:02 AM UTC 24
Peak memory 227076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3219465838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_targ
et_smoke.3219465838
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_stress_all.2706934009
Short name T1144
Test name
Test status
Simulation time 13203177552 ps
CPU time 111.34 seconds
Started Aug 21 08:34:47 AM UTC 24
Finished Aug 21 08:36:40 AM UTC 24
Peak memory 1855716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2706934009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 29.i2c_target_stress_all.2706934009
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.2700664719
Short name T1058
Test name
Test status
Simulation time 430611356 ps
CPU time 20.82 seconds
Started Aug 21 08:34:39 AM UTC 24
Finished Aug 21 08:35:01 AM UTC 24
Peak memory 216708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2700664719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stress_rd.2700664719
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.1906115659
Short name T1103
Test name
Test status
Simulation time 39622047979 ps
CPU time 68.39 seconds
Started Aug 21 08:34:38 AM UTC 24
Finished Aug 21 08:35:48 AM UTC 24
Peak memory 1288352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1906115659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stress_wr.1906115659
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.1119043847
Short name T1041
Test name
Test status
Simulation time 220584430 ps
CPU time 1.7 seconds
Started Aug 21 08:34:40 AM UTC 24
Finished Aug 21 08:34:43 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1119043847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_stretch.1119043847
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.1310475128
Short name T1009
Test name
Test status
Simulation time 1431573489 ps
CPU time 10.05 seconds
Started Aug 21 08:34:43 AM UTC 24
Finished Aug 21 08:34:55 AM UTC 24
Peak memory 226968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1310475128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_timeout.1310475128
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.3608317776
Short name T1068
Test name
Test status
Simulation time 946364447 ps
CPU time 13.07 seconds
Started Aug 21 08:34:55 AM UTC 24
Finished Aug 21 08:35:10 AM UTC 24
Peak memory 232912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3608317776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.3608317776
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_alert_test.76487924
Short name T334
Test name
Test status
Simulation time 26988411 ps
CPU time 0.96 seconds
Started Aug 21 08:22:51 AM UTC 24
Finished Aug 21 08:22:53 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=76487924 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.76487924
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.4049115485
Short name T30
Test name
Test status
Simulation time 128125602 ps
CPU time 2.03 seconds
Started Aug 21 08:22:42 AM UTC 24
Finished Aug 21 08:22:46 AM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4049115485 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.4049115485
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.911986325
Short name T324
Test name
Test status
Simulation time 4190322183 ps
CPU time 5.99 seconds
Started Aug 21 08:22:40 AM UTC 24
Finished Aug 21 08:22:48 AM UTC 24
Peak memory 268508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=911986325 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty.911986325
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.358361356
Short name T34
Test name
Test status
Simulation time 11275059473 ps
CPU time 67.38 seconds
Started Aug 21 08:22:41 AM UTC 24
Finished Aug 21 08:23:50 AM UTC 24
Peak memory 533000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358361356 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.358361356
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.964757130
Short name T129
Test name
Test status
Simulation time 2255914240 ps
CPU time 55.79 seconds
Started Aug 21 08:22:39 AM UTC 24
Finished Aug 21 08:23:37 AM UTC 24
Peak memory 788980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=964757130 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.964757130
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.2151087675
Short name T167
Test name
Test status
Simulation time 502561877 ps
CPU time 1.4 seconds
Started Aug 21 08:22:40 AM UTC 24
Finished Aug 21 08:22:43 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2151087675 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt.2151087675
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.960540031
Short name T175
Test name
Test status
Simulation time 330957695 ps
CPU time 5.11 seconds
Started Aug 21 08:22:41 AM UTC 24
Finished Aug 21 08:22:47 AM UTC 24
Peak memory 252052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=960540031 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.960540031
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_perf.955326863
Short name T306
Test name
Test status
Simulation time 1992470140 ps
CPU time 4.82 seconds
Started Aug 21 08:22:41 AM UTC 24
Finished Aug 21 08:22:47 AM UTC 24
Peak memory 252180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=955326863 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.955326863
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.2183714091
Short name T171
Test name
Test status
Simulation time 216987332 ps
CPU time 2.82 seconds
Started Aug 21 08:22:41 AM UTC 24
Finished Aug 21 08:22:45 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2183714091 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.2183714091
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.2608345172
Short name T47
Test name
Test status
Simulation time 2606208258 ps
CPU time 17.36 seconds
Started Aug 21 08:22:37 AM UTC 24
Finished Aug 21 08:22:56 AM UTC 24
Peak memory 331932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2608345172 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2608345172
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.3622017592
Short name T290
Test name
Test status
Simulation time 1143028896 ps
CPU time 9.6 seconds
Started Aug 21 08:22:41 AM UTC 24
Finished Aug 21 08:22:52 AM UTC 24
Peak memory 226844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3622017592 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3622017592
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.1450222416
Short name T219
Test name
Test status
Simulation time 448780202 ps
CPU time 1.05 seconds
Started Aug 21 08:22:51 AM UTC 24
Finished Aug 21 08:22:53 AM UTC 24
Peak memory 246624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1450222416 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1450222416
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.3317717376
Short name T327
Test name
Test status
Simulation time 1186771742 ps
CPU time 3.58 seconds
Started Aug 21 08:22:45 AM UTC 24
Finished Aug 21 08:22:50 AM UTC 24
Peak memory 233304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3317717376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3317717376
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.2995815000
Short name T325
Test name
Test status
Simulation time 636874313 ps
CPU time 1.83 seconds
Started Aug 21 08:22:45 AM UTC 24
Finished Aug 21 08:22:48 AM UTC 24
Peak memory 226552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2995815000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_acq.2995815000
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.1278460151
Short name T326
Test name
Test status
Simulation time 185046198 ps
CPU time 2.11 seconds
Started Aug 21 08:22:45 AM UTC 24
Finished Aug 21 08:22:49 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1278460151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_fifo_reset_tx.1278460151
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.2309781204
Short name T332
Test name
Test status
Simulation time 5494956566 ps
CPU time 2.66 seconds
Started Aug 21 08:22:48 AM UTC 24
Finished Aug 21 08:22:52 AM UTC 24
Peak memory 216976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2309781204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.2309781204
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.1914074292
Short name T328
Test name
Test status
Simulation time 458864297 ps
CPU time 1.93 seconds
Started Aug 21 08:22:48 AM UTC 24
Finished Aug 21 08:22:51 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1914074292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.1914074292
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_hrst.4023903681
Short name T180
Test name
Test status
Simulation time 943859786 ps
CPU time 2.52 seconds
Started Aug 21 08:22:46 AM UTC 24
Finished Aug 21 08:22:50 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4023903681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 3.i2c_target_hrst.4023903681
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.2560093837
Short name T333
Test name
Test status
Simulation time 1294300600 ps
CPU time 7.93 seconds
Started Aug 21 08:22:42 AM UTC 24
Finished Aug 21 08:22:52 AM UTC 24
Peak memory 233768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2560093837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_intr_smoke.2560093837
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.2955343537
Short name T176
Test name
Test status
Simulation time 11226310788 ps
CPU time 7.58 seconds
Started Aug 21 08:22:42 AM UTC 24
Finished Aug 21 08:22:52 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2955343537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2955343537
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.3537649834
Short name T58
Test name
Test status
Simulation time 562647230 ps
CPU time 3.3 seconds
Started Aug 21 08:22:50 AM UTC 24
Finished Aug 21 08:22:55 AM UTC 24
Peak memory 226704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3537649834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 3.i2c_target_nack_acqfull.3537649834
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.1709230641
Short name T184
Test name
Test status
Simulation time 464870878 ps
CPU time 2.45 seconds
Started Aug 21 08:22:50 AM UTC 24
Finished Aug 21 08:22:54 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1709230641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_nack_acqfull_addr.1709230641
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_nack_txstretch.2404413677
Short name T65
Test name
Test status
Simulation time 444884529 ps
CPU time 2.46 seconds
Started Aug 21 08:22:50 AM UTC 24
Finished Aug 21 08:22:54 AM UTC 24
Peak memory 233500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2404413677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_nack_txstretch.2404413677
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_perf.96487888
Short name T329
Test name
Test status
Simulation time 436121647 ps
CPU time 5.03 seconds
Started Aug 21 08:22:45 AM UTC 24
Finished Aug 21 08:22:52 AM UTC 24
Peak memory 226712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=96487888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 3.i2c_target_perf.96487888
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.553763891
Short name T336
Test name
Test status
Simulation time 1943903378 ps
CPU time 3.01 seconds
Started Aug 21 08:22:49 AM UTC 24
Finished Aug 21 08:22:54 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=553763891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 3.i2c_target_smbus_maxlen.553763891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.2754680147
Short name T345
Test name
Test status
Simulation time 761552685 ps
CPU time 25.05 seconds
Started Aug 21 08:22:42 AM UTC 24
Finished Aug 21 08:23:10 AM UTC 24
Peak memory 229072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2754680147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targe
t_smoke.2754680147
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.1124982109
Short name T723
Test name
Test status
Simulation time 36648610628 ps
CPU time 392.19 seconds
Started Aug 21 08:22:45 AM UTC 24
Finished Aug 21 08:29:22 AM UTC 24
Peak memory 4374956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1124982109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 3.i2c_target_stress_all.1124982109
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.645584173
Short name T286
Test name
Test status
Simulation time 3472967301 ps
CPU time 36.26 seconds
Started Aug 21 08:22:42 AM UTC 24
Finished Aug 21 08:23:21 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=645584173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stress_rd.645584173
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.3086530885
Short name T339
Test name
Test status
Simulation time 12997645499 ps
CPU time 11.71 seconds
Started Aug 21 08:22:42 AM UTC 24
Finished Aug 21 08:22:56 AM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3086530885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stress_wr.3086530885
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.3070933866
Short name T323
Test name
Test status
Simulation time 903863468 ps
CPU time 3.28 seconds
Started Aug 21 08:22:42 AM UTC 24
Finished Aug 21 08:22:48 AM UTC 24
Peak memory 226556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3070933866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_stretch.3070933866
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.2245205666
Short name T330
Test name
Test status
Simulation time 5235503015 ps
CPU time 7.5 seconds
Started Aug 21 08:22:42 AM UTC 24
Finished Aug 21 08:22:52 AM UTC 24
Peak memory 233704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2245205666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_timeout.2245205666
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.3842016663
Short name T335
Test name
Test status
Simulation time 208817012 ps
CPU time 2.98 seconds
Started Aug 21 08:22:49 AM UTC 24
Finished Aug 21 08:22:54 AM UTC 24
Peak memory 227032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3842016663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.3842016663
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_alert_test.1394364094
Short name T1092
Test name
Test status
Simulation time 38143921 ps
CPU time 1 seconds
Started Aug 21 08:35:32 AM UTC 24
Finished Aug 21 08:35:35 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1394364094 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1394364094
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_error_intr.2340718000
Short name T1070
Test name
Test status
Simulation time 416077321 ps
CPU time 4.49 seconds
Started Aug 21 08:35:07 AM UTC 24
Finished Aug 21 08:35:12 AM UTC 24
Peak memory 229000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2340718000 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2340718000
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.2998314957
Short name T1081
Test name
Test status
Simulation time 2032628346 ps
CPU time 23.91 seconds
Started Aug 21 08:35:03 AM UTC 24
Finished Aug 21 08:35:28 AM UTC 24
Peak memory 299028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2998314957 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty.2998314957
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.3909414703
Short name T1150
Test name
Test status
Simulation time 22485795379 ps
CPU time 100.65 seconds
Started Aug 21 08:35:03 AM UTC 24
Finished Aug 21 08:36:46 AM UTC 24
Peak memory 598296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3909414703 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.3909414703
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.3134866262
Short name T1086
Test name
Test status
Simulation time 4650177406 ps
CPU time 63.06 seconds
Started Aug 21 08:35:02 AM UTC 24
Finished Aug 21 08:36:07 AM UTC 24
Peak memory 739416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3134866262 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3134866262
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.493689178
Short name T1065
Test name
Test status
Simulation time 360810078 ps
CPU time 1.5 seconds
Started Aug 21 08:35:03 AM UTC 24
Finished Aug 21 08:35:06 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=493689178 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fmt.493689178
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.880912153
Short name T1071
Test name
Test status
Simulation time 127169135 ps
CPU time 9.23 seconds
Started Aug 21 08:35:03 AM UTC 24
Finished Aug 21 08:35:14 AM UTC 24
Peak memory 237656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=880912153 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.880912153
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.3843311718
Short name T1137
Test name
Test status
Simulation time 10686370091 ps
CPU time 89.81 seconds
Started Aug 21 08:35:02 AM UTC 24
Finished Aug 21 08:36:34 AM UTC 24
Peak memory 1120580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3843311718 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3843311718
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.155704350
Short name T281
Test name
Test status
Simulation time 5759647087 ps
CPU time 14.25 seconds
Started Aug 21 08:35:28 AM UTC 24
Finished Aug 21 08:35:43 AM UTC 24
Peak memory 216968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=155704350 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.155704350
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_override.3227796732
Short name T162
Test name
Test status
Simulation time 41470744 ps
CPU time 0.95 seconds
Started Aug 21 08:35:02 AM UTC 24
Finished Aug 21 08:35:04 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3227796732 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3227796732
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_perf.3530131270
Short name T1698
Test name
Test status
Simulation time 24626522383 ps
CPU time 991.52 seconds
Started Aug 21 08:35:04 AM UTC 24
Finished Aug 21 08:51:48 AM UTC 24
Peak memory 260420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3530131270 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3530131270
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.2060438587
Short name T1067
Test name
Test status
Simulation time 42657689 ps
CPU time 2.16 seconds
Started Aug 21 08:35:04 AM UTC 24
Finished Aug 21 08:35:08 AM UTC 24
Peak memory 239168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2060438587 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.2060438587
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.1676692714
Short name T1085
Test name
Test status
Simulation time 1391263633 ps
CPU time 28.37 seconds
Started Aug 21 08:35:02 AM UTC 24
Finished Aug 21 08:35:32 AM UTC 24
Peak memory 278688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1676692714 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1676692714
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.1988576230
Short name T1078
Test name
Test status
Simulation time 920038763 ps
CPU time 21.32 seconds
Started Aug 21 08:35:05 AM UTC 24
Finished Aug 21 08:35:27 AM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1988576230 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1988576230
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.3145334319
Short name T1087
Test name
Test status
Simulation time 3288536501 ps
CPU time 5.17 seconds
Started Aug 21 08:35:26 AM UTC 24
Finished Aug 21 08:35:32 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3145334319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3145334319
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.2314391073
Short name T1075
Test name
Test status
Simulation time 449269464 ps
CPU time 1.59 seconds
Started Aug 21 08:35:18 AM UTC 24
Finished Aug 21 08:35:22 AM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2314391073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_acq.2314391073
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.504380245
Short name T1077
Test name
Test status
Simulation time 475704104 ps
CPU time 2.32 seconds
Started Aug 21 08:35:22 AM UTC 24
Finished Aug 21 08:35:26 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=504380245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_target_fifo_reset_tx.504380245
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.537215165
Short name T1090
Test name
Test status
Simulation time 4872141571 ps
CPU time 3.48 seconds
Started Aug 21 08:35:29 AM UTC 24
Finished Aug 21 08:35:33 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=537215165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.537215165
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.1327285769
Short name T1088
Test name
Test status
Simulation time 156257132 ps
CPU time 2.54 seconds
Started Aug 21 08:35:29 AM UTC 24
Finished Aug 21 08:35:33 AM UTC 24
Peak memory 216484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1327285769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.1327285769
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_hrst.3019606582
Short name T1084
Test name
Test status
Simulation time 225358414 ps
CPU time 2.16 seconds
Started Aug 21 08:35:27 AM UTC 24
Finished Aug 21 08:35:30 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3019606582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.i2c_target_hrst.3019606582
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.1486344520
Short name T1074
Test name
Test status
Simulation time 2278478074 ps
CPU time 6.96 seconds
Started Aug 21 08:35:13 AM UTC 24
Finished Aug 21 08:35:21 AM UTC 24
Peak memory 228992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1486344520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.1486344520
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.3932348376
Short name T1128
Test name
Test status
Simulation time 18311690524 ps
CPU time 61.56 seconds
Started Aug 21 08:35:14 AM UTC 24
Finished Aug 21 08:36:17 AM UTC 24
Peak memory 794796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3932348376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3932348376
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.1245926121
Short name T1097
Test name
Test status
Simulation time 2014236284 ps
CPU time 4.26 seconds
Started Aug 21 08:35:31 AM UTC 24
Finished Aug 21 08:35:37 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1245926121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_target_nack_acqfull.1245926121
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.2322794293
Short name T1096
Test name
Test status
Simulation time 571173848 ps
CPU time 3.95 seconds
Started Aug 21 08:35:31 AM UTC 24
Finished Aug 21 08:35:36 AM UTC 24
Peak memory 216636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2322794293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_nack_acqfull_addr.2322794293
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_nack_txstretch.1549714221
Short name T1095
Test name
Test status
Simulation time 297394356 ps
CPU time 2.32 seconds
Started Aug 21 08:35:32 AM UTC 24
Finished Aug 21 08:35:36 AM UTC 24
Peak memory 233500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1549714221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_nack_txstretch.1549714221
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_perf.3986056015
Short name T1083
Test name
Test status
Simulation time 577895510 ps
CPU time 6.11 seconds
Started Aug 21 08:35:23 AM UTC 24
Finished Aug 21 08:35:30 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3986056015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.i2c_target_perf.3986056015
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.1852627079
Short name T1094
Test name
Test status
Simulation time 411185266 ps
CPU time 3.86 seconds
Started Aug 21 08:35:30 AM UTC 24
Finished Aug 21 08:35:35 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1852627079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_target_smbus_maxlen.1852627079
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.3787230396
Short name T1076
Test name
Test status
Simulation time 956083595 ps
CPU time 14.63 seconds
Started Aug 21 08:35:07 AM UTC 24
Finished Aug 21 08:35:23 AM UTC 24
Peak memory 228880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3787230396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_targ
et_smoke.3787230396
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.1472379035
Short name T1091
Test name
Test status
Simulation time 541214304 ps
CPU time 23.2 seconds
Started Aug 21 08:35:10 AM UTC 24
Finished Aug 21 08:35:34 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1472379035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stress_rd.1472379035
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.1070699568
Short name T1292
Test name
Test status
Simulation time 66303802314 ps
CPU time 230.91 seconds
Started Aug 21 08:35:09 AM UTC 24
Finished Aug 21 08:39:03 AM UTC 24
Peak memory 2945188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1070699568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stress_wr.1070699568
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.2096713065
Short name T1101
Test name
Test status
Simulation time 2394338316 ps
CPU time 31.79 seconds
Started Aug 21 08:35:12 AM UTC 24
Finished Aug 21 08:35:45 AM UTC 24
Peak memory 758040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2096713065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_stretch.2096713065
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.2729834623
Short name T1080
Test name
Test status
Simulation time 1296844897 ps
CPU time 10.84 seconds
Started Aug 21 08:35:15 AM UTC 24
Finished Aug 21 08:35:28 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2729834623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_timeout.2729834623
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.4125054138
Short name T1093
Test name
Test status
Simulation time 126212615 ps
CPU time 3.88 seconds
Started Aug 21 08:35:30 AM UTC 24
Finished Aug 21 08:35:35 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4125054138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.4125054138
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_alert_test.1990254470
Short name T1120
Test name
Test status
Simulation time 14814477 ps
CPU time 0.93 seconds
Started Aug 21 08:36:07 AM UTC 24
Finished Aug 21 08:36:09 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1990254470 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1990254470
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_error_intr.454239136
Short name T1102
Test name
Test status
Simulation time 132753094 ps
CPU time 4.89 seconds
Started Aug 21 08:35:40 AM UTC 24
Finished Aug 21 08:35:46 AM UTC 24
Peak memory 227096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=454239136 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.454239136
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.2137351185
Short name T1111
Test name
Test status
Simulation time 7220701203 ps
CPU time 20.04 seconds
Started Aug 21 08:35:36 AM UTC 24
Finished Aug 21 08:35:57 AM UTC 24
Peak memory 301524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2137351185 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty.2137351185
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.312474688
Short name T1305
Test name
Test status
Simulation time 19897008837 ps
CPU time 217.08 seconds
Started Aug 21 08:35:37 AM UTC 24
Finished Aug 21 08:39:18 AM UTC 24
Peak memory 819484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=312474688 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.312474688
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.1004463668
Short name T1161
Test name
Test status
Simulation time 27319281525 ps
CPU time 78.07 seconds
Started Aug 21 08:35:36 AM UTC 24
Finished Aug 21 08:36:56 AM UTC 24
Peak memory 913884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1004463668 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1004463668
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.1900461097
Short name T270
Test name
Test status
Simulation time 151449971 ps
CPU time 1.94 seconds
Started Aug 21 08:35:36 AM UTC 24
Finished Aug 21 08:35:39 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1900461097 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt.1900461097
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.3968807270
Short name T1100
Test name
Test status
Simulation time 528958103 ps
CPU time 5.52 seconds
Started Aug 21 08:35:36 AM UTC 24
Finished Aug 21 08:35:43 AM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3968807270 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.3968807270
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.284693837
Short name T1209
Test name
Test status
Simulation time 5050287212 ps
CPU time 127.87 seconds
Started Aug 21 08:35:35 AM UTC 24
Finished Aug 21 08:37:45 AM UTC 24
Peak memory 1325344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=284693837 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.284693837
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.2219564795
Short name T1141
Test name
Test status
Simulation time 3202594148 ps
CPU time 36.11 seconds
Started Aug 21 08:36:00 AM UTC 24
Finished Aug 21 08:36:37 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2219564795 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2219564795
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_override.3763830300
Short name T1098
Test name
Test status
Simulation time 84938193 ps
CPU time 0.88 seconds
Started Aug 21 08:35:35 AM UTC 24
Finished Aug 21 08:35:37 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3763830300 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.3763830300
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_perf.1318823332
Short name T1145
Test name
Test status
Simulation time 53986866940 ps
CPU time 112.91 seconds
Started Aug 21 08:35:37 AM UTC 24
Finished Aug 21 08:37:33 AM UTC 24
Peak memory 248032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1318823332 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1318823332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.224857306
Short name T1099
Test name
Test status
Simulation time 141875162 ps
CPU time 1.56 seconds
Started Aug 21 08:35:37 AM UTC 24
Finished Aug 21 08:35:40 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=224857306 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.224857306
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.477100061
Short name T1133
Test name
Test status
Simulation time 3595861025 ps
CPU time 47.84 seconds
Started Aug 21 08:35:33 AM UTC 24
Finished Aug 21 08:36:23 AM UTC 24
Peak memory 282912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=477100061 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.477100061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_stress_all.834701964
Short name T140
Test name
Test status
Simulation time 164580402315 ps
CPU time 547.34 seconds
Started Aug 21 08:35:40 AM UTC 24
Finished Aug 21 08:44:54 AM UTC 24
Peak memory 2658608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=834701964 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.834701964
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.1467750372
Short name T1104
Test name
Test status
Simulation time 435315303 ps
CPU time 10 seconds
Started Aug 21 08:35:38 AM UTC 24
Finished Aug 21 08:35:50 AM UTC 24
Peak memory 226968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1467750372 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1467750372
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.462246083
Short name T1117
Test name
Test status
Simulation time 8030428541 ps
CPU time 6.41 seconds
Started Aug 21 08:35:57 AM UTC 24
Finished Aug 21 08:36:05 AM UTC 24
Peak memory 226960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=462246083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_bad_addr.462246083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.2438484640
Short name T1110
Test name
Test status
Simulation time 569743059 ps
CPU time 1.37 seconds
Started Aug 21 08:35:54 AM UTC 24
Finished Aug 21 08:35:56 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2438484640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_acq.2438484640
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.2997735543
Short name T1112
Test name
Test status
Simulation time 280113475 ps
CPU time 1.4 seconds
Started Aug 21 08:35:56 AM UTC 24
Finished Aug 21 08:35:59 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2997735543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_fifo_reset_tx.2997735543
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.1618230501
Short name T1119
Test name
Test status
Simulation time 1845691045 ps
CPU time 4.74 seconds
Started Aug 21 08:36:01 AM UTC 24
Finished Aug 21 08:36:06 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1618230501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.1618230501
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.985512525
Short name T1116
Test name
Test status
Simulation time 234535063 ps
CPU time 1.67 seconds
Started Aug 21 08:36:01 AM UTC 24
Finished Aug 21 08:36:03 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=985512525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.985512525
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.1529743992
Short name T1108
Test name
Test status
Simulation time 1048969283 ps
CPU time 8.57 seconds
Started Aug 21 08:35:47 AM UTC 24
Finished Aug 21 08:35:56 AM UTC 24
Peak memory 233580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1529743992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.1529743992
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.939939982
Short name T1114
Test name
Test status
Simulation time 7803275961 ps
CPU time 9.41 seconds
Started Aug 21 08:35:49 AM UTC 24
Finished Aug 21 08:35:59 AM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=939939982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.939939982
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.1406474865
Short name T1121
Test name
Test status
Simulation time 557871346 ps
CPU time 3.59 seconds
Started Aug 21 08:36:05 AM UTC 24
Finished Aug 21 08:36:09 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1406474865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 31.i2c_target_nack_acqfull.1406474865
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.3646363691
Short name T1124
Test name
Test status
Simulation time 4875812616 ps
CPU time 4.48 seconds
Started Aug 21 08:36:06 AM UTC 24
Finished Aug 21 08:36:12 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3646363691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_nack_acqfull_addr.3646363691
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_perf.3754265792
Short name T1118
Test name
Test status
Simulation time 1385572393 ps
CPU time 7.97 seconds
Started Aug 21 08:35:56 AM UTC 24
Finished Aug 21 08:36:05 AM UTC 24
Peak memory 231184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3754265792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 31.i2c_target_perf.3754265792
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.1025015854
Short name T1053
Test name
Test status
Simulation time 464084201 ps
CPU time 2.91 seconds
Started Aug 21 08:36:04 AM UTC 24
Finished Aug 21 08:36:08 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1025015854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 31.i2c_target_smbus_maxlen.1025015854
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.1515043083
Short name T1127
Test name
Test status
Simulation time 1963596382 ps
CPU time 29.74 seconds
Started Aug 21 08:35:43 AM UTC 24
Finished Aug 21 08:36:14 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1515043083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_targ
et_smoke.1515043083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.3621283594
Short name T1535
Test name
Test status
Simulation time 28446302646 ps
CPU time 528.71 seconds
Started Aug 21 08:35:57 AM UTC 24
Finished Aug 21 08:44:52 AM UTC 24
Peak memory 5521680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3621283594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 31.i2c_target_stress_all.3621283594
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.3103649779
Short name T1125
Test name
Test status
Simulation time 3997711896 ps
CPU time 25.85 seconds
Started Aug 21 08:35:45 AM UTC 24
Finished Aug 21 08:36:12 AM UTC 24
Peak memory 226948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3103649779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stress_rd.3103649779
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.1804016275
Short name T1254
Test name
Test status
Simulation time 52663198987 ps
CPU time 154.01 seconds
Started Aug 21 08:35:45 AM UTC 24
Finished Aug 21 08:38:21 AM UTC 24
Peak memory 2161068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1804016275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stress_wr.1804016275
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.1112474318
Short name T1109
Test name
Test status
Simulation time 2258423371 ps
CPU time 9.7 seconds
Started Aug 21 08:35:46 AM UTC 24
Finished Aug 21 08:35:56 AM UTC 24
Peak memory 297184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1112474318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_stretch.1112474318
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.3379667227
Short name T1115
Test name
Test status
Simulation time 1476940538 ps
CPU time 9.39 seconds
Started Aug 21 08:35:51 AM UTC 24
Finished Aug 21 08:36:01 AM UTC 24
Peak memory 233512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3379667227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_timeout.3379667227
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.2505344400
Short name T1123
Test name
Test status
Simulation time 505876770 ps
CPU time 7.2 seconds
Started Aug 21 08:36:02 AM UTC 24
Finished Aug 21 08:36:10 AM UTC 24
Peak memory 227028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2505344400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.2505344400
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_alert_test.2634961716
Short name T1152
Test name
Test status
Simulation time 44766207 ps
CPU time 0.87 seconds
Started Aug 21 08:36:46 AM UTC 24
Finished Aug 21 08:36:48 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2634961716 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2634961716
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.1485252262
Short name T1130
Test name
Test status
Simulation time 838204258 ps
CPU time 2.11 seconds
Started Aug 21 08:36:15 AM UTC 24
Finished Aug 21 08:36:18 AM UTC 24
Peak memory 233572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1485252262 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1485252262
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.2854001517
Short name T1132
Test name
Test status
Simulation time 2145339766 ps
CPU time 11.06 seconds
Started Aug 21 08:36:11 AM UTC 24
Finished Aug 21 08:36:23 AM UTC 24
Peak memory 328036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854001517 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty.2854001517
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.3756118938
Short name T1240
Test name
Test status
Simulation time 2258296069 ps
CPU time 116.88 seconds
Started Aug 21 08:36:11 AM UTC 24
Finished Aug 21 08:38:10 AM UTC 24
Peak memory 549132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3756118938 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3756118938
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.1114693773
Short name T1167
Test name
Test status
Simulation time 15153530920 ps
CPU time 51.42 seconds
Started Aug 21 08:36:10 AM UTC 24
Finished Aug 21 08:37:03 AM UTC 24
Peak memory 721116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1114693773 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1114693773
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.345156544
Short name T1126
Test name
Test status
Simulation time 250132263 ps
CPU time 1.57 seconds
Started Aug 21 08:36:10 AM UTC 24
Finished Aug 21 08:36:13 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=345156544 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt.345156544
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.2900724469
Short name T1131
Test name
Test status
Simulation time 912516074 ps
CPU time 9.04 seconds
Started Aug 21 08:36:11 AM UTC 24
Finished Aug 21 08:36:21 AM UTC 24
Peak memory 262300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2900724469 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.2900724469
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.2699909570
Short name T1173
Test name
Test status
Simulation time 3069181903 ps
CPU time 66.07 seconds
Started Aug 21 08:36:08 AM UTC 24
Finished Aug 21 08:37:16 AM UTC 24
Peak memory 923792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2699909570 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2699909570
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.3269375340
Short name T1158
Test name
Test status
Simulation time 1571211845 ps
CPU time 11.91 seconds
Started Aug 21 08:36:38 AM UTC 24
Finished Aug 21 08:36:51 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3269375340 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.3269375340
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_override.4187726713
Short name T1089
Test name
Test status
Simulation time 16638262 ps
CPU time 0.95 seconds
Started Aug 21 08:36:07 AM UTC 24
Finished Aug 21 08:36:09 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4187726713 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.4187726713
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_perf.627763659
Short name T1184
Test name
Test status
Simulation time 2727035712 ps
CPU time 68.84 seconds
Started Aug 21 08:36:13 AM UTC 24
Finished Aug 21 08:37:24 AM UTC 24
Peak memory 250256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=627763659 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.627763659
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.3210624867
Short name T1129
Test name
Test status
Simulation time 201323385 ps
CPU time 3.74 seconds
Started Aug 21 08:36:13 AM UTC 24
Finished Aug 21 08:36:18 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3210624867 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.3210624867
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.1589064030
Short name T1192
Test name
Test status
Simulation time 7180547554 ps
CPU time 77.57 seconds
Started Aug 21 08:36:07 AM UTC 24
Finished Aug 21 08:37:27 AM UTC 24
Peak memory 309456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1589064030 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1589064030
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_stress_all.3961974283
Short name T1357
Test name
Test status
Simulation time 8254243962 ps
CPU time 235.09 seconds
Started Aug 21 08:36:18 AM UTC 24
Finished Aug 21 08:40:16 AM UTC 24
Peak memory 1446436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3961974283 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.3961974283
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.1931620097
Short name T1135
Test name
Test status
Simulation time 1612163466 ps
CPU time 12.16 seconds
Started Aug 21 08:36:14 AM UTC 24
Finished Aug 21 08:36:27 AM UTC 24
Peak memory 233496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1931620097 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1931620097
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.1268131086
Short name T1149
Test name
Test status
Simulation time 3787988608 ps
CPU time 7.68 seconds
Started Aug 21 08:36:37 AM UTC 24
Finished Aug 21 08:36:46 AM UTC 24
Peak memory 226964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1268131086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1268131086
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.1735812647
Short name T314
Test name
Test status
Simulation time 329090238 ps
CPU time 3.36 seconds
Started Aug 21 08:36:32 AM UTC 24
Finished Aug 21 08:36:36 AM UTC 24
Peak memory 220612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1735812647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_fifo_reset_acq.1735812647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.1237452241
Short name T1140
Test name
Test status
Simulation time 674402915 ps
CPU time 2.41 seconds
Started Aug 21 08:36:34 AM UTC 24
Finished Aug 21 08:36:37 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1237452241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_fifo_reset_tx.1237452241
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.512467186
Short name T1148
Test name
Test status
Simulation time 1154729573 ps
CPU time 4.68 seconds
Started Aug 21 08:36:39 AM UTC 24
Finished Aug 21 08:36:45 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=512467186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.512467186
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.1547608325
Short name T1146
Test name
Test status
Simulation time 114001400 ps
CPU time 1.87 seconds
Started Aug 21 08:36:39 AM UTC 24
Finished Aug 21 08:36:42 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1547608325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.1547608325
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.2661355782
Short name T1136
Test name
Test status
Simulation time 3644393054 ps
CPU time 8.57 seconds
Started Aug 21 08:36:23 AM UTC 24
Finished Aug 21 08:36:33 AM UTC 24
Peak memory 233720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2661355782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.2661355782
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.2340328553
Short name T1196
Test name
Test status
Simulation time 10766669800 ps
CPU time 67.84 seconds
Started Aug 21 08:36:25 AM UTC 24
Finished Aug 21 08:37:34 AM UTC 24
Peak memory 1366440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2340328553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2340328553
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.3186743382
Short name T1153
Test name
Test status
Simulation time 485155886 ps
CPU time 4.55 seconds
Started Aug 21 08:36:43 AM UTC 24
Finished Aug 21 08:36:48 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3186743382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 32.i2c_target_nack_acqfull.3186743382
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.1492260452
Short name T1157
Test name
Test status
Simulation time 2245064897 ps
CPU time 5.28 seconds
Started Aug 21 08:36:44 AM UTC 24
Finished Aug 21 08:36:50 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1492260452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_nack_acqfull_addr.1492260452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_nack_txstretch.3823341711
Short name T1155
Test name
Test status
Simulation time 265157570 ps
CPU time 2.25 seconds
Started Aug 21 08:36:46 AM UTC 24
Finished Aug 21 08:36:49 AM UTC 24
Peak memory 233556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3823341711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_nack_txstretch.3823341711
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_perf.2318530197
Short name T1147
Test name
Test status
Simulation time 892393523 ps
CPU time 6.79 seconds
Started Aug 21 08:36:35 AM UTC 24
Finished Aug 21 08:36:43 AM UTC 24
Peak memory 230964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2318530197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 32.i2c_target_perf.2318530197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.2290208931
Short name T1151
Test name
Test status
Simulation time 947316413 ps
CPU time 3.87 seconds
Started Aug 21 08:36:43 AM UTC 24
Finished Aug 21 08:36:48 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2290208931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 32.i2c_target_smbus_maxlen.2290208931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.3653605212
Short name T1138
Test name
Test status
Simulation time 3272113266 ps
CPU time 15.4 seconds
Started Aug 21 08:36:18 AM UTC 24
Finished Aug 21 08:36:35 AM UTC 24
Peak memory 233756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3653605212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_targ
et_smoke.3653605212
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.1171140170
Short name T1177
Test name
Test status
Simulation time 11044086040 ps
CPU time 42.74 seconds
Started Aug 21 08:36:36 AM UTC 24
Finished Aug 21 08:37:20 AM UTC 24
Peak memory 250132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1171140170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 32.i2c_target_stress_all.1171140170
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.2055156273
Short name T1189
Test name
Test status
Simulation time 1396701805 ps
CPU time 62.82 seconds
Started Aug 21 08:36:21 AM UTC 24
Finished Aug 21 08:37:26 AM UTC 24
Peak memory 226844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2055156273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stress_rd.2055156273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.267061310
Short name T1517
Test name
Test status
Simulation time 41971491490 ps
CPU time 471.71 seconds
Started Aug 21 08:36:19 AM UTC 24
Finished Aug 21 08:44:16 AM UTC 24
Peak memory 5578908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=267061310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stress_wr.267061310
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_stretch.2563853082
Short name T1142
Test name
Test status
Simulation time 1725684897 ps
CPU time 15.26 seconds
Started Aug 21 08:36:22 AM UTC 24
Finished Aug 21 08:36:39 AM UTC 24
Peak memory 430116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2563853082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_stretch.2563853082
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.433327608
Short name T1139
Test name
Test status
Simulation time 4553431901 ps
CPU time 10.11 seconds
Started Aug 21 08:36:25 AM UTC 24
Finished Aug 21 08:36:36 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=433327608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_timeout.433327608
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/32.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_alert_test.4202768570
Short name T1183
Test name
Test status
Simulation time 26893313 ps
CPU time 0.86 seconds
Started Aug 21 08:37:22 AM UTC 24
Finished Aug 21 08:37:23 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4202768570 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.4202768570
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.4255277273
Short name T1162
Test name
Test status
Simulation time 648556810 ps
CPU time 4.14 seconds
Started Aug 21 08:36:53 AM UTC 24
Finished Aug 21 08:36:58 AM UTC 24
Peak memory 230996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4255277273 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.4255277273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.2761237749
Short name T1163
Test name
Test status
Simulation time 909349558 ps
CPU time 11.49 seconds
Started Aug 21 08:36:49 AM UTC 24
Finished Aug 21 08:37:02 AM UTC 24
Peak memory 268184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2761237749 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empty.2761237749
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.995473264
Short name T1406
Test name
Test status
Simulation time 15983165902 ps
CPU time 255.09 seconds
Started Aug 21 08:36:50 AM UTC 24
Finished Aug 21 08:41:09 AM UTC 24
Peak memory 1022164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=995473264 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.995473264
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.2327233132
Short name T1258
Test name
Test status
Simulation time 6083885922 ps
CPU time 95.42 seconds
Started Aug 21 08:36:48 AM UTC 24
Finished Aug 21 08:38:26 AM UTC 24
Peak memory 903440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2327233132 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2327233132
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.825139525
Short name T1159
Test name
Test status
Simulation time 473721759 ps
CPU time 1.47 seconds
Started Aug 21 08:36:49 AM UTC 24
Finished Aug 21 08:36:52 AM UTC 24
Peak memory 216352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=825139525 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt.825139525
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.2478260470
Short name T1164
Test name
Test status
Simulation time 618615557 ps
CPU time 10.45 seconds
Started Aug 21 08:36:50 AM UTC 24
Finished Aug 21 08:37:02 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2478260470 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.2478260470
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.1052834298
Short name T1309
Test name
Test status
Simulation time 21833230293 ps
CPU time 150.52 seconds
Started Aug 21 08:36:48 AM UTC 24
Finished Aug 21 08:39:21 AM UTC 24
Peak memory 1607828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1052834298 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1052834298
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_override.2182497266
Short name T1156
Test name
Test status
Simulation time 15161720 ps
CPU time 1.04 seconds
Started Aug 21 08:36:47 AM UTC 24
Finished Aug 21 08:36:49 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2182497266 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2182497266
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_perf.3309177161
Short name T1512
Test name
Test status
Simulation time 7601663513 ps
CPU time 423.61 seconds
Started Aug 21 08:36:51 AM UTC 24
Finished Aug 21 08:44:00 AM UTC 24
Peak memory 1507852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3309177161 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3309177161
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.288365365
Short name T1166
Test name
Test status
Simulation time 351789374 ps
CPU time 9.51 seconds
Started Aug 21 08:36:53 AM UTC 24
Finished Aug 21 08:37:03 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=288365365 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.288365365
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.1052318029
Short name T1170
Test name
Test status
Simulation time 2931421298 ps
CPU time 26.05 seconds
Started Aug 21 08:36:47 AM UTC 24
Finished Aug 21 08:37:14 AM UTC 24
Peak memory 329896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1052318029 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.1052318029
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_stress_all.3422736790
Short name T297
Test name
Test status
Simulation time 41701965792 ps
CPU time 214.12 seconds
Started Aug 21 08:36:57 AM UTC 24
Finished Aug 21 08:40:34 AM UTC 24
Peak memory 1102116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3422736790 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.3422736790
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.2879706619
Short name T1165
Test name
Test status
Simulation time 1617514762 ps
CPU time 9.41 seconds
Started Aug 21 08:36:53 AM UTC 24
Finished Aug 21 08:37:03 AM UTC 24
Peak memory 227020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2879706619 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2879706619
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.3262532095
Short name T1180
Test name
Test status
Simulation time 1043780876 ps
CPU time 5.31 seconds
Started Aug 21 08:37:15 AM UTC 24
Finished Aug 21 08:37:21 AM UTC 24
Peak memory 218576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3262532095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3262532095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.1444962987
Short name T1169
Test name
Test status
Simulation time 144113606 ps
CPU time 1.63 seconds
Started Aug 21 08:37:09 AM UTC 24
Finished Aug 21 08:37:13 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1444962987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_acq.1444962987
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.2735625173
Short name T1171
Test name
Test status
Simulation time 375632155 ps
CPU time 1.28 seconds
Started Aug 21 08:37:12 AM UTC 24
Finished Aug 21 08:37:15 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2735625173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_fifo_reset_tx.2735625173
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.2704881020
Short name T1182
Test name
Test status
Simulation time 1559917051 ps
CPU time 3.63 seconds
Started Aug 21 08:37:18 AM UTC 24
Finished Aug 21 08:37:23 AM UTC 24
Peak memory 216440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2704881020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.2704881020
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.2902372467
Short name T1178
Test name
Test status
Simulation time 321967939 ps
CPU time 1.33 seconds
Started Aug 21 08:37:18 AM UTC 24
Finished Aug 21 08:37:20 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2902372467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.2902372467
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_hrst.1894784386
Short name T1179
Test name
Test status
Simulation time 664981813 ps
CPU time 3.9 seconds
Started Aug 21 08:37:16 AM UTC 24
Finished Aug 21 08:37:21 AM UTC 24
Peak memory 231120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1894784386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 33.i2c_target_hrst.1894784386
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.1427312137
Short name T1174
Test name
Test status
Simulation time 4387868302 ps
CPU time 11.23 seconds
Started Aug 21 08:37:04 AM UTC 24
Finished Aug 21 08:37:17 AM UTC 24
Peak memory 233796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1427312137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.1427312137
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.1004378924
Short name T1327
Test name
Test status
Simulation time 13044917460 ps
CPU time 151.67 seconds
Started Aug 21 08:37:04 AM UTC 24
Finished Aug 21 08:39:38 AM UTC 24
Peak memory 2873412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1004378924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.1004378924
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.1702979668
Short name T1188
Test name
Test status
Simulation time 2834045984 ps
CPU time 4.04 seconds
Started Aug 21 08:37:20 AM UTC 24
Finished Aug 21 08:37:26 AM UTC 24
Peak memory 227068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1702979668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 33.i2c_target_nack_acqfull.1702979668
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.1234212726
Short name T1191
Test name
Test status
Simulation time 563249626 ps
CPU time 3.94 seconds
Started Aug 21 08:37:21 AM UTC 24
Finished Aug 21 08:37:26 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1234212726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_nack_acqfull_addr.1234212726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_nack_txstretch.1489577777
Short name T1187
Test name
Test status
Simulation time 143244401 ps
CPU time 2.38 seconds
Started Aug 21 08:37:21 AM UTC 24
Finished Aug 21 08:37:25 AM UTC 24
Peak memory 233528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1489577777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_nack_txstretch.1489577777
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_perf.1416617955
Short name T1181
Test name
Test status
Simulation time 2426622081 ps
CPU time 7.81 seconds
Started Aug 21 08:37:14 AM UTC 24
Finished Aug 21 08:37:23 AM UTC 24
Peak memory 230988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1416617955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 33.i2c_target_perf.1416617955
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.2185243064
Short name T1185
Test name
Test status
Simulation time 530309207 ps
CPU time 3.68 seconds
Started Aug 21 08:37:19 AM UTC 24
Finished Aug 21 08:37:24 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2185243064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 33.i2c_target_smbus_maxlen.2185243064
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.2632941622
Short name T1168
Test name
Test status
Simulation time 619018093 ps
CPU time 9.28 seconds
Started Aug 21 08:36:58 AM UTC 24
Finished Aug 21 08:37:08 AM UTC 24
Peak memory 233652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2632941622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_targ
et_smoke.2632941622
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.1589831697
Short name T1290
Test name
Test status
Simulation time 55988571060 ps
CPU time 102.42 seconds
Started Aug 21 08:37:14 AM UTC 24
Finished Aug 21 08:38:58 AM UTC 24
Peak memory 868580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1589831697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 33.i2c_target_stress_all.1589831697
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.2681212632
Short name T1175
Test name
Test status
Simulation time 742492305 ps
CPU time 14.04 seconds
Started Aug 21 08:37:03 AM UTC 24
Finished Aug 21 08:37:18 AM UTC 24
Peak memory 233568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2681212632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stress_rd.2681212632
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.4044877135
Short name T1318
Test name
Test status
Simulation time 41665091340 ps
CPU time 187.42 seconds
Started Aug 21 08:36:59 AM UTC 24
Finished Aug 21 08:40:09 AM UTC 24
Peak memory 2853088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4044877135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stress_wr.4044877135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_stretch.2835224302
Short name T1197
Test name
Test status
Simulation time 2185181169 ps
CPU time 30.1 seconds
Started Aug 21 08:37:03 AM UTC 24
Finished Aug 21 08:37:34 AM UTC 24
Peak memory 684312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2835224302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_stretch.2835224302
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.2101239899
Short name T1172
Test name
Test status
Simulation time 5201290925 ps
CPU time 9.92 seconds
Started Aug 21 08:37:04 AM UTC 24
Finished Aug 21 08:37:15 AM UTC 24
Peak memory 233896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2101239899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_timeout.2101239899
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.3344586395
Short name T1186
Test name
Test status
Simulation time 137075513 ps
CPU time 4.13 seconds
Started Aug 21 08:37:19 AM UTC 24
Finished Aug 21 08:37:24 AM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3344586395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.3344586395
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_alert_test.2463456590
Short name T1214
Test name
Test status
Simulation time 15386136 ps
CPU time 0.95 seconds
Started Aug 21 08:37:46 AM UTC 24
Finished Aug 21 08:37:48 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2463456590 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2463456590
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.919329637
Short name T1195
Test name
Test status
Simulation time 88530255 ps
CPU time 3.69 seconds
Started Aug 21 08:37:27 AM UTC 24
Finished Aug 21 08:37:33 AM UTC 24
Peak memory 231260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=919329637 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.919329637
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.2885899578
Short name T1194
Test name
Test status
Simulation time 194924990 ps
CPU time 4.68 seconds
Started Aug 21 08:37:25 AM UTC 24
Finished Aug 21 08:37:31 AM UTC 24
Peak memory 254012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2885899578 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empty.2885899578
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.3255624824
Short name T1298
Test name
Test status
Simulation time 3596278136 ps
CPU time 103.81 seconds
Started Aug 21 08:37:26 AM UTC 24
Finished Aug 21 08:39:12 AM UTC 24
Peak memory 751684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3255624824 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3255624824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.3358283123
Short name T1310
Test name
Test status
Simulation time 7480381443 ps
CPU time 113.95 seconds
Started Aug 21 08:37:25 AM UTC 24
Finished Aug 21 08:39:22 AM UTC 24
Peak memory 672140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3358283123 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3358283123
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.2235064400
Short name T1193
Test name
Test status
Simulation time 148837380 ps
CPU time 1.76 seconds
Started Aug 21 08:37:25 AM UTC 24
Finished Aug 21 08:37:28 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2235064400 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.2235064400
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.1322866156
Short name T1154
Test name
Test status
Simulation time 912468298 ps
CPU time 6.79 seconds
Started Aug 21 08:37:25 AM UTC 24
Finished Aug 21 08:37:33 AM UTC 24
Peak memory 260336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1322866156 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.1322866156
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.3978251449
Short name T128
Test name
Test status
Simulation time 14221234906 ps
CPU time 91.22 seconds
Started Aug 21 08:37:24 AM UTC 24
Finished Aug 21 08:38:58 AM UTC 24
Peak memory 1124508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3978251449 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3978251449
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.3195229003
Short name T1215
Test name
Test status
Simulation time 450190369 ps
CPU time 9.03 seconds
Started Aug 21 08:37:39 AM UTC 24
Finished Aug 21 08:37:49 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3195229003 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3195229003
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_override.2239878050
Short name T1190
Test name
Test status
Simulation time 27417580 ps
CPU time 1.08 seconds
Started Aug 21 08:37:24 AM UTC 24
Finished Aug 21 08:37:26 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2239878050 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.2239878050
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_perf.2469021968
Short name T1252
Test name
Test status
Simulation time 6835676641 ps
CPU time 51 seconds
Started Aug 21 08:37:26 AM UTC 24
Finished Aug 21 08:38:19 AM UTC 24
Peak memory 297164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2469021968 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2469021968
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.2895698157
Short name T1122
Test name
Test status
Simulation time 113554932 ps
CPU time 1.94 seconds
Started Aug 21 08:37:26 AM UTC 24
Finished Aug 21 08:37:30 AM UTC 24
Peak memory 238360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2895698157 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.2895698157
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.1479512920
Short name T1224
Test name
Test status
Simulation time 15474985559 ps
CPU time 27.99 seconds
Started Aug 21 08:37:23 AM UTC 24
Finished Aug 21 08:37:53 AM UTC 24
Peak memory 325796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1479512920 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1479512920
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.1882468532
Short name T1235
Test name
Test status
Simulation time 10183636989 ps
CPU time 38.75 seconds
Started Aug 21 08:37:26 AM UTC 24
Finished Aug 21 08:38:07 AM UTC 24
Peak memory 226884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1882468532 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1882468532
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.2165887399
Short name T1205
Test name
Test status
Simulation time 1920544744 ps
CPU time 3.91 seconds
Started Aug 21 08:37:36 AM UTC 24
Finished Aug 21 08:37:41 AM UTC 24
Peak memory 233544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=2165887399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2165887399
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.1516027559
Short name T1200
Test name
Test status
Simulation time 357745802 ps
CPU time 2.19 seconds
Started Aug 21 08:37:34 AM UTC 24
Finished Aug 21 08:37:37 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1516027559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_acq.1516027559
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.1016134005
Short name T1203
Test name
Test status
Simulation time 155672532 ps
CPU time 1.66 seconds
Started Aug 21 08:37:35 AM UTC 24
Finished Aug 21 08:37:38 AM UTC 24
Peak memory 230520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1016134005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_fifo_reset_tx.1016134005
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.600457428
Short name T1207
Test name
Test status
Simulation time 1261525225 ps
CPU time 3.33 seconds
Started Aug 21 08:37:39 AM UTC 24
Finished Aug 21 08:37:43 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=600457428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.600457428
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.3310679813
Short name T1204
Test name
Test status
Simulation time 363855892 ps
CPU time 1.16 seconds
Started Aug 21 08:37:39 AM UTC 24
Finished Aug 21 08:37:41 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3310679813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.3310679813
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.2252774182
Short name T1202
Test name
Test status
Simulation time 2168276193 ps
CPU time 6 seconds
Started Aug 21 08:37:31 AM UTC 24
Finished Aug 21 08:37:38 AM UTC 24
Peak memory 244008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2252774182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.2252774182
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.1903789991
Short name T1257
Test name
Test status
Simulation time 19588505217 ps
CPU time 50.96 seconds
Started Aug 21 08:37:32 AM UTC 24
Finished Aug 21 08:38:24 AM UTC 24
Peak memory 1108460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1903789991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1903789991
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.783847589
Short name T1218
Test name
Test status
Simulation time 587064690 ps
CPU time 5.28 seconds
Started Aug 21 08:37:43 AM UTC 24
Finished Aug 21 08:37:49 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=783847589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 34.i2c_target_nack_acqfull.783847589
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.2317652090
Short name T1211
Test name
Test status
Simulation time 2182816751 ps
CPU time 2.89 seconds
Started Aug 21 08:37:43 AM UTC 24
Finished Aug 21 08:37:47 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2317652090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_nack_acqfull_addr.2317652090
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_nack_txstretch.1561251711
Short name T1213
Test name
Test status
Simulation time 1017165182 ps
CPU time 2.29 seconds
Started Aug 21 08:37:44 AM UTC 24
Finished Aug 21 08:37:47 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1561251711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_nack_txstretch.1561251711
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_perf.4230528830
Short name T1206
Test name
Test status
Simulation time 526851485 ps
CPU time 6.04 seconds
Started Aug 21 08:37:35 AM UTC 24
Finished Aug 21 08:37:42 AM UTC 24
Peak memory 230916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4230528830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 34.i2c_target_perf.4230528830
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.2983286710
Short name T1210
Test name
Test status
Simulation time 5272374435 ps
CPU time 3.7 seconds
Started Aug 21 08:37:42 AM UTC 24
Finished Aug 21 08:37:47 AM UTC 24
Peak memory 216440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2983286710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 34.i2c_target_smbus_maxlen.2983286710
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.1802475801
Short name T1220
Test name
Test status
Simulation time 763748176 ps
CPU time 21.82 seconds
Started Aug 21 08:37:27 AM UTC 24
Finished Aug 21 08:37:51 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1802475801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_targ
et_smoke.1802475801
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.2506712673
Short name T1733
Test name
Test status
Simulation time 44704790194 ps
CPU time 770.39 seconds
Started Aug 21 08:37:36 AM UTC 24
Finished Aug 21 08:50:34 AM UTC 24
Peak memory 6414608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2506712673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 34.i2c_target_stress_all.2506712673
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.4275987790
Short name T1226
Test name
Test status
Simulation time 2161916897 ps
CPU time 22.91 seconds
Started Aug 21 08:37:30 AM UTC 24
Finished Aug 21 08:37:54 AM UTC 24
Peak memory 233748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4275987790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stress_rd.4275987790
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.1527340643
Short name T1400
Test name
Test status
Simulation time 65605686154 ps
CPU time 209.28 seconds
Started Aug 21 08:37:28 AM UTC 24
Finished Aug 21 08:41:00 AM UTC 24
Peak memory 2769120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1527340643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stress_wr.1527340643
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_stretch.1752812864
Short name T1198
Test name
Test status
Simulation time 1308149825 ps
CPU time 3.68 seconds
Started Aug 21 08:37:31 AM UTC 24
Finished Aug 21 08:37:36 AM UTC 24
Peak memory 235620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1752812864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_stretch.1752812864
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.1894598796
Short name T1208
Test name
Test status
Simulation time 1222844643 ps
CPU time 9.84 seconds
Started Aug 21 08:37:34 AM UTC 24
Finished Aug 21 08:37:45 AM UTC 24
Peak memory 233588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1894598796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_timeout.1894598796
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/34.i2c_target_tx_stretch_ctrl.1985329996
Short name T1212
Test name
Test status
Simulation time 116915258 ps
CPU time 4.13 seconds
Started Aug 21 08:37:42 AM UTC 24
Finished Aug 21 08:37:47 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1985329996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.1985329996
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_alert_test.3873800245
Short name T1250
Test name
Test status
Simulation time 48217450 ps
CPU time 0.96 seconds
Started Aug 21 08:38:16 AM UTC 24
Finished Aug 21 08:38:18 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3873800245 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3873800245
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_error_intr.1958578086
Short name T1227
Test name
Test status
Simulation time 71362569 ps
CPU time 2.05 seconds
Started Aug 21 08:37:52 AM UTC 24
Finished Aug 21 08:37:55 AM UTC 24
Peak memory 227144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1958578086 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1958578086
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.854740992
Short name T1230
Test name
Test status
Simulation time 353767891 ps
CPU time 9.34 seconds
Started Aug 21 08:37:49 AM UTC 24
Finished Aug 21 08:37:59 AM UTC 24
Peak memory 292964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=854740992 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty.854740992
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.3915291689
Short name T1363
Test name
Test status
Simulation time 2697758645 ps
CPU time 151.76 seconds
Started Aug 21 08:37:50 AM UTC 24
Finished Aug 21 08:40:24 AM UTC 24
Peak memory 542924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3915291689 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3915291689
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.3613049777
Short name T1280
Test name
Test status
Simulation time 2563570019 ps
CPU time 58.05 seconds
Started Aug 21 08:37:48 AM UTC 24
Finished Aug 21 08:38:48 AM UTC 24
Peak memory 782800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3613049777 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3613049777
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.2473896363
Short name T1222
Test name
Test status
Simulation time 98595826 ps
CPU time 1.75 seconds
Started Aug 21 08:37:48 AM UTC 24
Finished Aug 21 08:37:51 AM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2473896363 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.2473896363
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.2269070842
Short name T1229
Test name
Test status
Simulation time 171974741 ps
CPU time 4.94 seconds
Started Aug 21 08:37:50 AM UTC 24
Finished Aug 21 08:37:56 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2269070842 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.2269070842
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.207097891
Short name T1405
Test name
Test status
Simulation time 19448596953 ps
CPU time 198.65 seconds
Started Aug 21 08:37:47 AM UTC 24
Finished Aug 21 08:41:09 AM UTC 24
Peak memory 1161364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=207097891 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.207097891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.3997339011
Short name T1248
Test name
Test status
Simulation time 404626097 ps
CPU time 6.08 seconds
Started Aug 21 08:38:09 AM UTC 24
Finished Aug 21 08:38:16 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3997339011 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.3997339011
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_override.3433328276
Short name T1219
Test name
Test status
Simulation time 74401929 ps
CPU time 1.07 seconds
Started Aug 21 08:37:47 AM UTC 24
Finished Aug 21 08:37:49 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3433328276 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3433328276
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_perf.259194620
Short name T43
Test name
Test status
Simulation time 1073716586 ps
CPU time 43.64 seconds
Started Aug 21 08:37:50 AM UTC 24
Finished Aug 21 08:38:35 AM UTC 24
Peak memory 352396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=259194620 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.259194620
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.2219988807
Short name T1228
Test name
Test status
Simulation time 727685088 ps
CPU time 4.49 seconds
Started Aug 21 08:37:50 AM UTC 24
Finished Aug 21 08:37:55 AM UTC 24
Peak memory 247868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2219988807 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2219988807
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.1677946342
Short name T1265
Test name
Test status
Simulation time 21626263418 ps
CPU time 46.86 seconds
Started Aug 21 08:37:46 AM UTC 24
Finished Aug 21 08:38:34 AM UTC 24
Peak memory 284904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1677946342 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1677946342
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_stress_all.2775421752
Short name T139
Test name
Test status
Simulation time 10080707529 ps
CPU time 41.73 seconds
Started Aug 21 08:37:52 AM UTC 24
Finished Aug 21 08:38:35 AM UTC 24
Peak memory 344496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2775421752 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2775421752
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.2859314237
Short name T1236
Test name
Test status
Simulation time 1269357820 ps
CPU time 16.72 seconds
Started Aug 21 08:37:50 AM UTC 24
Finished Aug 21 08:38:08 AM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2859314237 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.2859314237
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.1525726035
Short name T1245
Test name
Test status
Simulation time 2325648361 ps
CPU time 5.24 seconds
Started Aug 21 08:38:08 AM UTC 24
Finished Aug 21 08:38:14 AM UTC 24
Peak memory 226976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1525726035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1525726035
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.1744872233
Short name T1233
Test name
Test status
Simulation time 213042848 ps
CPU time 2.02 seconds
Started Aug 21 08:38:03 AM UTC 24
Finished Aug 21 08:38:06 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1744872233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_acq.1744872233
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.4229351647
Short name T1234
Test name
Test status
Simulation time 942304317 ps
CPU time 2.81 seconds
Started Aug 21 08:38:03 AM UTC 24
Finished Aug 21 08:38:07 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4229351647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_fifo_reset_tx.4229351647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.4060012689
Short name T1246
Test name
Test status
Simulation time 523578556 ps
CPU time 4.46 seconds
Started Aug 21 08:38:09 AM UTC 24
Finished Aug 21 08:38:15 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4060012689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.4060012689
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.2074202821
Short name T1243
Test name
Test status
Simulation time 146775711 ps
CPU time 1.36 seconds
Started Aug 21 08:38:10 AM UTC 24
Finished Aug 21 08:38:13 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2074202821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.2074202821
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_hrst.264078869
Short name T1242
Test name
Test status
Simulation time 846690008 ps
CPU time 2.94 seconds
Started Aug 21 08:38:08 AM UTC 24
Finished Aug 21 08:38:12 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=264078869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 35.i2c_target_hrst.264078869
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.1426716880
Short name T1237
Test name
Test status
Simulation time 4101735450 ps
CPU time 11.24 seconds
Started Aug 21 08:37:55 AM UTC 24
Finished Aug 21 08:38:08 AM UTC 24
Peak memory 233212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1426716880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.1426716880
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.4230616114
Short name T1335
Test name
Test status
Simulation time 19267348554 ps
CPU time 115.19 seconds
Started Aug 21 08:37:57 AM UTC 24
Finished Aug 21 08:39:54 AM UTC 24
Peak memory 2400424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=4230616114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.4230616114
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.3206838543
Short name T1251
Test name
Test status
Simulation time 508262627 ps
CPU time 4.44 seconds
Started Aug 21 08:38:14 AM UTC 24
Finished Aug 21 08:38:19 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3206838543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 35.i2c_target_nack_acqfull.3206838543
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.208536865
Short name T1253
Test name
Test status
Simulation time 1846376969 ps
CPU time 4.47 seconds
Started Aug 21 08:38:14 AM UTC 24
Finished Aug 21 08:38:19 AM UTC 24
Peak memory 216396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=208536865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_nack_acqfull_addr.208536865
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_perf.3314183621
Short name T1244
Test name
Test status
Simulation time 2045106554 ps
CPU time 5.23 seconds
Started Aug 21 08:38:07 AM UTC 24
Finished Aug 21 08:38:13 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3314183621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 35.i2c_target_perf.3314183621
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.278948185
Short name T1249
Test name
Test status
Simulation time 441952281 ps
CPU time 3.58 seconds
Started Aug 21 08:38:13 AM UTC 24
Finished Aug 21 08:38:17 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=278948185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 35.i2c_target_smbus_maxlen.278948185
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.3581843766
Short name T1238
Test name
Test status
Simulation time 784547733 ps
CPU time 13.83 seconds
Started Aug 21 08:37:53 AM UTC 24
Finished Aug 21 08:38:08 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3581843766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_targ
et_smoke.3581843766
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.3387218095
Short name T1450
Test name
Test status
Simulation time 51239050613 ps
CPU time 245.84 seconds
Started Aug 21 08:38:07 AM UTC 24
Finished Aug 21 08:42:16 AM UTC 24
Peak memory 3242268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3387218095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 35.i2c_target_stress_all.3387218095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.734728437
Short name T1256
Test name
Test status
Simulation time 2350851824 ps
CPU time 28.39 seconds
Started Aug 21 08:37:54 AM UTC 24
Finished Aug 21 08:38:24 AM UTC 24
Peak memory 243992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=734728437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stress_rd.734728437
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.1308652574
Short name T1740
Test name
Test status
Simulation time 53298871975 ps
CPU time 929.24 seconds
Started Aug 21 08:37:53 AM UTC 24
Finished Aug 21 08:53:32 AM UTC 24
Peak memory 8450336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1308652574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stress_wr.1308652574
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.1486911791
Short name T1232
Test name
Test status
Simulation time 765580352 ps
CPU time 5.73 seconds
Started Aug 21 08:37:55 AM UTC 24
Finished Aug 21 08:38:02 AM UTC 24
Peak memory 260124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1486911791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_stretch.1486911791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.2775535955
Short name T1239
Test name
Test status
Simulation time 5750194339 ps
CPU time 10.74 seconds
Started Aug 21 08:37:57 AM UTC 24
Finished Aug 21 08:38:08 AM UTC 24
Peak memory 226968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2775535955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_timeout.2775535955
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.2073506720
Short name T1259
Test name
Test status
Simulation time 457677005 ps
CPU time 12.03 seconds
Started Aug 21 08:38:12 AM UTC 24
Finished Aug 21 08:38:26 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2073506720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2073506720
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_alert_test.1783978204
Short name T1283
Test name
Test status
Simulation time 19456655 ps
CPU time 1.05 seconds
Started Aug 21 08:38:47 AM UTC 24
Finished Aug 21 08:38:50 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1783978204 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1783978204
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_error_intr.56925057
Short name T1263
Test name
Test status
Simulation time 98579911 ps
CPU time 3.22 seconds
Started Aug 21 08:38:26 AM UTC 24
Finished Aug 21 08:38:30 AM UTC 24
Peak memory 227088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=56925057 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.56925057
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.204476649
Short name T1261
Test name
Test status
Simulation time 512935395 ps
CPU time 5.55 seconds
Started Aug 21 08:38:20 AM UTC 24
Finished Aug 21 08:38:27 AM UTC 24
Peak memory 254056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=204476649 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty.204476649
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.2256496815
Short name T1358
Test name
Test status
Simulation time 3698424274 ps
CPU time 115.17 seconds
Started Aug 21 08:38:20 AM UTC 24
Finished Aug 21 08:40:18 AM UTC 24
Peak memory 739604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2256496815 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2256496815
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.1281241601
Short name T1371
Test name
Test status
Simulation time 1752757501 ps
CPU time 135.54 seconds
Started Aug 21 08:38:19 AM UTC 24
Finished Aug 21 08:40:37 AM UTC 24
Peak memory 620700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1281241601 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1281241601
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.2488455309
Short name T1255
Test name
Test status
Simulation time 278814013 ps
CPU time 1.28 seconds
Started Aug 21 08:38:20 AM UTC 24
Finished Aug 21 08:38:23 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2488455309 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt.2488455309
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.828313408
Short name T1262
Test name
Test status
Simulation time 293550132 ps
CPU time 7.96 seconds
Started Aug 21 08:38:20 AM UTC 24
Finished Aug 21 08:38:29 AM UTC 24
Peak memory 243808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=828313408 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.828313408
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.3316558357
Short name T1328
Test name
Test status
Simulation time 16162307920 ps
CPU time 78.41 seconds
Started Aug 21 08:38:19 AM UTC 24
Finished Aug 21 08:39:39 AM UTC 24
Peak memory 999944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3316558357 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.3316558357
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.2147141306
Short name T1289
Test name
Test status
Simulation time 744409093 ps
CPU time 14.65 seconds
Started Aug 21 08:38:42 AM UTC 24
Finished Aug 21 08:38:58 AM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2147141306 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.2147141306
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_mode_toggle.1401720340
Short name T1275
Test name
Test status
Simulation time 157748870 ps
CPU time 2.03 seconds
Started Aug 21 08:38:41 AM UTC 24
Finished Aug 21 08:38:44 AM UTC 24
Peak memory 227088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1401720340 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1401720340
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_override.1673840176
Short name T163
Test name
Test status
Simulation time 93920787 ps
CPU time 0.94 seconds
Started Aug 21 08:38:18 AM UTC 24
Finished Aug 21 08:38:20 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1673840176 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1673840176
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_perf.290430931
Short name T1747
Test name
Test status
Simulation time 29679772246 ps
CPU time 2189.88 seconds
Started Aug 21 08:38:21 AM UTC 24
Finished Aug 21 09:15:12 AM UTC 24
Peak memory 4464800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=290430931 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.290430931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.485455568
Short name T1260
Test name
Test status
Simulation time 442507864 ps
CPU time 1.95 seconds
Started Aug 21 08:38:24 AM UTC 24
Finished Aug 21 08:38:26 AM UTC 24
Peak memory 238460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=485455568 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.485455568
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.464435229
Short name T1313
Test name
Test status
Simulation time 1871069976 ps
CPU time 67.98 seconds
Started Aug 21 08:38:17 AM UTC 24
Finished Aug 21 08:39:27 AM UTC 24
Peak memory 352360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=464435229 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.464435229
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.875310453
Short name T1272
Test name
Test status
Simulation time 7781000102 ps
CPU time 15.27 seconds
Started Aug 21 08:38:25 AM UTC 24
Finished Aug 21 08:38:41 AM UTC 24
Peak memory 229048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=875310453 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.875310453
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.2316243762
Short name T1284
Test name
Test status
Simulation time 1227690106 ps
CPU time 9.67 seconds
Started Aug 21 08:38:40 AM UTC 24
Finished Aug 21 08:38:51 AM UTC 24
Peak memory 231036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=2316243762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2316243762
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.3732065993
Short name T1268
Test name
Test status
Simulation time 159883397 ps
CPU time 1.34 seconds
Started Aug 21 08:38:36 AM UTC 24
Finished Aug 21 08:38:39 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3732065993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_acq.3732065993
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.2734617960
Short name T1247
Test name
Test status
Simulation time 223161124 ps
CPU time 2.6 seconds
Started Aug 21 08:38:37 AM UTC 24
Finished Aug 21 08:38:41 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2734617960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_fifo_reset_tx.2734617960
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.3166204654
Short name T1279
Test name
Test status
Simulation time 1210867809 ps
CPU time 3.73 seconds
Started Aug 21 08:38:42 AM UTC 24
Finished Aug 21 08:38:47 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3166204654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.3166204654
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.1056408978
Short name T1277
Test name
Test status
Simulation time 127577633 ps
CPU time 1.58 seconds
Started Aug 21 08:38:42 AM UTC 24
Finished Aug 21 08:38:45 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1056408978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.1056408978
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_hrst.3382321584
Short name T1276
Test name
Test status
Simulation time 881255336 ps
CPU time 3.13 seconds
Started Aug 21 08:38:40 AM UTC 24
Finished Aug 21 08:38:44 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3382321584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 36.i2c_target_hrst.3382321584
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.1976411856
Short name T1269
Test name
Test status
Simulation time 7224513329 ps
CPU time 7.93 seconds
Started Aug 21 08:38:31 AM UTC 24
Finished Aug 21 08:38:40 AM UTC 24
Peak memory 233812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1976411856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.1976411856
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.2454861751
Short name T1300
Test name
Test status
Simulation time 15854990112 ps
CPU time 37.51 seconds
Started Aug 21 08:38:35 AM UTC 24
Finished Aug 21 08:39:14 AM UTC 24
Peak memory 651496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2454861751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.2454861751
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.1755108245
Short name T1287
Test name
Test status
Simulation time 9204630777 ps
CPU time 4.72 seconds
Started Aug 21 08:38:45 AM UTC 24
Finished Aug 21 08:38:51 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1755108245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 36.i2c_target_nack_acqfull.1755108245
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.1793563700
Short name T1285
Test name
Test status
Simulation time 531051499 ps
CPU time 4.18 seconds
Started Aug 21 08:38:45 AM UTC 24
Finished Aug 21 08:38:51 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1793563700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_nack_acqfull_addr.1793563700
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_nack_txstretch.1069823301
Short name T1282
Test name
Test status
Simulation time 130785769 ps
CPU time 2.59 seconds
Started Aug 21 08:38:45 AM UTC 24
Finished Aug 21 08:38:49 AM UTC 24
Peak memory 233476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1069823301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_nack_txstretch.1069823301
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_perf.720840832
Short name T1273
Test name
Test status
Simulation time 512449194 ps
CPU time 5.2 seconds
Started Aug 21 08:38:38 AM UTC 24
Finished Aug 21 08:38:44 AM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=720840832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 36.i2c_target_perf.720840832
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.3330966630
Short name T1281
Test name
Test status
Simulation time 563621555 ps
CPU time 3.55 seconds
Started Aug 21 08:38:44 AM UTC 24
Finished Aug 21 08:38:49 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3330966630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 36.i2c_target_smbus_maxlen.3330966630
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.1412355547
Short name T1737
Test name
Test status
Simulation time 40391899363 ps
CPU time 784.84 seconds
Started Aug 21 08:38:39 AM UTC 24
Finished Aug 21 08:51:51 AM UTC 24
Peak memory 6810128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1412355547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 36.i2c_target_stress_all.1412355547
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.972310719
Short name T1264
Test name
Test status
Simulation time 1043999515 ps
CPU time 5.19 seconds
Started Aug 21 08:38:28 AM UTC 24
Finished Aug 21 08:38:34 AM UTC 24
Peak memory 216604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=972310719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stress_rd.972310719
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.1986157236
Short name T1270
Test name
Test status
Simulation time 9652292155 ps
CPU time 11.68 seconds
Started Aug 21 08:38:28 AM UTC 24
Finished Aug 21 08:38:41 AM UTC 24
Peak memory 216964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1986157236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stress_wr.1986157236
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.2621047024
Short name T1267
Test name
Test status
Simulation time 1890170389 ps
CPU time 5.1 seconds
Started Aug 21 08:38:30 AM UTC 24
Finished Aug 21 08:38:36 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2621047024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_stretch.2621047024
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.3418354409
Short name T1274
Test name
Test status
Simulation time 2612188975 ps
CPU time 7.51 seconds
Started Aug 21 08:38:35 AM UTC 24
Finished Aug 21 08:38:44 AM UTC 24
Peak memory 233940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3418354409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_timeout.3418354409
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/36.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_alert_test.1940653441
Short name T1317
Test name
Test status
Simulation time 36059139 ps
CPU time 0.89 seconds
Started Aug 21 08:39:28 AM UTC 24
Finished Aug 21 08:39:30 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1940653441 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1940653441
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_error_intr.3924754165
Short name T1293
Test name
Test status
Simulation time 1402503085 ps
CPU time 4.44 seconds
Started Aug 21 08:38:58 AM UTC 24
Finished Aug 21 08:39:04 AM UTC 24
Peak memory 245996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3924754165 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3924754165
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.1285372980
Short name T1296
Test name
Test status
Simulation time 338086753 ps
CPU time 16.41 seconds
Started Aug 21 08:38:52 AM UTC 24
Finished Aug 21 08:39:09 AM UTC 24
Peak memory 264216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1285372980 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empty.1285372980
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.3055399109
Short name T1223
Test name
Test status
Simulation time 5723827346 ps
CPU time 160.65 seconds
Started Aug 21 08:38:52 AM UTC 24
Finished Aug 21 08:41:35 AM UTC 24
Peak memory 514236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3055399109 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.3055399109
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_overflow.2704012531
Short name T1386
Test name
Test status
Simulation time 1438195185 ps
CPU time 112.01 seconds
Started Aug 21 08:38:50 AM UTC 24
Finished Aug 21 08:40:44 AM UTC 24
Peak memory 569424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2704012531 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2704012531
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.3521740232
Short name T1288
Test name
Test status
Simulation time 96162305 ps
CPU time 1.34 seconds
Started Aug 21 08:38:51 AM UTC 24
Finished Aug 21 08:38:53 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3521740232 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt.3521740232
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.3738734806
Short name T1294
Test name
Test status
Simulation time 210857405 ps
CPU time 11.22 seconds
Started Aug 21 08:38:52 AM UTC 24
Finished Aug 21 08:39:04 AM UTC 24
Peak memory 256084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3738734806 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.3738734806
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.4281416161
Short name T1364
Test name
Test status
Simulation time 16307471159 ps
CPU time 93.7 seconds
Started Aug 21 08:38:50 AM UTC 24
Finished Aug 21 08:40:25 AM UTC 24
Peak memory 1081576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4281416161 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.4281416161
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.2003917425
Short name T1329
Test name
Test status
Simulation time 1570881732 ps
CPU time 18.94 seconds
Started Aug 21 08:39:21 AM UTC 24
Finished Aug 21 08:39:41 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2003917425 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2003917425
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_override.1809444399
Short name T1286
Test name
Test status
Simulation time 278036079 ps
CPU time 0.94 seconds
Started Aug 21 08:38:49 AM UTC 24
Finished Aug 21 08:38:51 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1809444399 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1809444399
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_perf.777544489
Short name T1299
Test name
Test status
Simulation time 2807032101 ps
CPU time 20.26 seconds
Started Aug 21 08:38:52 AM UTC 24
Finished Aug 21 08:39:13 AM UTC 24
Peak memory 256412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=777544489 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.777544489
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.1282011040
Short name T1291
Test name
Test status
Simulation time 182353953 ps
CPU time 3.22 seconds
Started Aug 21 08:38:54 AM UTC 24
Finished Aug 21 08:38:58 AM UTC 24
Peak memory 226976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1282011040 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.1282011040
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.2843099878
Short name T1333
Test name
Test status
Simulation time 8396476822 ps
CPU time 57.87 seconds
Started Aug 21 08:38:48 AM UTC 24
Finished Aug 21 08:39:47 AM UTC 24
Peak memory 375060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2843099878 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2843099878
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.1367384598
Short name T1325
Test name
Test status
Simulation time 680793569 ps
CPU time 36.28 seconds
Started Aug 21 08:38:58 AM UTC 24
Finished Aug 21 08:39:36 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1367384598 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.1367384598
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.2422199070
Short name T1312
Test name
Test status
Simulation time 809457733 ps
CPU time 6.59 seconds
Started Aug 21 08:39:18 AM UTC 24
Finished Aug 21 08:39:26 AM UTC 24
Peak memory 227036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=2422199070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2422199070
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.1917932971
Short name T1304
Test name
Test status
Simulation time 457947564 ps
CPU time 2.07 seconds
Started Aug 21 08:39:14 AM UTC 24
Finished Aug 21 08:39:17 AM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1917932971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_fifo_reset_acq.1917932971
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.3688764014
Short name T1306
Test name
Test status
Simulation time 1748024167 ps
CPU time 2.13 seconds
Started Aug 21 08:39:15 AM UTC 24
Finished Aug 21 08:39:19 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3688764014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_fifo_reset_tx.3688764014
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.1410121325
Short name T1314
Test name
Test status
Simulation time 1784868205 ps
CPU time 4.58 seconds
Started Aug 21 08:39:22 AM UTC 24
Finished Aug 21 08:39:27 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1410121325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.1410121325
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.1181829146
Short name T1311
Test name
Test status
Simulation time 426689153 ps
CPU time 1.74 seconds
Started Aug 21 08:39:22 AM UTC 24
Finished Aug 21 08:39:25 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1181829146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.1181829146
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.2376539793
Short name T1302
Test name
Test status
Simulation time 1280962053 ps
CPU time 6.68 seconds
Started Aug 21 08:39:09 AM UTC 24
Finished Aug 21 08:39:17 AM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2376539793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_intr_smoke.2376539793
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.3393436526
Short name T1365
Test name
Test status
Simulation time 21707986812 ps
CPU time 77.74 seconds
Started Aug 21 08:39:10 AM UTC 24
Finished Aug 21 08:40:30 AM UTC 24
Peak memory 1784040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3393436526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3393436526
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.3564207523
Short name T1320
Test name
Test status
Simulation time 440594254 ps
CPU time 4.06 seconds
Started Aug 21 08:39:26 AM UTC 24
Finished Aug 21 08:39:31 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3564207523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_target_nack_acqfull.3564207523
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.508973964
Short name T1322
Test name
Test status
Simulation time 1874781511 ps
CPU time 4.39 seconds
Started Aug 21 08:39:27 AM UTC 24
Finished Aug 21 08:39:33 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=508973964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_nack_acqfull_addr.508973964
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_perf.1330611265
Short name T1316
Test name
Test status
Simulation time 3441857073 ps
CPU time 10.03 seconds
Started Aug 21 08:39:17 AM UTC 24
Finished Aug 21 08:39:28 AM UTC 24
Peak memory 248044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1330611265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 37.i2c_target_perf.1330611265
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.2474526508
Short name T1319
Test name
Test status
Simulation time 723512121 ps
CPU time 4.8 seconds
Started Aug 21 08:39:25 AM UTC 24
Finished Aug 21 08:39:31 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2474526508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_target_smbus_maxlen.2474526508
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.3224586763
Short name T1297
Test name
Test status
Simulation time 1292313416 ps
CPU time 8.91 seconds
Started Aug 21 08:38:59 AM UTC 24
Finished Aug 21 08:39:10 AM UTC 24
Peak memory 227076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3224586763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_targ
et_smoke.3224586763
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.3539806644
Short name T1571
Test name
Test status
Simulation time 22699918343 ps
CPU time 366.4 seconds
Started Aug 21 08:39:17 AM UTC 24
Finished Aug 21 08:45:28 AM UTC 24
Peak memory 4587700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3539806644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 37.i2c_target_stress_all.3539806644
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.874735166
Short name T1308
Test name
Test status
Simulation time 733361415 ps
CPU time 15.25 seconds
Started Aug 21 08:39:05 AM UTC 24
Finished Aug 21 08:39:21 AM UTC 24
Peak memory 233028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=874735166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stress_rd.874735166
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.2076228791
Short name T1303
Test name
Test status
Simulation time 41237250915 ps
CPU time 63.89 seconds
Started Aug 21 08:39:04 AM UTC 24
Finished Aug 21 08:40:09 AM UTC 24
Peak memory 1249520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2076228791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stress_wr.2076228791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_stretch.2804564840
Short name T1295
Test name
Test status
Simulation time 1829712034 ps
CPU time 2.61 seconds
Started Aug 21 08:39:05 AM UTC 24
Finished Aug 21 08:39:08 AM UTC 24
Peak memory 218624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2804564840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_stretch.2804564840
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.357087186
Short name T1307
Test name
Test status
Simulation time 5043683279 ps
CPU time 7.29 seconds
Started Aug 21 08:39:11 AM UTC 24
Finished Aug 21 08:39:20 AM UTC 24
Peak memory 227192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=357087186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_timeout.357087186
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.2698637311
Short name T1315
Test name
Test status
Simulation time 88669948 ps
CPU time 3.36 seconds
Started Aug 21 08:39:23 AM UTC 24
Finished Aug 21 08:39:27 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2698637311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.2698637311
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_alert_test.1109106922
Short name T1351
Test name
Test status
Simulation time 17872902 ps
CPU time 0.95 seconds
Started Aug 21 08:40:08 AM UTC 24
Finished Aug 21 08:40:10 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1109106922 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1109106922
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.350043367
Short name T1331
Test name
Test status
Simulation time 142200188 ps
CPU time 2.67 seconds
Started Aug 21 08:39:37 AM UTC 24
Finished Aug 21 08:39:41 AM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=350043367 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.350043367
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.1606369687
Short name T1332
Test name
Test status
Simulation time 1239960364 ps
CPU time 7.94 seconds
Started Aug 21 08:39:33 AM UTC 24
Finished Aug 21 08:39:42 AM UTC 24
Peak memory 274532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1606369687 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty.1606369687
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.767224577
Short name T1374
Test name
Test status
Simulation time 13063752762 ps
CPU time 63.25 seconds
Started Aug 21 08:39:34 AM UTC 24
Finished Aug 21 08:40:39 AM UTC 24
Peak memory 432400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=767224577 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.767224577
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.3408106385
Short name T1435
Test name
Test status
Simulation time 10043704220 ps
CPU time 147.43 seconds
Started Aug 21 08:39:32 AM UTC 24
Finished Aug 21 08:42:01 AM UTC 24
Peak memory 856536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3408106385 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3408106385
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.1013015979
Short name T1324
Test name
Test status
Simulation time 440021090 ps
CPU time 1.4 seconds
Started Aug 21 08:39:32 AM UTC 24
Finished Aug 21 08:39:34 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1013015979 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.1013015979
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.1201769434
Short name T1330
Test name
Test status
Simulation time 812283648 ps
CPU time 7.08 seconds
Started Aug 21 08:39:33 AM UTC 24
Finished Aug 21 08:39:41 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1201769434 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.1201769434
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.171517922
Short name T1398
Test name
Test status
Simulation time 7301849210 ps
CPU time 81.86 seconds
Started Aug 21 08:39:31 AM UTC 24
Finished Aug 21 08:40:55 AM UTC 24
Peak memory 1110168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=171517922 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.171517922
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.861618843
Short name T1362
Test name
Test status
Simulation time 425694149 ps
CPU time 21.67 seconds
Started Aug 21 08:39:58 AM UTC 24
Finished Aug 21 08:40:21 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=861618843 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.861618843
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_mode_toggle.285888384
Short name T1344
Test name
Test status
Simulation time 318714184 ps
CPU time 3.63 seconds
Started Aug 21 08:39:58 AM UTC 24
Finished Aug 21 08:40:03 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=285888384 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.285888384
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_override.309097894
Short name T1321
Test name
Test status
Simulation time 32624664 ps
CPU time 1.09 seconds
Started Aug 21 08:39:29 AM UTC 24
Finished Aug 21 08:39:32 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=309097894 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.309097894
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_perf.1937551126
Short name T1339
Test name
Test status
Simulation time 2925769704 ps
CPU time 22.1 seconds
Started Aug 21 08:39:34 AM UTC 24
Finished Aug 21 08:39:57 AM UTC 24
Peak memory 387224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1937551126 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1937551126
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.2623493284
Short name T1326
Test name
Test status
Simulation time 75069781 ps
CPU time 1.55 seconds
Started Aug 21 08:39:35 AM UTC 24
Finished Aug 21 08:39:38 AM UTC 24
Peak memory 236464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2623493284 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.2623493284
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.375428439
Short name T1379
Test name
Test status
Simulation time 1369869326 ps
CPU time 70.48 seconds
Started Aug 21 08:39:28 AM UTC 24
Finished Aug 21 08:40:41 AM UTC 24
Peak memory 415952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=375428439 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.375428439
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.2704236477
Short name T1346
Test name
Test status
Simulation time 3567008928 ps
CPU time 26.01 seconds
Started Aug 21 08:39:37 AM UTC 24
Finished Aug 21 08:40:05 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2704236477 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2704236477
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.1828278334
Short name T1349
Test name
Test status
Simulation time 2551088018 ps
CPU time 8.22 seconds
Started Aug 21 08:39:58 AM UTC 24
Finished Aug 21 08:40:08 AM UTC 24
Peak memory 227184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1828278334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1828278334
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.1426144654
Short name T1341
Test name
Test status
Simulation time 122532597 ps
CPU time 1.5 seconds
Started Aug 21 08:39:55 AM UTC 24
Finished Aug 21 08:39:58 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1426144654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_fifo_reset_acq.1426144654
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.4159942628
Short name T1342
Test name
Test status
Simulation time 415505942 ps
CPU time 1.56 seconds
Started Aug 21 08:39:57 AM UTC 24
Finished Aug 21 08:40:00 AM UTC 24
Peak memory 226476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4159942628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_fifo_reset_tx.4159942628
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.2200376024
Short name T1348
Test name
Test status
Simulation time 1908935870 ps
CPU time 4.28 seconds
Started Aug 21 08:40:00 AM UTC 24
Finished Aug 21 08:40:06 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2200376024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.2200376024
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.1739373056
Short name T1347
Test name
Test status
Simulation time 388836433 ps
CPU time 1.2 seconds
Started Aug 21 08:40:03 AM UTC 24
Finished Aug 21 08:40:05 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1739373056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.1739373056
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_hrst.148861038
Short name T1343
Test name
Test status
Simulation time 166202477 ps
CPU time 2.21 seconds
Started Aug 21 08:39:58 AM UTC 24
Finished Aug 21 08:40:01 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=148861038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 38.i2c_target_hrst.148861038
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.1936804303
Short name T1336
Test name
Test status
Simulation time 1430252749 ps
CPU time 13.35 seconds
Started Aug 21 08:39:42 AM UTC 24
Finished Aug 21 08:39:56 AM UTC 24
Peak memory 233528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1936804303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.1936804303
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.723538271
Short name T1345
Test name
Test status
Simulation time 9733644628 ps
CPU time 20.5 seconds
Started Aug 21 08:39:43 AM UTC 24
Finished Aug 21 08:40:04 AM UTC 24
Peak memory 616680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=723538271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.723538271
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.1415688459
Short name T1354
Test name
Test status
Simulation time 1048444492 ps
CPU time 4.13 seconds
Started Aug 21 08:40:06 AM UTC 24
Finished Aug 21 08:40:11 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1415688459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_target_nack_acqfull.1415688459
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.3403552898
Short name T1353
Test name
Test status
Simulation time 2012724899 ps
CPU time 3.92 seconds
Started Aug 21 08:40:06 AM UTC 24
Finished Aug 21 08:40:11 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3403552898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_nack_acqfull_addr.3403552898
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_nack_txstretch.1115910464
Short name T1352
Test name
Test status
Simulation time 176240242 ps
CPU time 2.66 seconds
Started Aug 21 08:40:07 AM UTC 24
Finished Aug 21 08:40:11 AM UTC 24
Peak memory 233432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1115910464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_nack_txstretch.1115910464
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_perf.1456028117
Short name T1278
Test name
Test status
Simulation time 965822355 ps
CPU time 10.42 seconds
Started Aug 21 08:39:57 AM UTC 24
Finished Aug 21 08:40:09 AM UTC 24
Peak memory 250112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1456028117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 38.i2c_target_perf.1456028117
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.3529089721
Short name T1350
Test name
Test status
Simulation time 2276256630 ps
CPU time 3.55 seconds
Started Aug 21 08:40:05 AM UTC 24
Finished Aug 21 08:40:09 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3529089721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_target_smbus_maxlen.3529089721
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.2561543755
Short name T1334
Test name
Test status
Simulation time 3227379416 ps
CPU time 12.67 seconds
Started Aug 21 08:39:39 AM UTC 24
Finished Aug 21 08:39:53 AM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2561543755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_targ
et_smoke.2561543755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.3629234942
Short name T1402
Test name
Test status
Simulation time 43398400532 ps
CPU time 66.65 seconds
Started Aug 21 08:39:57 AM UTC 24
Finished Aug 21 08:41:05 AM UTC 24
Peak memory 477356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3629234942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 38.i2c_target_stress_all.3629234942
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.265080472
Short name T1340
Test name
Test status
Simulation time 2404217879 ps
CPU time 14.73 seconds
Started Aug 21 08:39:41 AM UTC 24
Finished Aug 21 08:39:57 AM UTC 24
Peak memory 228936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=265080472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stress_rd.265080472
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.2247306873
Short name T1524
Test name
Test status
Simulation time 36930891709 ps
CPU time 291.91 seconds
Started Aug 21 08:39:40 AM UTC 24
Finished Aug 21 08:44:36 AM UTC 24
Peak memory 4039068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2247306873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stress_wr.2247306873
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_stretch.146947605
Short name T1338
Test name
Test status
Simulation time 875263535 ps
CPU time 14.21 seconds
Started Aug 21 08:39:42 AM UTC 24
Finished Aug 21 08:39:57 AM UTC 24
Peak memory 376872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=146947605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_tar
get_stretch.146947605
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.1720670818
Short name T1337
Test name
Test status
Simulation time 4250994879 ps
CPU time 7.29 seconds
Started Aug 21 08:39:48 AM UTC 24
Finished Aug 21 08:39:56 AM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1720670818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_timeout.1720670818
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/38.i2c_target_tx_stretch_ctrl.531151534
Short name T1355
Test name
Test status
Simulation time 487996987 ps
CPU time 6.32 seconds
Started Aug 21 08:40:04 AM UTC 24
Finished Aug 21 08:40:11 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=531151534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_tx_stretch_ctrl.531151534
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_alert_test.875173436
Short name T1387
Test name
Test status
Simulation time 46606381 ps
CPU time 0.92 seconds
Started Aug 21 08:40:43 AM UTC 24
Finished Aug 21 08:40:45 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=875173436 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.875173436
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_error_intr.2212838023
Short name T1360
Test name
Test status
Simulation time 64606571 ps
CPU time 1.84 seconds
Started Aug 21 08:40:17 AM UTC 24
Finished Aug 21 08:40:20 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212838023 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2212838023
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.1116587246
Short name T1361
Test name
Test status
Simulation time 312371843 ps
CPU time 7.51 seconds
Started Aug 21 08:40:11 AM UTC 24
Finished Aug 21 08:40:20 AM UTC 24
Peak memory 256200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1116587246 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty.1116587246
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.578263888
Short name T1477
Test name
Test status
Simulation time 2470876181 ps
CPU time 162.81 seconds
Started Aug 21 08:40:11 AM UTC 24
Finished Aug 21 08:42:57 AM UTC 24
Peak memory 688400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=578263888 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.578263888
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.1908038598
Short name T1411
Test name
Test status
Simulation time 2245057796 ps
CPU time 61.09 seconds
Started Aug 21 08:40:10 AM UTC 24
Finished Aug 21 08:41:13 AM UTC 24
Peak memory 776408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1908038598 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1908038598
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.3849544030
Short name T1356
Test name
Test status
Simulation time 1566999493 ps
CPU time 1.37 seconds
Started Aug 21 08:40:11 AM UTC 24
Finished Aug 21 08:40:14 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3849544030 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt.3849544030
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.2157481774
Short name T1359
Test name
Test status
Simulation time 1326623751 ps
CPU time 5.62 seconds
Started Aug 21 08:40:11 AM UTC 24
Finished Aug 21 08:40:18 AM UTC 24
Peak memory 241964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2157481774 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.2157481774
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.1852916733
Short name T1559
Test name
Test status
Simulation time 4812387329 ps
CPU time 296.8 seconds
Started Aug 21 08:40:10 AM UTC 24
Finished Aug 21 08:45:11 AM UTC 24
Peak memory 1323156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1852916733 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1852916733
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.1348362238
Short name T1381
Test name
Test status
Simulation time 577597341 ps
CPU time 6.37 seconds
Started Aug 21 08:40:35 AM UTC 24
Finished Aug 21 08:40:43 AM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1348362238 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1348362238
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_perf.862503563
Short name T1627
Test name
Test status
Simulation time 47558384410 ps
CPU time 381.34 seconds
Started Aug 21 08:40:12 AM UTC 24
Finished Aug 21 08:46:38 AM UTC 24
Peak memory 226968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=862503563 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.862503563
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.1283094034
Short name T1739
Test name
Test status
Simulation time 23223065293 ps
CPU time 789.64 seconds
Started Aug 21 08:40:13 AM UTC 24
Finished Aug 21 08:53:32 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1283094034 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.1283094034
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.1329732872
Short name T1393
Test name
Test status
Simulation time 1544259296 ps
CPU time 37.04 seconds
Started Aug 21 08:40:09 AM UTC 24
Finished Aug 21 08:40:48 AM UTC 24
Peak memory 362876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1329732872 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1329732872
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.1709062721
Short name T1366
Test name
Test status
Simulation time 1653214600 ps
CPU time 14.63 seconds
Started Aug 21 08:40:15 AM UTC 24
Finished Aug 21 08:40:30 AM UTC 24
Peak memory 233488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1709062721 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1709062721
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.1327723720
Short name T1384
Test name
Test status
Simulation time 731492055 ps
CPU time 7.24 seconds
Started Aug 21 08:40:35 AM UTC 24
Finished Aug 21 08:40:43 AM UTC 24
Peak memory 228752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1327723720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1327723720
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.3240068621
Short name T1367
Test name
Test status
Simulation time 762901800 ps
CPU time 2.12 seconds
Started Aug 21 08:40:31 AM UTC 24
Finished Aug 21 08:40:34 AM UTC 24
Peak memory 216704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3240068621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_acq.3240068621
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.543287125
Short name T1369
Test name
Test status
Simulation time 159405732 ps
CPU time 1.12 seconds
Started Aug 21 08:40:32 AM UTC 24
Finished Aug 21 08:40:34 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=543287125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 39.i2c_target_fifo_reset_tx.543287125
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.2993091769
Short name T1383
Test name
Test status
Simulation time 1049802516 ps
CPU time 3.43 seconds
Started Aug 21 08:40:38 AM UTC 24
Finished Aug 21 08:40:43 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2993091769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.2993091769
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.2171262043
Short name T1380
Test name
Test status
Simulation time 531264953 ps
CPU time 1.65 seconds
Started Aug 21 08:40:39 AM UTC 24
Finished Aug 21 08:40:42 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2171262043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.2171262043
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_hrst.1684957955
Short name T1375
Test name
Test status
Simulation time 2290763111 ps
CPU time 3.89 seconds
Started Aug 21 08:40:35 AM UTC 24
Finished Aug 21 08:40:40 AM UTC 24
Peak memory 227196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1684957955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 39.i2c_target_hrst.1684957955
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.3804662880
Short name T1368
Test name
Test status
Simulation time 4947248890 ps
CPU time 10.49 seconds
Started Aug 21 08:40:22 AM UTC 24
Finished Aug 21 08:40:34 AM UTC 24
Peak memory 243948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3804662880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.3804662880
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.352546679
Short name T1376
Test name
Test status
Simulation time 17503675523 ps
CPU time 14.64 seconds
Started Aug 21 08:40:24 AM UTC 24
Finished Aug 21 08:40:40 AM UTC 24
Peak memory 216956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=352546679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.352546679
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.1260510851
Short name T1388
Test name
Test status
Simulation time 4561117318 ps
CPU time 3.13 seconds
Started Aug 21 08:40:40 AM UTC 24
Finished Aug 21 08:40:45 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1260510851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 39.i2c_target_nack_acqfull.1260510851
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.2280921188
Short name T1392
Test name
Test status
Simulation time 1021240686 ps
CPU time 4.02 seconds
Started Aug 21 08:40:42 AM UTC 24
Finished Aug 21 08:40:47 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2280921188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_nack_acqfull_addr.2280921188
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.3384774486
Short name T1389
Test name
Test status
Simulation time 2405304641 ps
CPU time 2.47 seconds
Started Aug 21 08:40:42 AM UTC 24
Finished Aug 21 08:40:45 AM UTC 24
Peak memory 233884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3384774486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_nack_txstretch.3384774486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_perf.499753533
Short name T1382
Test name
Test status
Simulation time 3715963954 ps
CPU time 7.82 seconds
Started Aug 21 08:40:34 AM UTC 24
Finished Aug 21 08:40:43 AM UTC 24
Peak memory 233640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=499753533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.i2c_target_perf.499753533
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.1491603333
Short name T1385
Test name
Test status
Simulation time 711825314 ps
CPU time 3.49 seconds
Started Aug 21 08:40:39 AM UTC 24
Finished Aug 21 08:40:44 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1491603333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 39.i2c_target_smbus_maxlen.1491603333
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.3786317640
Short name T1370
Test name
Test status
Simulation time 1426695712 ps
CPU time 14.25 seconds
Started Aug 21 08:40:19 AM UTC 24
Finished Aug 21 08:40:34 AM UTC 24
Peak memory 233572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3786317640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_targ
et_smoke.3786317640
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.2404282317
Short name T1241
Test name
Test status
Simulation time 23540073759 ps
CPU time 66.59 seconds
Started Aug 21 08:40:35 AM UTC 24
Finished Aug 21 08:41:43 AM UTC 24
Peak memory 782576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2404282317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 39.i2c_target_stress_all.2404282317
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.3577009697
Short name T1423
Test name
Test status
Simulation time 1066618078 ps
CPU time 57.94 seconds
Started Aug 21 08:40:21 AM UTC 24
Finished Aug 21 08:41:21 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3577009697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stress_rd.3577009697
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.3282216196
Short name T1397
Test name
Test status
Simulation time 44147694587 ps
CPU time 33.62 seconds
Started Aug 21 08:40:20 AM UTC 24
Finished Aug 21 08:40:55 AM UTC 24
Peak memory 768412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3282216196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stress_wr.3282216196
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_stretch.741182111
Short name T1395
Test name
Test status
Simulation time 2100604100 ps
CPU time 26.32 seconds
Started Aug 21 08:40:21 AM UTC 24
Finished Aug 21 08:40:49 AM UTC 24
Peak memory 327956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=741182111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_tar
get_stretch.741182111
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.3363600721
Short name T1373
Test name
Test status
Simulation time 1138680256 ps
CPU time 10.9 seconds
Started Aug 21 08:40:26 AM UTC 24
Finished Aug 21 08:40:39 AM UTC 24
Peak memory 233628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3363600721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_timeout.3363600721
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.2815485083
Short name T1391
Test name
Test status
Simulation time 239015653 ps
CPU time 5.54 seconds
Started Aug 21 08:40:39 AM UTC 24
Finished Aug 21 08:40:46 AM UTC 24
Peak memory 216664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2815485083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.2815485083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_alert_test.2673674206
Short name T346
Test name
Test status
Simulation time 39683113 ps
CPU time 0.75 seconds
Started Aug 21 08:23:08 AM UTC 24
Finished Aug 21 08:23:10 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2673674206 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2673674206
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.56391786
Short name T23
Test name
Test status
Simulation time 206734257 ps
CPU time 1.92 seconds
Started Aug 21 08:22:54 AM UTC 24
Finished Aug 21 08:22:58 AM UTC 24
Peak memory 228232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=56391786 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.56391786
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.2590642434
Short name T196
Test name
Test status
Simulation time 479319899 ps
CPU time 5.88 seconds
Started Aug 21 08:22:53 AM UTC 24
Finished Aug 21 08:23:00 AM UTC 24
Peak memory 252004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590642434 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty.2590642434
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.2527528575
Short name T190
Test name
Test status
Simulation time 7137114837 ps
CPU time 137.99 seconds
Started Aug 21 08:22:53 AM UTC 24
Finished Aug 21 08:25:14 AM UTC 24
Peak memory 393688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2527528575 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2527528575
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.3974503902
Short name T209
Test name
Test status
Simulation time 5049006395 ps
CPU time 58.25 seconds
Started Aug 21 08:22:53 AM UTC 24
Finished Aug 21 08:23:53 AM UTC 24
Peak memory 821392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3974503902 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3974503902
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.3684421373
Short name T338
Test name
Test status
Simulation time 426800371 ps
CPU time 1.24 seconds
Started Aug 21 08:22:53 AM UTC 24
Finished Aug 21 08:22:56 AM UTC 24
Peak memory 216404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3684421373 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.3684421373
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.1280572656
Short name T88
Test name
Test status
Simulation time 144393063 ps
CPU time 3.24 seconds
Started Aug 21 08:22:53 AM UTC 24
Finished Aug 21 08:22:58 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1280572656 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.1280572656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.2725076347
Short name T91
Test name
Test status
Simulation time 25234796597 ps
CPU time 120.9 seconds
Started Aug 21 08:22:53 AM UTC 24
Finished Aug 21 08:24:56 AM UTC 24
Peak memory 1442020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2725076347 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2725076347
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.3069226351
Short name T45
Test name
Test status
Simulation time 1704311448 ps
CPU time 19.15 seconds
Started Aug 21 08:23:02 AM UTC 24
Finished Aug 21 08:23:22 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3069226351 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3069226351
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_override.1777054118
Short name T337
Test name
Test status
Simulation time 15411716 ps
CPU time 0.97 seconds
Started Aug 21 08:22:52 AM UTC 24
Finished Aug 21 08:22:54 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1777054118 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.1777054118
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_perf.1041369351
Short name T259
Test name
Test status
Simulation time 6053386649 ps
CPU time 20 seconds
Started Aug 21 08:22:53 AM UTC 24
Finished Aug 21 08:23:15 AM UTC 24
Peak memory 256212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1041369351 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1041369351
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.3330438332
Short name T194
Test name
Test status
Simulation time 72909576 ps
CPU time 3.75 seconds
Started Aug 21 08:22:54 AM UTC 24
Finished Aug 21 08:23:00 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3330438332 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.3330438332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.2487245951
Short name T355
Test name
Test status
Simulation time 8565584685 ps
CPU time 26.1 seconds
Started Aug 21 08:22:52 AM UTC 24
Finished Aug 21 08:23:20 AM UTC 24
Peak memory 352380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2487245951 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2487245951
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.1980078463
Short name T165
Test name
Test status
Simulation time 592484735 ps
CPU time 25.89 seconds
Started Aug 21 08:22:54 AM UTC 24
Finished Aug 21 08:23:22 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1980078463 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1980078463
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.2170473952
Short name T220
Test name
Test status
Simulation time 210180504 ps
CPU time 1.38 seconds
Started Aug 21 08:23:07 AM UTC 24
Finished Aug 21 08:23:09 AM UTC 24
Peak memory 246804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2170473952 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2170473952
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.1797642997
Short name T344
Test name
Test status
Simulation time 1169484155 ps
CPU time 6.51 seconds
Started Aug 21 08:23:00 AM UTC 24
Finished Aug 21 08:23:08 AM UTC 24
Peak memory 232840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1797642997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1797642997
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.3744938676
Short name T197
Test name
Test status
Simulation time 160664599 ps
CPU time 1.6 seconds
Started Aug 21 08:22:58 AM UTC 24
Finished Aug 21 08:23:01 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3744938676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_acq.3744938676
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.732047661
Short name T198
Test name
Test status
Simulation time 208253455 ps
CPU time 1.36 seconds
Started Aug 21 08:22:59 AM UTC 24
Finished Aug 21 08:23:02 AM UTC 24
Peak memory 214332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=732047661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 4.i2c_target_fifo_reset_tx.732047661
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.3789639434
Short name T213
Test name
Test status
Simulation time 466473206 ps
CPU time 4 seconds
Started Aug 21 08:23:02 AM UTC 24
Finished Aug 21 08:23:07 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3789639434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.3789639434
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.3730768544
Short name T199
Test name
Test status
Simulation time 128161502 ps
CPU time 1.98 seconds
Started Aug 21 08:23:03 AM UTC 24
Finished Aug 21 08:23:06 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3730768544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.3730768544
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.1845099778
Short name T212
Test name
Test status
Simulation time 1038714633 ps
CPU time 7.89 seconds
Started Aug 21 08:22:57 AM UTC 24
Finished Aug 21 08:23:06 AM UTC 24
Peak memory 226904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1845099778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.1845099778
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.494731332
Short name T367
Test name
Test status
Simulation time 14239052115 ps
CPU time 32.55 seconds
Started Aug 21 08:22:57 AM UTC 24
Finished Aug 21 08:23:31 AM UTC 24
Peak memory 936160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=494731332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.494731332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.1548436271
Short name T347
Test name
Test status
Simulation time 556625175 ps
CPU time 4.34 seconds
Started Aug 21 08:23:06 AM UTC 24
Finished Aug 21 08:23:11 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1548436271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 4.i2c_target_nack_acqfull.1548436271
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.4067835332
Short name T349
Test name
Test status
Simulation time 456818643 ps
CPU time 4.54 seconds
Started Aug 21 08:23:07 AM UTC 24
Finished Aug 21 08:23:13 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4067835332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_nack_acqfull_addr.4067835332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.1787919857
Short name T200
Test name
Test status
Simulation time 140458562 ps
CPU time 2.12 seconds
Started Aug 21 08:23:07 AM UTC 24
Finished Aug 21 08:23:10 AM UTC 24
Peak memory 233764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1787919857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_nack_txstretch.1787919857
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_perf.1797627647
Short name T342
Test name
Test status
Simulation time 632237915 ps
CPU time 7.05 seconds
Started Aug 21 08:22:59 AM UTC 24
Finished Aug 21 08:23:08 AM UTC 24
Peak memory 226856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1797627647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 4.i2c_target_perf.1797627647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.3296143444
Short name T348
Test name
Test status
Simulation time 548435926 ps
CPU time 4.42 seconds
Started Aug 21 08:23:06 AM UTC 24
Finished Aug 21 08:23:11 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3296143444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 4.i2c_target_smbus_maxlen.3296143444
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.3627383364
Short name T360
Test name
Test status
Simulation time 2027240232 ps
CPU time 31.08 seconds
Started Aug 21 08:22:55 AM UTC 24
Finished Aug 21 08:23:28 AM UTC 24
Peak memory 227084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3627383364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targe
t_smoke.3627383364
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.2082026453
Short name T631
Test name
Test status
Simulation time 45380959133 ps
CPU time 289.32 seconds
Started Aug 21 08:23:00 AM UTC 24
Finished Aug 21 08:27:53 AM UTC 24
Peak memory 2879452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2082026453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 4.i2c_target_stress_all.2082026453
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2668053016
Short name T352
Test name
Test status
Simulation time 5621984146 ps
CPU time 19.65 seconds
Started Aug 21 08:22:56 AM UTC 24
Finished Aug 21 08:23:17 AM UTC 24
Peak memory 246008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2668053016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stress_rd.2668053016
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.4276583393
Short name T62
Test name
Test status
Simulation time 55756984667 ps
CPU time 64.33 seconds
Started Aug 21 08:22:56 AM UTC 24
Finished Aug 21 08:24:02 AM UTC 24
Peak memory 1163616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4276583393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stress_wr.4276583393
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.3506662696
Short name T195
Test name
Test status
Simulation time 189312899 ps
CPU time 2.75 seconds
Started Aug 21 08:22:56 AM UTC 24
Finished Aug 21 08:23:00 AM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3506662696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_stretch.3506662696
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.1693343942
Short name T343
Test name
Test status
Simulation time 2730215520 ps
CPU time 9.51 seconds
Started Aug 21 08:22:57 AM UTC 24
Finished Aug 21 08:23:08 AM UTC 24
Peak memory 227144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1693343942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_timeout.1693343942
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.3816622791
Short name T351
Test name
Test status
Simulation time 567039984 ps
CPU time 9.96 seconds
Started Aug 21 08:23:05 AM UTC 24
Finished Aug 21 08:23:16 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3816622791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.3816622791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_alert_test.3102849579
Short name T1419
Test name
Test status
Simulation time 35827110 ps
CPU time 0.99 seconds
Started Aug 21 08:41:18 AM UTC 24
Finished Aug 21 08:41:19 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3102849579 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3102849579
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.881506717
Short name T1399
Test name
Test status
Simulation time 2617638657 ps
CPU time 6.64 seconds
Started Aug 21 08:40:48 AM UTC 24
Finished Aug 21 08:40:55 AM UTC 24
Peak memory 287204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=881506717 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.881506717
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.1690117294
Short name T1403
Test name
Test status
Simulation time 1325569995 ps
CPU time 19.37 seconds
Started Aug 21 08:40:45 AM UTC 24
Finished Aug 21 08:41:06 AM UTC 24
Peak memory 280676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1690117294 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.1690117294
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.2662446175
Short name T1456
Test name
Test status
Simulation time 8252225140 ps
CPU time 103.53 seconds
Started Aug 21 08:40:45 AM UTC 24
Finished Aug 21 08:42:31 AM UTC 24
Peak memory 448788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2662446175 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2662446175
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.3516220715
Short name T1453
Test name
Test status
Simulation time 11138712028 ps
CPU time 92.62 seconds
Started Aug 21 08:40:44 AM UTC 24
Finished Aug 21 08:42:19 AM UTC 24
Peak memory 897228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3516220715 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3516220715
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.878800668
Short name T1394
Test name
Test status
Simulation time 217173359 ps
CPU time 1.67 seconds
Started Aug 21 08:40:45 AM UTC 24
Finished Aug 21 08:40:48 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=878800668 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.878800668
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.2277032837
Short name T1396
Test name
Test status
Simulation time 1503473850 ps
CPU time 7.73 seconds
Started Aug 21 08:40:45 AM UTC 24
Finished Aug 21 08:40:54 AM UTC 24
Peak memory 249904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2277032837 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.2277032837
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.1681340984
Short name T1521
Test name
Test status
Simulation time 3951273148 ps
CPU time 221.24 seconds
Started Aug 21 08:40:44 AM UTC 24
Finished Aug 21 08:44:29 AM UTC 24
Peak memory 1151400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1681340984 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1681340984
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.2651389226
Short name T1416
Test name
Test status
Simulation time 494920588 ps
CPU time 5.05 seconds
Started Aug 21 08:41:11 AM UTC 24
Finished Aug 21 08:41:17 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2651389226 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2651389226
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_mode_toggle.2433831702
Short name T83
Test name
Test status
Simulation time 386186677 ps
CPU time 2.23 seconds
Started Aug 21 08:41:10 AM UTC 24
Finished Aug 21 08:41:13 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2433831702 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.2433831702
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_override.2454122627
Short name T1390
Test name
Test status
Simulation time 19360653 ps
CPU time 1.03 seconds
Started Aug 21 08:40:44 AM UTC 24
Finished Aug 21 08:40:46 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2454122627 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2454122627
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_perf.287210284
Short name T1470
Test name
Test status
Simulation time 27273265284 ps
CPU time 124.57 seconds
Started Aug 21 08:40:46 AM UTC 24
Finished Aug 21 08:42:53 AM UTC 24
Peak memory 784616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=287210284 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.287210284
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.2217571011
Short name T1407
Test name
Test status
Simulation time 2929463217 ps
CPU time 36.96 seconds
Started Aug 21 08:40:46 AM UTC 24
Finished Aug 21 08:41:25 AM UTC 24
Peak memory 358612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2217571011 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.2217571011
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.2421626713
Short name T1426
Test name
Test status
Simulation time 3969045570 ps
CPU time 40 seconds
Started Aug 21 08:40:44 AM UTC 24
Finished Aug 21 08:41:25 AM UTC 24
Peak memory 397600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2421626713 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2421626713
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_stress_all.845741815
Short name T301
Test name
Test status
Simulation time 42799623874 ps
CPU time 930.01 seconds
Started Aug 21 08:40:49 AM UTC 24
Finished Aug 21 08:56:29 AM UTC 24
Peak memory 2222472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=845741815 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.845741815
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.82638259
Short name T1415
Test name
Test status
Simulation time 782085339 ps
CPU time 37.07 seconds
Started Aug 21 08:40:46 AM UTC 24
Finished Aug 21 08:41:25 AM UTC 24
Peak memory 226884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=82638259 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.82638259
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.121071179
Short name T1421
Test name
Test status
Simulation time 5052115029 ps
CPU time 9.38 seconds
Started Aug 21 08:41:10 AM UTC 24
Finished Aug 21 08:41:20 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=121071179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_bad_addr.121071179
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.1245146469
Short name T1409
Test name
Test status
Simulation time 588085767 ps
CPU time 2.49 seconds
Started Aug 21 08:41:06 AM UTC 24
Finished Aug 21 08:41:10 AM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1245146469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_acq.1245146469
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.2615517236
Short name T1408
Test name
Test status
Simulation time 177524988 ps
CPU time 1.9 seconds
Started Aug 21 08:41:06 AM UTC 24
Finished Aug 21 08:41:09 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2615517236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_fifo_reset_tx.2615517236
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.3363059306
Short name T1413
Test name
Test status
Simulation time 280434136 ps
CPU time 2.25 seconds
Started Aug 21 08:41:12 AM UTC 24
Finished Aug 21 08:41:15 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3363059306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.3363059306
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.2570866118
Short name T1414
Test name
Test status
Simulation time 162329383 ps
CPU time 1.61 seconds
Started Aug 21 08:41:14 AM UTC 24
Finished Aug 21 08:41:17 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2570866118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.2570866118
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.3456823727
Short name T1404
Test name
Test status
Simulation time 2137358073 ps
CPU time 9.53 seconds
Started Aug 21 08:40:56 AM UTC 24
Finished Aug 21 08:41:07 AM UTC 24
Peak memory 228824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3456823727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.3456823727
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.3310396774
Short name T1438
Test name
Test status
Simulation time 12255563802 ps
CPU time 65.92 seconds
Started Aug 21 08:40:56 AM UTC 24
Finished Aug 21 08:42:04 AM UTC 24
Peak memory 1482924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3310396774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.3310396774
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.2945247804
Short name T1425
Test name
Test status
Simulation time 592084198 ps
CPU time 5.59 seconds
Started Aug 21 08:41:16 AM UTC 24
Finished Aug 21 08:41:23 AM UTC 24
Peak memory 227136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2945247804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 40.i2c_target_nack_acqfull.2945247804
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.1909410023
Short name T1377
Test name
Test status
Simulation time 945440423 ps
CPU time 3.25 seconds
Started Aug 21 08:41:17 AM UTC 24
Finished Aug 21 08:41:22 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1909410023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_nack_acqfull_addr.1909410023
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_nack_txstretch.3813575319
Short name T1422
Test name
Test status
Simulation time 125275987 ps
CPU time 2.1 seconds
Started Aug 21 08:41:18 AM UTC 24
Finished Aug 21 08:41:21 AM UTC 24
Peak memory 233272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3813575319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_nack_txstretch.3813575319
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_perf.1098169461
Short name T1412
Test name
Test status
Simulation time 850797602 ps
CPU time 5.44 seconds
Started Aug 21 08:41:08 AM UTC 24
Finished Aug 21 08:41:14 AM UTC 24
Peak memory 232976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1098169461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 40.i2c_target_perf.1098169461
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.835410061
Short name T1418
Test name
Test status
Simulation time 1079150373 ps
CPU time 2.85 seconds
Started Aug 21 08:41:15 AM UTC 24
Finished Aug 21 08:41:19 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=835410061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 40.i2c_target_smbus_maxlen.835410061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.3833451106
Short name T1417
Test name
Test status
Simulation time 962369375 ps
CPU time 28.36 seconds
Started Aug 21 08:40:49 AM UTC 24
Finished Aug 21 08:41:18 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3833451106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_targ
et_smoke.3833451106
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.884308191
Short name T1519
Test name
Test status
Simulation time 24583338269 ps
CPU time 195.59 seconds
Started Aug 21 08:41:10 AM UTC 24
Finished Aug 21 08:44:28 AM UTC 24
Peak memory 1931484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=884308191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.i2c_target_stress_all.884308191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.3496880335
Short name T1401
Test name
Test status
Simulation time 2562654533 ps
CPU time 9.2 seconds
Started Aug 21 08:40:55 AM UTC 24
Finished Aug 21 08:41:05 AM UTC 24
Peak memory 223076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3496880335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stress_rd.3496880335
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.32278061
Short name T1699
Test name
Test status
Simulation time 45313618109 ps
CPU time 412.16 seconds
Started Aug 21 08:40:50 AM UTC 24
Finished Aug 21 08:47:47 AM UTC 24
Peak memory 5095844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=32278061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_stress_wr.32278061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_stretch.1125845988
Short name T1378
Test name
Test status
Simulation time 3552614913 ps
CPU time 26.08 seconds
Started Aug 21 08:40:56 AM UTC 24
Finished Aug 21 08:41:23 AM UTC 24
Peak memory 588108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1125845988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_stretch.1125845988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.838591424
Short name T1410
Test name
Test status
Simulation time 5382196747 ps
CPU time 8.86 seconds
Started Aug 21 08:41:01 AM UTC 24
Finished Aug 21 08:41:11 AM UTC 24
Peak memory 227152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=838591424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_timeout.838591424
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/40.i2c_target_tx_stretch_ctrl.2271596591
Short name T1420
Test name
Test status
Simulation time 138672822 ps
CPU time 4.7 seconds
Started Aug 21 08:41:14 AM UTC 24
Finished Aug 21 08:41:20 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2271596591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.2271596591
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_alert_test.2924810274
Short name T1442
Test name
Test status
Simulation time 17128790 ps
CPU time 0.94 seconds
Started Aug 21 08:42:05 AM UTC 24
Finished Aug 21 08:42:07 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2924810274 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2924810274
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.38027974
Short name T1221
Test name
Test status
Simulation time 2070911182 ps
CPU time 10.83 seconds
Started Aug 21 08:41:22 AM UTC 24
Finished Aug 21 08:41:34 AM UTC 24
Peak memory 327752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38027974 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty.38027974
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.3444138068
Short name T1446
Test name
Test status
Simulation time 2692113460 ps
CPU time 45.95 seconds
Started Aug 21 08:41:22 AM UTC 24
Finished Aug 21 08:42:10 AM UTC 24
Peak memory 360912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3444138068 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3444138068
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.898499085
Short name T1471
Test name
Test status
Simulation time 2619345470 ps
CPU time 91.89 seconds
Started Aug 21 08:41:21 AM UTC 24
Finished Aug 21 08:42:55 AM UTC 24
Peak memory 868456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=898499085 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.898499085
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.248477424
Short name T1372
Test name
Test status
Simulation time 502050279 ps
CPU time 2.17 seconds
Started Aug 21 08:41:21 AM UTC 24
Finished Aug 21 08:41:24 AM UTC 24
Peak memory 216848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=248477424 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.248477424
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.642318489
Short name T1301
Test name
Test status
Simulation time 190812572 ps
CPU time 5.35 seconds
Started Aug 21 08:41:22 AM UTC 24
Finished Aug 21 08:41:28 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=642318489 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.642318489
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.2983527006
Short name T1489
Test name
Test status
Simulation time 4168055067 ps
CPU time 105.87 seconds
Started Aug 21 08:41:21 AM UTC 24
Finished Aug 21 08:43:09 AM UTC 24
Peak memory 1153172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2983527006 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2983527006
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.613226758
Short name T1448
Test name
Test status
Simulation time 1028992874 ps
CPU time 14.46 seconds
Started Aug 21 08:41:57 AM UTC 24
Finished Aug 21 08:42:12 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=613226758 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.613226758
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_override.3802576227
Short name T1424
Test name
Test status
Simulation time 44942429 ps
CPU time 0.99 seconds
Started Aug 21 08:41:20 AM UTC 24
Finished Aug 21 08:41:22 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802576227 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3802576227
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_perf.2443570969
Short name T1746
Test name
Test status
Simulation time 72601090919 ps
CPU time 1523.08 seconds
Started Aug 21 08:41:23 AM UTC 24
Finished Aug 21 09:07:02 AM UTC 24
Peak memory 3328164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2443570969 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2443570969
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.753113893
Short name T1231
Test name
Test status
Simulation time 2008548067 ps
CPU time 10.08 seconds
Started Aug 21 08:41:24 AM UTC 24
Finished Aug 21 08:41:36 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=753113893 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.753113893
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.1477515094
Short name T1454
Test name
Test status
Simulation time 2457804785 ps
CPU time 60.43 seconds
Started Aug 21 08:41:19 AM UTC 24
Finished Aug 21 08:42:21 AM UTC 24
Peak memory 518408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1477515094 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1477515094
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_stress_all.966058939
Short name T142
Test name
Test status
Simulation time 13283601774 ps
CPU time 455.13 seconds
Started Aug 21 08:41:25 AM UTC 24
Finished Aug 21 08:49:06 AM UTC 24
Peak memory 1613992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=966058939 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.966058939
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.675780877
Short name T1433
Test name
Test status
Simulation time 1096700027 ps
CPU time 31.66 seconds
Started Aug 21 08:41:24 AM UTC 24
Finished Aug 21 08:41:57 AM UTC 24
Peak memory 227136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=675780877 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.675780877
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.177694789
Short name T1431
Test name
Test status
Simulation time 1765693946 ps
CPU time 7.4 seconds
Started Aug 21 08:41:48 AM UTC 24
Finished Aug 21 08:41:56 AM UTC 24
Peak memory 233028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=177694789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_bad_addr.177694789
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.1236753861
Short name T1427
Test name
Test status
Simulation time 192167423 ps
CPU time 2.12 seconds
Started Aug 21 08:41:41 AM UTC 24
Finished Aug 21 08:41:45 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1236753861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_acq.1236753861
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.518443814
Short name T1428
Test name
Test status
Simulation time 202490381 ps
CPU time 1.42 seconds
Started Aug 21 08:41:44 AM UTC 24
Finished Aug 21 08:41:47 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=518443814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 41.i2c_target_fifo_reset_tx.518443814
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.3752210640
Short name T1437
Test name
Test status
Simulation time 388279744 ps
CPU time 3.09 seconds
Started Aug 21 08:41:58 AM UTC 24
Finished Aug 21 08:42:02 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3752210640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.3752210640
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_tx.3282910823
Short name T1434
Test name
Test status
Simulation time 1516255396 ps
CPU time 2.16 seconds
Started Aug 21 08:41:58 AM UTC 24
Finished Aug 21 08:42:01 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3282910823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.3282910823
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.252757486
Short name T1271
Test name
Test status
Simulation time 1350265427 ps
CPU time 7.97 seconds
Started Aug 21 08:41:35 AM UTC 24
Finished Aug 21 08:41:44 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=252757486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 41.i2c_target_intr_smoke.252757486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.1104944646
Short name T1473
Test name
Test status
Simulation time 12752567491 ps
CPU time 78.51 seconds
Started Aug 21 08:41:35 AM UTC 24
Finished Aug 21 08:42:55 AM UTC 24
Peak memory 1493172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1104944646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.1104944646
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.3889500129
Short name T1444
Test name
Test status
Simulation time 3844722902 ps
CPU time 4.38 seconds
Started Aug 21 08:42:02 AM UTC 24
Finished Aug 21 08:42:08 AM UTC 24
Peak memory 226960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3889500129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 41.i2c_target_nack_acqfull.3889500129
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.286848051
Short name T1441
Test name
Test status
Simulation time 733060462 ps
CPU time 2.79 seconds
Started Aug 21 08:42:03 AM UTC 24
Finished Aug 21 08:42:07 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=286848051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_nack_acqfull_addr.286848051
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.3889178005
Short name T1443
Test name
Test status
Simulation time 142171978 ps
CPU time 2.08 seconds
Started Aug 21 08:42:04 AM UTC 24
Finished Aug 21 08:42:08 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3889178005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_nack_txstretch.3889178005
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_perf.4271044899
Short name T1430
Test name
Test status
Simulation time 8745135454 ps
CPU time 7.18 seconds
Started Aug 21 08:41:45 AM UTC 24
Finished Aug 21 08:41:54 AM UTC 24
Peak memory 233748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4271044899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 41.i2c_target_perf.4271044899
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.4140682655
Short name T1440
Test name
Test status
Simulation time 1584061268 ps
CPU time 3.24 seconds
Started Aug 21 08:42:02 AM UTC 24
Finished Aug 21 08:42:06 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4140682655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 41.i2c_target_smbus_maxlen.4140682655
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.215701689
Short name T1436
Test name
Test status
Simulation time 4023609146 ps
CPU time 34.51 seconds
Started Aug 21 08:41:26 AM UTC 24
Finished Aug 21 08:42:02 AM UTC 24
Peak memory 231360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=215701689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_targe
t_smoke.215701689
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.3659066059
Short name T1463
Test name
Test status
Simulation time 59510627106 ps
CPU time 54.08 seconds
Started Aug 21 08:41:45 AM UTC 24
Finished Aug 21 08:42:41 AM UTC 24
Peak memory 495904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3659066059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 41.i2c_target_stress_all.3659066059
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.1174543333
Short name T1439
Test name
Test status
Simulation time 1644137602 ps
CPU time 33.21 seconds
Started Aug 21 08:41:30 AM UTC 24
Finished Aug 21 08:42:05 AM UTC 24
Peak memory 244048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1174543333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stress_rd.1174543333
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.2750108629
Short name T1744
Test name
Test status
Simulation time 60258253521 ps
CPU time 1059.07 seconds
Started Aug 21 08:41:27 AM UTC 24
Finished Aug 21 08:59:17 AM UTC 24
Peak memory 9906592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2750108629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stress_wr.2750108629
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.1969470767
Short name T1199
Test name
Test status
Simulation time 1335036755 ps
CPU time 2.81 seconds
Started Aug 21 08:41:30 AM UTC 24
Finished Aug 21 08:41:34 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1969470767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_stretch.1969470767
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.307803612
Short name T1429
Test name
Test status
Simulation time 5375817598 ps
CPU time 11.43 seconds
Started Aug 21 08:41:36 AM UTC 24
Finished Aug 21 08:41:49 AM UTC 24
Peak memory 226948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=307803612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_timeout.307803612
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/41.i2c_target_tx_stretch_ctrl.741536581
Short name T1449
Test name
Test status
Simulation time 745206937 ps
CPU time 10.53 seconds
Started Aug 21 08:42:02 AM UTC 24
Finished Aug 21 08:42:14 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=741536581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_tx_stretch_ctrl.741536581
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_alert_test.662146918
Short name T1480
Test name
Test status
Simulation time 90835234 ps
CPU time 0.92 seconds
Started Aug 21 08:42:57 AM UTC 24
Finished Aug 21 08:42:59 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=662146918 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.662146918
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.3821367860
Short name T1455
Test name
Test status
Simulation time 273985112 ps
CPU time 2.46 seconds
Started Aug 21 08:42:18 AM UTC 24
Finished Aug 21 08:42:22 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3821367860 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3821367860
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.231939526
Short name T1459
Test name
Test status
Simulation time 664418438 ps
CPU time 20.89 seconds
Started Aug 21 08:42:11 AM UTC 24
Finished Aug 21 08:42:33 AM UTC 24
Peak memory 286848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231939526 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty.231939526
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.1331339046
Short name T1538
Test name
Test status
Simulation time 3045555788 ps
CPU time 162.79 seconds
Started Aug 21 08:42:12 AM UTC 24
Finished Aug 21 08:44:57 AM UTC 24
Peak memory 755976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1331339046 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1331339046
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.3163114973
Short name T1560
Test name
Test status
Simulation time 2701079848 ps
CPU time 181.43 seconds
Started Aug 21 08:42:09 AM UTC 24
Finished Aug 21 08:45:13 AM UTC 24
Peak memory 870820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3163114973 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3163114973
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.2908496755
Short name T1447
Test name
Test status
Simulation time 329261354 ps
CPU time 1.34 seconds
Started Aug 21 08:42:09 AM UTC 24
Finished Aug 21 08:42:11 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2908496755 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt.2908496755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.660887010
Short name T1452
Test name
Test status
Simulation time 153981197 ps
CPU time 5.42 seconds
Started Aug 21 08:42:11 AM UTC 24
Finished Aug 21 08:42:17 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=660887010 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.660887010
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.3432542121
Short name T1552
Test name
Test status
Simulation time 12026459679 ps
CPU time 172.88 seconds
Started Aug 21 08:42:09 AM UTC 24
Finished Aug 21 08:45:04 AM UTC 24
Peak memory 985408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3432542121 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3432542121
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.1452777969
Short name T1474
Test name
Test status
Simulation time 733538057 ps
CPU time 6.12 seconds
Started Aug 21 08:42:49 AM UTC 24
Finished Aug 21 08:42:56 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1452777969 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.1452777969
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_mode_toggle.977930237
Short name T1467
Test name
Test status
Simulation time 342059679 ps
CPU time 2.32 seconds
Started Aug 21 08:42:48 AM UTC 24
Finished Aug 21 08:42:51 AM UTC 24
Peak memory 229172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=977930237 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.977930237
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_override.550393473
Short name T1445
Test name
Test status
Simulation time 27246694 ps
CPU time 1.01 seconds
Started Aug 21 08:42:08 AM UTC 24
Finished Aug 21 08:42:10 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=550393473 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.550393473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_perf.2934210527
Short name T1716
Test name
Test status
Simulation time 50667360141 ps
CPU time 539.5 seconds
Started Aug 21 08:42:13 AM UTC 24
Finished Aug 21 08:51:19 AM UTC 24
Peak memory 227068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2934210527 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2934210527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.3727217587
Short name T1451
Test name
Test status
Simulation time 280709463 ps
CPU time 2.11 seconds
Started Aug 21 08:42:14 AM UTC 24
Finished Aug 21 08:42:17 AM UTC 24
Peak memory 228764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3727217587 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.3727217587
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.1027405468
Short name T1487
Test name
Test status
Simulation time 2297154619 ps
CPU time 58.84 seconds
Started Aug 21 08:42:08 AM UTC 24
Finished Aug 21 08:43:08 AM UTC 24
Peak memory 299288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1027405468 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1027405468
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.1920733280
Short name T1457
Test name
Test status
Simulation time 658305338 ps
CPU time 13.72 seconds
Started Aug 21 08:42:17 AM UTC 24
Finished Aug 21 08:42:32 AM UTC 24
Peak memory 230964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1920733280 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1920733280
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.854500381
Short name T1468
Test name
Test status
Simulation time 902755449 ps
CPU time 7.6 seconds
Started Aug 21 08:42:42 AM UTC 24
Finished Aug 21 08:42:51 AM UTC 24
Peak memory 233616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=854500381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_bad_addr.854500381
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.601589350
Short name T1461
Test name
Test status
Simulation time 401695330 ps
CPU time 2.33 seconds
Started Aug 21 08:42:35 AM UTC 24
Finished Aug 21 08:42:38 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=601589350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_fifo_reset_acq.601589350
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.498262707
Short name T1462
Test name
Test status
Simulation time 304569166 ps
CPU time 1.94 seconds
Started Aug 21 08:42:37 AM UTC 24
Finished Aug 21 08:42:40 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=498262707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 42.i2c_target_fifo_reset_tx.498262707
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.1744832134
Short name T1475
Test name
Test status
Simulation time 452158255 ps
CPU time 3.61 seconds
Started Aug 21 08:42:52 AM UTC 24
Finished Aug 21 08:42:56 AM UTC 24
Peak memory 215988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1744832134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.1744832134
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.901970774
Short name T1472
Test name
Test status
Simulation time 130094174 ps
CPU time 2.06 seconds
Started Aug 21 08:42:52 AM UTC 24
Finished Aug 21 08:42:55 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=901970774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.901970774
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_hrst.1117552091
Short name T1469
Test name
Test status
Simulation time 374545811 ps
CPU time 4.07 seconds
Started Aug 21 08:42:47 AM UTC 24
Finished Aug 21 08:42:52 AM UTC 24
Peak memory 227080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1117552091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 42.i2c_target_hrst.1117552091
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.4069352664
Short name T1464
Test name
Test status
Simulation time 1308426882 ps
CPU time 12.36 seconds
Started Aug 21 08:42:32 AM UTC 24
Finished Aug 21 08:42:46 AM UTC 24
Peak memory 233328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=4069352664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.4069352664
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.1525429340
Short name T1618
Test name
Test status
Simulation time 17793437962 ps
CPU time 223.5 seconds
Started Aug 21 08:42:33 AM UTC 24
Finished Aug 21 08:46:20 AM UTC 24
Peak memory 2959796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1525429340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1525429340
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.2198567269
Short name T1484
Test name
Test status
Simulation time 2015493082 ps
CPU time 4.86 seconds
Started Aug 21 08:42:56 AM UTC 24
Finished Aug 21 08:43:02 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2198567269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 42.i2c_target_nack_acqfull.2198567269
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.875820542
Short name T1483
Test name
Test status
Simulation time 2145189142 ps
CPU time 3.04 seconds
Started Aug 21 08:42:56 AM UTC 24
Finished Aug 21 08:43:00 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=875820542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_nack_acqfull_addr.875820542
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_perf.2196851579
Short name T1465
Test name
Test status
Simulation time 555617366 ps
CPU time 6.5 seconds
Started Aug 21 08:42:39 AM UTC 24
Finished Aug 21 08:42:47 AM UTC 24
Peak memory 228880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2196851579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 42.i2c_target_perf.2196851579
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.996474813
Short name T1479
Test name
Test status
Simulation time 1829969845 ps
CPU time 3.37 seconds
Started Aug 21 08:42:54 AM UTC 24
Finished Aug 21 08:42:58 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=996474813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 42.i2c_target_smbus_maxlen.996474813
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.1570779417
Short name T1460
Test name
Test status
Simulation time 3557313564 ps
CPU time 13.18 seconds
Started Aug 21 08:42:19 AM UTC 24
Finished Aug 21 08:42:34 AM UTC 24
Peak memory 233724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1570779417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_targ
et_smoke.1570779417
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.1098267135
Short name T1529
Test name
Test status
Simulation time 36756493039 ps
CPU time 124.26 seconds
Started Aug 21 08:42:41 AM UTC 24
Finished Aug 21 08:44:48 AM UTC 24
Peak memory 1538332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1098267135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 42.i2c_target_stress_all.1098267135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.2476870018
Short name T1478
Test name
Test status
Simulation time 2920360981 ps
CPU time 33.4 seconds
Started Aug 21 08:42:23 AM UTC 24
Finished Aug 21 08:42:57 AM UTC 24
Peak memory 250068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2476870018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stress_rd.2476870018
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.134329511
Short name T1540
Test name
Test status
Simulation time 54684632656 ps
CPU time 154.06 seconds
Started Aug 21 08:42:22 AM UTC 24
Finished Aug 21 08:44:58 AM UTC 24
Peak memory 2328732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=134329511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_t
arget_stress_wr.134329511
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.1618255501
Short name T1466
Test name
Test status
Simulation time 2406488276 ps
CPU time 12.59 seconds
Started Aug 21 08:42:34 AM UTC 24
Finished Aug 21 08:42:48 AM UTC 24
Peak memory 231040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1618255501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_timeout.1618255501
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.2925213028
Short name T1476
Test name
Test status
Simulation time 90272903 ps
CPU time 3.05 seconds
Started Aug 21 08:42:53 AM UTC 24
Finished Aug 21 08:42:57 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2925213028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.2925213028
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_alert_test.3387321007
Short name T1511
Test name
Test status
Simulation time 28099296 ps
CPU time 0.98 seconds
Started Aug 21 08:43:56 AM UTC 24
Finished Aug 21 08:43:58 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3387321007 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3387321007
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.3249215445
Short name T1490
Test name
Test status
Simulation time 217448348 ps
CPU time 2.85 seconds
Started Aug 21 08:43:06 AM UTC 24
Finished Aug 21 08:43:10 AM UTC 24
Peak memory 227144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3249215445 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.3249215445
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.3476951726
Short name T1491
Test name
Test status
Simulation time 406580420 ps
CPU time 12.7 seconds
Started Aug 21 08:43:00 AM UTC 24
Finished Aug 21 08:43:14 AM UTC 24
Peak memory 307276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3476951726 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty.3476951726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.3600715894
Short name T1526
Test name
Test status
Simulation time 3420942644 ps
CPU time 95.94 seconds
Started Aug 21 08:43:01 AM UTC 24
Finished Aug 21 08:44:39 AM UTC 24
Peak memory 649424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3600715894 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3600715894
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.3380949496
Short name T1562
Test name
Test status
Simulation time 2140370270 ps
CPU time 135.71 seconds
Started Aug 21 08:42:59 AM UTC 24
Finished Aug 21 08:45:17 AM UTC 24
Peak memory 710624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3380949496 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3380949496
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.3555490118
Short name T1485
Test name
Test status
Simulation time 121005170 ps
CPU time 1.74 seconds
Started Aug 21 08:43:00 AM UTC 24
Finished Aug 21 08:43:03 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3555490118 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fmt.3555490118
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.2982432579
Short name T1488
Test name
Test status
Simulation time 453087952 ps
CPU time 7.6 seconds
Started Aug 21 08:43:00 AM UTC 24
Finished Aug 21 08:43:09 AM UTC 24
Peak memory 256340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2982432579 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.2982432579
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.3524523243
Short name T1674
Test name
Test status
Simulation time 8303257374 ps
CPU time 260.81 seconds
Started Aug 21 08:42:59 AM UTC 24
Finished Aug 21 08:47:23 AM UTC 24
Peak memory 1237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3524523243 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3524523243
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.2233351503
Short name T1458
Test name
Test status
Simulation time 808573933 ps
CPU time 7.73 seconds
Started Aug 21 08:43:42 AM UTC 24
Finished Aug 21 08:43:50 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2233351503 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2233351503
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_override.2068308938
Short name T1481
Test name
Test status
Simulation time 18690610 ps
CPU time 0.9 seconds
Started Aug 21 08:42:57 AM UTC 24
Finished Aug 21 08:42:59 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2068308938 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2068308938
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_perf.4203858869
Short name T1503
Test name
Test status
Simulation time 2757740210 ps
CPU time 39.6 seconds
Started Aug 21 08:43:01 AM UTC 24
Finished Aug 21 08:43:42 AM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4203858869 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.4203858869
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_perf_precise.429432755
Short name T1486
Test name
Test status
Simulation time 147642520 ps
CPU time 1.65 seconds
Started Aug 21 08:43:03 AM UTC 24
Finished Aug 21 08:43:06 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=429432755 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.429432755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.281225407
Short name T1520
Test name
Test status
Simulation time 1632787084 ps
CPU time 89.12 seconds
Started Aug 21 08:42:57 AM UTC 24
Finished Aug 21 08:44:28 AM UTC 24
Peak memory 397464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=281225407 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.281225407
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_stress_all.1600954088
Short name T1732
Test name
Test status
Simulation time 44564260999 ps
CPU time 433.61 seconds
Started Aug 21 08:43:09 AM UTC 24
Finished Aug 21 08:50:28 AM UTC 24
Peak memory 1913064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1600954088 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.1600954088
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.1548107510
Short name T1492
Test name
Test status
Simulation time 3795126817 ps
CPU time 12.99 seconds
Started Aug 21 08:43:03 AM UTC 24
Finished Aug 21 08:43:17 AM UTC 24
Peak memory 233720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1548107510 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1548107510
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.244855951
Short name T1432
Test name
Test status
Simulation time 1037675339 ps
CPU time 11.16 seconds
Started Aug 21 08:43:36 AM UTC 24
Finished Aug 21 08:43:49 AM UTC 24
Peak memory 233504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=244855951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_bad_addr.244855951
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.4074135745
Short name T1498
Test name
Test status
Simulation time 233977827 ps
CPU time 2.55 seconds
Started Aug 21 08:43:27 AM UTC 24
Finished Aug 21 08:43:31 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4074135745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_acq.4074135745
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.181859279
Short name T1500
Test name
Test status
Simulation time 253510114 ps
CPU time 2.86 seconds
Started Aug 21 08:43:31 AM UTC 24
Finished Aug 21 08:43:35 AM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=181859279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_target_fifo_reset_tx.181859279
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.679258867
Short name T1482
Test name
Test status
Simulation time 418295885 ps
CPU time 4.16 seconds
Started Aug 21 08:43:43 AM UTC 24
Finished Aug 21 08:43:48 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=679258867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.679258867
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.898662108
Short name T1505
Test name
Test status
Simulation time 519127113 ps
CPU time 2.19 seconds
Started Aug 21 08:43:44 AM UTC 24
Finished Aug 21 08:43:47 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=898662108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.898662108
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_hrst.3143975253
Short name T1504
Test name
Test status
Simulation time 736666220 ps
CPU time 3.7 seconds
Started Aug 21 08:43:37 AM UTC 24
Finished Aug 21 08:43:43 AM UTC 24
Peak memory 233760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3143975253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 43.i2c_target_hrst.3143975253
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.2980134447
Short name T1495
Test name
Test status
Simulation time 777554487 ps
CPU time 7.32 seconds
Started Aug 21 08:43:18 AM UTC 24
Finished Aug 21 08:43:26 AM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2980134447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_intr_smoke.2980134447
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.2836217762
Short name T1496
Test name
Test status
Simulation time 327630248 ps
CPU time 3.56 seconds
Started Aug 21 08:43:22 AM UTC 24
Finished Aug 21 08:43:27 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2836217762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2836217762
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.1961078369
Short name T1507
Test name
Test status
Simulation time 464589752 ps
CPU time 4.33 seconds
Started Aug 21 08:43:50 AM UTC 24
Finished Aug 21 08:43:56 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1961078369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_target_nack_acqfull.1961078369
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.3874794565
Short name T1509
Test name
Test status
Simulation time 1028451958 ps
CPU time 4.67 seconds
Started Aug 21 08:43:51 AM UTC 24
Finished Aug 21 08:43:57 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3874794565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_nack_acqfull_addr.3874794565
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_nack_txstretch.3809907012
Short name T1510
Test name
Test status
Simulation time 500797887 ps
CPU time 2.14 seconds
Started Aug 21 08:43:54 AM UTC 24
Finished Aug 21 08:43:58 AM UTC 24
Peak memory 233496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3809907012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_nack_txstretch.3809907012
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_perf.3485177762
Short name T1501
Test name
Test status
Simulation time 512356098 ps
CPU time 3.52 seconds
Started Aug 21 08:43:31 AM UTC 24
Finished Aug 21 08:43:36 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3485177762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 43.i2c_target_perf.3485177762
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.3807957155
Short name T1506
Test name
Test status
Simulation time 354753904 ps
CPU time 3.24 seconds
Started Aug 21 08:43:49 AM UTC 24
Finished Aug 21 08:43:54 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3807957155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 43.i2c_target_smbus_maxlen.3807957155
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.1669577912
Short name T1494
Test name
Test status
Simulation time 2512665649 ps
CPU time 14.8 seconds
Started Aug 21 08:43:09 AM UTC 24
Finished Aug 21 08:43:25 AM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1669577912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_targ
et_smoke.1669577912
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.3592936245
Short name T1533
Test name
Test status
Simulation time 7866181095 ps
CPU time 76.13 seconds
Started Aug 21 08:43:33 AM UTC 24
Finished Aug 21 08:44:51 AM UTC 24
Peak memory 323764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3592936245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 43.i2c_target_stress_all.3592936245
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.1511180524
Short name T1499
Test name
Test status
Simulation time 996893345 ps
CPU time 20.99 seconds
Started Aug 21 08:43:10 AM UTC 24
Finished Aug 21 08:43:33 AM UTC 24
Peak memory 232956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1511180524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stress_rd.1511180524
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.3692628624
Short name T1683
Test name
Test status
Simulation time 67955050020 ps
CPU time 256.09 seconds
Started Aug 21 08:43:09 AM UTC 24
Finished Aug 21 08:47:29 AM UTC 24
Peak memory 2996448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3692628624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stress_wr.3692628624
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_stretch.1736712078
Short name T1493
Test name
Test status
Simulation time 744307163 ps
CPU time 5.47 seconds
Started Aug 21 08:43:15 AM UTC 24
Finished Aug 21 08:43:21 AM UTC 24
Peak memory 260064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1736712078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_stretch.1736712078
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.2491188777
Short name T1502
Test name
Test status
Simulation time 1030630170 ps
CPU time 9.37 seconds
Started Aug 21 08:43:26 AM UTC 24
Finished Aug 21 08:43:36 AM UTC 24
Peak memory 233512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2491188777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_timeout.2491188777
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.3627208259
Short name T1508
Test name
Test status
Simulation time 265071250 ps
CPU time 6.87 seconds
Started Aug 21 08:43:48 AM UTC 24
Finished Aug 21 08:43:56 AM UTC 24
Peak memory 216792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3627208259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.3627208259
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_alert_test.3187457945
Short name T1544
Test name
Test status
Simulation time 46299783 ps
CPU time 0.86 seconds
Started Aug 21 08:44:59 AM UTC 24
Finished Aug 21 08:45:01 AM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3187457945 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3187457945
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_error_intr.2136177973
Short name T1523
Test name
Test status
Simulation time 74817644 ps
CPU time 2 seconds
Started Aug 21 08:44:29 AM UTC 24
Finished Aug 21 08:44:32 AM UTC 24
Peak memory 226328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2136177973 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2136177973
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.3885060745
Short name T1516
Test name
Test status
Simulation time 651824747 ps
CPU time 9.74 seconds
Started Aug 21 08:44:02 AM UTC 24
Finished Aug 21 08:44:13 AM UTC 24
Peak memory 241700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3885060745 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty.3885060745
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.1276087082
Short name T1593
Test name
Test status
Simulation time 3014439801 ps
CPU time 103.1 seconds
Started Aug 21 08:44:12 AM UTC 24
Finished Aug 21 08:45:57 AM UTC 24
Peak memory 856268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1276087082 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1276087082
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.171471819
Short name T1547
Test name
Test status
Simulation time 1496737396 ps
CPU time 60.07 seconds
Started Aug 21 08:44:00 AM UTC 24
Finished Aug 21 08:45:01 AM UTC 24
Peak memory 596076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=171471819 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.171471819
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.1487770738
Short name T1514
Test name
Test status
Simulation time 315267068 ps
CPU time 1.49 seconds
Started Aug 21 08:44:02 AM UTC 24
Finished Aug 21 08:44:04 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1487770738 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.1487770738
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.1908319836
Short name T1515
Test name
Test status
Simulation time 627161142 ps
CPU time 4.76 seconds
Started Aug 21 08:44:05 AM UTC 24
Finished Aug 21 08:44:11 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1908319836 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.1908319836
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.4214505095
Short name T1602
Test name
Test status
Simulation time 2452574427 ps
CPU time 129 seconds
Started Aug 21 08:43:58 AM UTC 24
Finished Aug 21 08:46:10 AM UTC 24
Peak memory 827600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4214505095 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.4214505095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.3303836149
Short name T1554
Test name
Test status
Simulation time 294236358 ps
CPU time 11.87 seconds
Started Aug 21 08:44:52 AM UTC 24
Finished Aug 21 08:45:05 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3303836149 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3303836149
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_mode_toggle.3274379357
Short name T289
Test name
Test status
Simulation time 373001577 ps
CPU time 3.96 seconds
Started Aug 21 08:44:52 AM UTC 24
Finished Aug 21 08:44:57 AM UTC 24
Peak memory 232992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3274379357 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3274379357
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_override.3091031198
Short name T1513
Test name
Test status
Simulation time 47177622 ps
CPU time 0.96 seconds
Started Aug 21 08:43:58 AM UTC 24
Finished Aug 21 08:44:00 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3091031198 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3091031198
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_perf.1406924667
Short name T1691
Test name
Test status
Simulation time 53095318058 ps
CPU time 201.47 seconds
Started Aug 21 08:44:13 AM UTC 24
Finished Aug 21 08:47:37 AM UTC 24
Peak memory 774284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1406924667 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1406924667
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.2557278242
Short name T1518
Test name
Test status
Simulation time 1539683984 ps
CPU time 10.12 seconds
Started Aug 21 08:44:17 AM UTC 24
Finished Aug 21 08:44:28 AM UTC 24
Peak memory 260180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2557278242 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.2557278242
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.3162506938
Short name T1531
Test name
Test status
Simulation time 891487547 ps
CPU time 50.85 seconds
Started Aug 21 08:43:56 AM UTC 24
Finished Aug 21 08:44:49 AM UTC 24
Peak memory 313556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3162506938 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3162506938
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.1146198563
Short name T1527
Test name
Test status
Simulation time 2965706378 ps
CPU time 11.34 seconds
Started Aug 21 08:44:29 AM UTC 24
Finished Aug 21 08:44:42 AM UTC 24
Peak memory 229016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1146198563 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1146198563
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.3221563908
Short name T1545
Test name
Test status
Simulation time 6253693223 ps
CPU time 8.71 seconds
Started Aug 21 08:44:51 AM UTC 24
Finished Aug 21 08:45:01 AM UTC 24
Peak memory 222812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3221563908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3221563908
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.2151066853
Short name T1534
Test name
Test status
Simulation time 273596185 ps
CPU time 1.39 seconds
Started Aug 21 08:44:49 AM UTC 24
Finished Aug 21 08:44:51 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2151066853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_acq.2151066853
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.2125296838
Short name T1536
Test name
Test status
Simulation time 269587436 ps
CPU time 2.61 seconds
Started Aug 21 08:44:49 AM UTC 24
Finished Aug 21 08:44:53 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2125296838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_fifo_reset_tx.2125296838
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.3644202598
Short name T1542
Test name
Test status
Simulation time 659649445 ps
CPU time 4.53 seconds
Started Aug 21 08:44:54 AM UTC 24
Finished Aug 21 08:44:59 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3644202598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.3644202598
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.869375452
Short name T1541
Test name
Test status
Simulation time 246266848 ps
CPU time 2.3 seconds
Started Aug 21 08:44:55 AM UTC 24
Finished Aug 21 08:44:58 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=869375452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.869375452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.3200641747
Short name T1532
Test name
Test status
Simulation time 1001287652 ps
CPU time 9.04 seconds
Started Aug 21 08:44:40 AM UTC 24
Finished Aug 21 08:44:50 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3200641747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.3200641747
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.1697970828
Short name T1625
Test name
Test status
Simulation time 19775498078 ps
CPU time 115.05 seconds
Started Aug 21 08:44:40 AM UTC 24
Finished Aug 21 08:46:37 AM UTC 24
Peak memory 2511284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1697970828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1697970828
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.2260136439
Short name T1551
Test name
Test status
Simulation time 1226494788 ps
CPU time 4.71 seconds
Started Aug 21 08:44:58 AM UTC 24
Finished Aug 21 08:45:04 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2260136439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_target_nack_acqfull.2260136439
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.1665269453
Short name T1549
Test name
Test status
Simulation time 3645420438 ps
CPU time 3.89 seconds
Started Aug 21 08:44:58 AM UTC 24
Finished Aug 21 08:45:03 AM UTC 24
Peak memory 216720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1665269453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_nack_acqfull_addr.1665269453
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_perf.3163168062
Short name T1539
Test name
Test status
Simulation time 2828298665 ps
CPU time 6.21 seconds
Started Aug 21 08:44:50 AM UTC 24
Finished Aug 21 08:44:57 AM UTC 24
Peak memory 233036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3163168062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 44.i2c_target_perf.3163168062
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.4155061027
Short name T1546
Test name
Test status
Simulation time 1562058237 ps
CPU time 2.39 seconds
Started Aug 21 08:44:58 AM UTC 24
Finished Aug 21 08:45:01 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4155061027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_target_smbus_maxlen.4155061027
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.1894121317
Short name T1525
Test name
Test status
Simulation time 2026717482 ps
CPU time 8.15 seconds
Started Aug 21 08:44:29 AM UTC 24
Finished Aug 21 08:44:39 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1894121317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_targ
et_smoke.1894121317
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.513194809
Short name T1589
Test name
Test status
Simulation time 33465885145 ps
CPU time 53.3 seconds
Started Aug 21 08:44:50 AM UTC 24
Finished Aug 21 08:45:45 AM UTC 24
Peak memory 313520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=513194809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.i2c_target_stress_all.513194809
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.222552573
Short name T1569
Test name
Test status
Simulation time 1167401011 ps
CPU time 50.09 seconds
Started Aug 21 08:44:34 AM UTC 24
Finished Aug 21 08:45:25 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=222552573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stress_rd.222552573
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.970327261
Short name T1550
Test name
Test status
Simulation time 8821106120 ps
CPU time 31.65 seconds
Started Aug 21 08:44:30 AM UTC 24
Finished Aug 21 08:45:03 AM UTC 24
Peak memory 216968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=970327261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stress_wr.970327261
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_stretch.185113858
Short name T1530
Test name
Test status
Simulation time 1722066112 ps
CPU time 10.45 seconds
Started Aug 21 08:44:37 AM UTC 24
Finished Aug 21 08:44:48 AM UTC 24
Peak memory 356584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=185113858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_tar
get_stretch.185113858
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.243264316
Short name T1537
Test name
Test status
Simulation time 4612383738 ps
CPU time 9.81 seconds
Started Aug 21 08:44:43 AM UTC 24
Finished Aug 21 08:44:54 AM UTC 24
Peak memory 233876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=243264316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_timeout.243264316
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.2923635546
Short name T1543
Test name
Test status
Simulation time 126389403 ps
CPU time 3.53 seconds
Started Aug 21 08:44:55 AM UTC 24
Finished Aug 21 08:44:59 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2923635546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.2923635546
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_alert_test.2271222861
Short name T1579
Test name
Test status
Simulation time 49069291 ps
CPU time 0.95 seconds
Started Aug 21 08:45:31 AM UTC 24
Finished Aug 21 08:45:33 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2271222861 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.2271222861
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.1376042062
Short name T1558
Test name
Test status
Simulation time 1324135211 ps
CPU time 3.23 seconds
Started Aug 21 08:45:05 AM UTC 24
Finished Aug 21 08:45:09 AM UTC 24
Peak memory 244068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1376042062 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1376042062
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.3459754984
Short name T1561
Test name
Test status
Simulation time 318877413 ps
CPU time 10.47 seconds
Started Aug 21 08:45:02 AM UTC 24
Finished Aug 21 08:45:14 AM UTC 24
Peak memory 252236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3459754984 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty.3459754984
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.3569676485
Short name T1592
Test name
Test status
Simulation time 8730314769 ps
CPU time 50.57 seconds
Started Aug 21 08:45:04 AM UTC 24
Finished Aug 21 08:45:56 AM UTC 24
Peak memory 381140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3569676485 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3569676485
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.3144853710
Short name T1636
Test name
Test status
Simulation time 1576515481 ps
CPU time 103.96 seconds
Started Aug 21 08:45:02 AM UTC 24
Finished Aug 21 08:46:48 AM UTC 24
Peak memory 587876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3144853710 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3144853710
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.750848590
Short name T1553
Test name
Test status
Simulation time 111265707 ps
CPU time 1.65 seconds
Started Aug 21 08:45:02 AM UTC 24
Finished Aug 21 08:45:05 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=750848590 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fmt.750848590
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.3474767166
Short name T1557
Test name
Test status
Simulation time 2545155257 ps
CPU time 4.72 seconds
Started Aug 21 08:45:03 AM UTC 24
Finished Aug 21 08:45:08 AM UTC 24
Peak memory 216716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3474767166 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.3474767166
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.3669312335
Short name T1613
Test name
Test status
Simulation time 13288028487 ps
CPU time 72.42 seconds
Started Aug 21 08:45:02 AM UTC 24
Finished Aug 21 08:46:17 AM UTC 24
Peak memory 1038548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3669312335 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.3669312335
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.203384123
Short name T1580
Test name
Test status
Simulation time 505109366 ps
CPU time 8.41 seconds
Started Aug 21 08:45:24 AM UTC 24
Finished Aug 21 08:45:34 AM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=203384123 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.203384123
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_override.352467755
Short name T1548
Test name
Test status
Simulation time 24993748 ps
CPU time 0.87 seconds
Started Aug 21 08:45:00 AM UTC 24
Finished Aug 21 08:45:02 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=352467755 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.352467755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_perf.2580431065
Short name T1598
Test name
Test status
Simulation time 18146536869 ps
CPU time 123.92 seconds
Started Aug 21 08:45:04 AM UTC 24
Finished Aug 21 08:47:10 AM UTC 24
Peak memory 1231080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2580431065 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2580431065
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.2180129118
Short name T1555
Test name
Test status
Simulation time 369106795 ps
CPU time 1.67 seconds
Started Aug 21 08:45:05 AM UTC 24
Finished Aug 21 08:45:07 AM UTC 24
Peak memory 226440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2180129118 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.2180129118
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.78484260
Short name T1576
Test name
Test status
Simulation time 6244546945 ps
CPU time 29.79 seconds
Started Aug 21 08:45:00 AM UTC 24
Finished Aug 21 08:45:31 AM UTC 24
Peak memory 381212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=78484260 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.78484260
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.989181793
Short name T1583
Test name
Test status
Simulation time 579962451 ps
CPU time 30.46 seconds
Started Aug 21 08:45:05 AM UTC 24
Finished Aug 21 08:45:37 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=989181793 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.989181793
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.3310829995
Short name T1570
Test name
Test status
Simulation time 8581936641 ps
CPU time 6.86 seconds
Started Aug 21 08:45:19 AM UTC 24
Finished Aug 21 08:45:27 AM UTC 24
Peak memory 233800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3310829995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3310829995
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.4153945041
Short name T1563
Test name
Test status
Simulation time 456459041 ps
CPU time 1.43 seconds
Started Aug 21 08:45:15 AM UTC 24
Finished Aug 21 08:45:17 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4153945041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_fifo_reset_acq.4153945041
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.592847652
Short name T1565
Test name
Test status
Simulation time 169613992 ps
CPU time 1.49 seconds
Started Aug 21 08:45:17 AM UTC 24
Finished Aug 21 08:45:19 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=592847652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 45.i2c_target_fifo_reset_tx.592847652
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.2880239290
Short name T1575
Test name
Test status
Simulation time 543978399 ps
CPU time 4.89 seconds
Started Aug 21 08:45:25 AM UTC 24
Finished Aug 21 08:45:31 AM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2880239290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.2880239290
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.1079626259
Short name T1572
Test name
Test status
Simulation time 154271343 ps
CPU time 2.32 seconds
Started Aug 21 08:45:26 AM UTC 24
Finished Aug 21 08:45:30 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1079626259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.1079626259
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_hrst.1770417574
Short name T1568
Test name
Test status
Simulation time 345818658 ps
CPU time 3.46 seconds
Started Aug 21 08:45:20 AM UTC 24
Finished Aug 21 08:45:24 AM UTC 24
Peak memory 233644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1770417574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 45.i2c_target_hrst.1770417574
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.646453470
Short name T1564
Test name
Test status
Simulation time 4437726009 ps
CPU time 7.39 seconds
Started Aug 21 08:45:09 AM UTC 24
Finished Aug 21 08:45:18 AM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=646453470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_target_intr_smoke.646453470
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.826754129
Short name T1573
Test name
Test status
Simulation time 9196910203 ps
CPU time 18.18 seconds
Started Aug 21 08:45:10 AM UTC 24
Finished Aug 21 08:45:30 AM UTC 24
Peak memory 276648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=826754129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.826754129
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.3811516327
Short name T1556
Test name
Test status
Simulation time 592806805 ps
CPU time 5 seconds
Started Aug 21 08:45:29 AM UTC 24
Finished Aug 21 08:45:36 AM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3811516327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 45.i2c_target_nack_acqfull.3811516327
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.218157840
Short name T1582
Test name
Test status
Simulation time 2151906201 ps
CPU time 4.35 seconds
Started Aug 21 08:45:31 AM UTC 24
Finished Aug 21 08:45:36 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=218157840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_nack_acqfull_addr.218157840
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_perf.295802242
Short name T1567
Test name
Test status
Simulation time 509351094 ps
CPU time 4.57 seconds
Started Aug 21 08:45:18 AM UTC 24
Finished Aug 21 08:45:23 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=295802242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 45.i2c_target_perf.295802242
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.498483839
Short name T1578
Test name
Test status
Simulation time 486011370 ps
CPU time 4.24 seconds
Started Aug 21 08:45:27 AM UTC 24
Finished Aug 21 08:45:33 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=498483839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 45.i2c_target_smbus_maxlen.498483839
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.4036988089
Short name T1577
Test name
Test status
Simulation time 701263191 ps
CPU time 24.86 seconds
Started Aug 21 08:45:06 AM UTC 24
Finished Aug 21 08:45:32 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4036988089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_targ
et_smoke.4036988089
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.3846430821
Short name T1729
Test name
Test status
Simulation time 88370906930 ps
CPU time 271.43 seconds
Started Aug 21 08:45:18 AM UTC 24
Finished Aug 21 08:49:53 AM UTC 24
Peak memory 2503128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3846430821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 45.i2c_target_stress_all.3846430821
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.1817031722
Short name T1615
Test name
Test status
Simulation time 1282224902 ps
CPU time 67.36 seconds
Started Aug 21 08:45:09 AM UTC 24
Finished Aug 21 08:46:18 AM UTC 24
Peak memory 231180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1817031722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stress_rd.1817031722
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.1408134169
Short name T1686
Test name
Test status
Simulation time 36135527158 ps
CPU time 142.9 seconds
Started Aug 21 08:45:08 AM UTC 24
Finished Aug 21 08:47:33 AM UTC 24
Peak memory 2189724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1408134169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stress_wr.1408134169
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.4014356016
Short name T1616
Test name
Test status
Simulation time 3870340006 ps
CPU time 68.07 seconds
Started Aug 21 08:45:09 AM UTC 24
Finished Aug 21 08:46:19 AM UTC 24
Peak memory 1048924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4014356016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_stretch.4014356016
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.292235433
Short name T1566
Test name
Test status
Simulation time 1990859493 ps
CPU time 7.91 seconds
Started Aug 21 08:45:12 AM UTC 24
Finished Aug 21 08:45:22 AM UTC 24
Peak memory 243884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=292235433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_timeout.292235433
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.187597387
Short name T1574
Test name
Test status
Simulation time 159149835 ps
CPU time 2.69 seconds
Started Aug 21 08:45:26 AM UTC 24
Finished Aug 21 08:45:30 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=187597387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_tx_stretch_ctrl.187597387
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_alert_test.1111076576
Short name T1608
Test name
Test status
Simulation time 93629862 ps
CPU time 0.94 seconds
Started Aug 21 08:46:12 AM UTC 24
Finished Aug 21 08:46:15 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111076576 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1111076576
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.4199886277
Short name T1587
Test name
Test status
Simulation time 142940534 ps
CPU time 2.8 seconds
Started Aug 21 08:45:38 AM UTC 24
Finished Aug 21 08:45:41 AM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4199886277 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.4199886277
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.3723415384
Short name T1588
Test name
Test status
Simulation time 378220300 ps
CPU time 6.35 seconds
Started Aug 21 08:45:34 AM UTC 24
Finished Aug 21 08:45:42 AM UTC 24
Peak memory 299048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3723415384 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty.3723415384
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.2862441323
Short name T1632
Test name
Test status
Simulation time 11543551198 ps
CPU time 66.55 seconds
Started Aug 21 08:45:35 AM UTC 24
Finished Aug 21 08:46:43 AM UTC 24
Peak memory 370852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2862441323 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.2862441323
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3848077773
Short name T1653
Test name
Test status
Simulation time 5184247524 ps
CPU time 83.37 seconds
Started Aug 21 08:45:34 AM UTC 24
Finished Aug 21 08:46:59 AM UTC 24
Peak memory 532972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3848077773 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3848077773
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.1328780966
Short name T1584
Test name
Test status
Simulation time 1608961201 ps
CPU time 1.82 seconds
Started Aug 21 08:45:34 AM UTC 24
Finished Aug 21 08:45:37 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1328780966 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fmt.1328780966
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.3040361004
Short name T1586
Test name
Test status
Simulation time 178877169 ps
CPU time 3.98 seconds
Started Aug 21 08:45:35 AM UTC 24
Finished Aug 21 08:45:40 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3040361004 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.3040361004
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.382972407
Short name T1730
Test name
Test status
Simulation time 7162139551 ps
CPU time 271.63 seconds
Started Aug 21 08:45:33 AM UTC 24
Finished Aug 21 08:50:09 AM UTC 24
Peak memory 1212604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=382972407 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.382972407
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.1953040623
Short name T1607
Test name
Test status
Simulation time 1505234030 ps
CPU time 7.52 seconds
Started Aug 21 08:46:04 AM UTC 24
Finished Aug 21 08:46:13 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953040623 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1953040623
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_override.409495628
Short name T1581
Test name
Test status
Simulation time 29028149 ps
CPU time 1.09 seconds
Started Aug 21 08:45:32 AM UTC 24
Finished Aug 21 08:45:34 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=409495628 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.409495628
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_perf.230419592
Short name T1595
Test name
Test status
Simulation time 2697310068 ps
CPU time 23.29 seconds
Started Aug 21 08:45:35 AM UTC 24
Finished Aug 21 08:46:00 AM UTC 24
Peak memory 561368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=230419592 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.230419592
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.2452826341
Short name T1585
Test name
Test status
Simulation time 236723182 ps
CPU time 2.26 seconds
Started Aug 21 08:45:36 AM UTC 24
Finished Aug 21 08:45:40 AM UTC 24
Peak memory 230908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2452826341 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.2452826341
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.3143628951
Short name T1659
Test name
Test status
Simulation time 3389151299 ps
CPU time 88.99 seconds
Started Aug 21 08:45:32 AM UTC 24
Finished Aug 21 08:47:03 AM UTC 24
Peak memory 450900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3143628951 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3143628951
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.1991732036
Short name T1591
Test name
Test status
Simulation time 734142306 ps
CPU time 16.62 seconds
Started Aug 21 08:45:37 AM UTC 24
Finished Aug 21 08:45:55 AM UTC 24
Peak memory 227076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1991732036 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1991732036
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.1084530431
Short name T1605
Test name
Test status
Simulation time 1202036332 ps
CPU time 9.16 seconds
Started Aug 21 08:46:01 AM UTC 24
Finished Aug 21 08:46:11 AM UTC 24
Peak memory 232964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1084530431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1084530431
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.2726491464
Short name T1596
Test name
Test status
Simulation time 922301517 ps
CPU time 1.56 seconds
Started Aug 21 08:45:57 AM UTC 24
Finished Aug 21 08:46:01 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2726491464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_acq.2726491464
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.891092314
Short name T1597
Test name
Test status
Simulation time 329324229 ps
CPU time 1.62 seconds
Started Aug 21 08:45:59 AM UTC 24
Finished Aug 21 08:46:02 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=891092314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 46.i2c_target_fifo_reset_tx.891092314
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.3365099575
Short name T1604
Test name
Test status
Simulation time 496944854 ps
CPU time 2.48 seconds
Started Aug 21 08:46:07 AM UTC 24
Finished Aug 21 08:46:11 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3365099575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.3365099575
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.2307456430
Short name T1603
Test name
Test status
Simulation time 111849619 ps
CPU time 1.64 seconds
Started Aug 21 08:46:07 AM UTC 24
Finished Aug 21 08:46:10 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2307456430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.2307456430
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_hrst.2095277584
Short name T1599
Test name
Test status
Simulation time 292929934 ps
CPU time 3.13 seconds
Started Aug 21 08:46:02 AM UTC 24
Finished Aug 21 08:46:06 AM UTC 24
Peak memory 233328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2095277584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 46.i2c_target_hrst.2095277584
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.3972429420
Short name T1590
Test name
Test status
Simulation time 740104928 ps
CPU time 7.02 seconds
Started Aug 21 08:45:46 AM UTC 24
Finished Aug 21 08:45:54 AM UTC 24
Peak memory 233164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3972429420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.3972429420
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.938737742
Short name T1726
Test name
Test status
Simulation time 24141266935 ps
CPU time 171.7 seconds
Started Aug 21 08:45:55 AM UTC 24
Finished Aug 21 08:48:49 AM UTC 24
Peak memory 2281636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=938737742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.938737742
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.3915283563
Short name T1610
Test name
Test status
Simulation time 565038251 ps
CPU time 4.04 seconds
Started Aug 21 08:46:10 AM UTC 24
Finished Aug 21 08:46:15 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3915283563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 46.i2c_target_nack_acqfull.3915283563
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.45749835
Short name T1614
Test name
Test status
Simulation time 552553989 ps
CPU time 5.7 seconds
Started Aug 21 08:46:11 AM UTC 24
Finished Aug 21 08:46:18 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=45749835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_nack_acqfull_addr.45749835
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.3730633653
Short name T1612
Test name
Test status
Simulation time 277566099 ps
CPU time 2.01 seconds
Started Aug 21 08:46:12 AM UTC 24
Finished Aug 21 08:46:16 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3730633653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_nack_txstretch.3730633653
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_perf.1677640367
Short name T1600
Test name
Test status
Simulation time 2286207458 ps
CPU time 5.61 seconds
Started Aug 21 08:45:59 AM UTC 24
Finished Aug 21 08:46:06 AM UTC 24
Peak memory 231312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1677640367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 46.i2c_target_perf.1677640367
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2647016474
Short name T1609
Test name
Test status
Simulation time 1762560627 ps
CPU time 3.8 seconds
Started Aug 21 08:46:10 AM UTC 24
Finished Aug 21 08:46:15 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2647016474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 46.i2c_target_smbus_maxlen.2647016474
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.603151904
Short name T1594
Test name
Test status
Simulation time 1288519599 ps
CPU time 15.63 seconds
Started Aug 21 08:45:41 AM UTC 24
Finished Aug 21 08:45:58 AM UTC 24
Peak memory 233500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=603151904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_targe
t_smoke.603151904
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.4032736081
Short name T1622
Test name
Test status
Simulation time 39305968808 ps
CPU time 25.89 seconds
Started Aug 21 08:46:01 AM UTC 24
Finished Aug 21 08:46:28 AM UTC 24
Peak memory 276656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=4032736081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 46.i2c_target_stress_all.4032736081
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.2576762315
Short name T1628
Test name
Test status
Simulation time 1270142021 ps
CPU time 56.66 seconds
Started Aug 21 08:45:42 AM UTC 24
Finished Aug 21 08:46:40 AM UTC 24
Peak memory 228828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2576762315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stress_rd.2576762315
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.2629529623
Short name T1743
Test name
Test status
Simulation time 50592110089 ps
CPU time 745.63 seconds
Started Aug 21 08:45:41 AM UTC 24
Finished Aug 21 08:58:14 AM UTC 24
Peak memory 8132832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2629529623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stress_wr.2629529623
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.2509551449
Short name T1725
Test name
Test status
Simulation time 5480607881 ps
CPU time 177.46 seconds
Started Aug 21 08:45:43 AM UTC 24
Finished Aug 21 08:48:43 AM UTC 24
Peak memory 1165648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2509551449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_stretch.2509551449
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.2932142560
Short name T1601
Test name
Test status
Simulation time 5346082227 ps
CPU time 10.36 seconds
Started Aug 21 08:45:56 AM UTC 24
Finished Aug 21 08:46:09 AM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2932142560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_timeout.2932142560
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.876129242
Short name T1606
Test name
Test status
Simulation time 88586854 ps
CPU time 2.79 seconds
Started Aug 21 08:46:07 AM UTC 24
Finished Aug 21 08:46:11 AM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=876129242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_tx_stretch_ctrl.876129242
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_alert_test.3423401117
Short name T1645
Test name
Test status
Simulation time 45259622 ps
CPU time 0.86 seconds
Started Aug 21 08:46:53 AM UTC 24
Finished Aug 21 08:46:55 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3423401117 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3423401117
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.173654641
Short name T1621
Test name
Test status
Simulation time 370588503 ps
CPU time 4.53 seconds
Started Aug 21 08:46:20 AM UTC 24
Finished Aug 21 08:46:26 AM UTC 24
Peak memory 241176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=173654641 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.173654641
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2009019398
Short name T1623
Test name
Test status
Simulation time 829919467 ps
CPU time 13.05 seconds
Started Aug 21 08:46:17 AM UTC 24
Finished Aug 21 08:46:31 AM UTC 24
Peak memory 317732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2009019398 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empty.2009019398
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.2702327657
Short name T1661
Test name
Test status
Simulation time 1979703217 ps
CPU time 47.91 seconds
Started Aug 21 08:46:18 AM UTC 24
Finished Aug 21 08:47:08 AM UTC 24
Peak memory 366676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2702327657 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2702327657
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1956001925
Short name T1642
Test name
Test status
Simulation time 7856463006 ps
CPU time 36 seconds
Started Aug 21 08:46:16 AM UTC 24
Finished Aug 21 08:46:53 AM UTC 24
Peak memory 553228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1956001925 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1956001925
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.3311166481
Short name T1617
Test name
Test status
Simulation time 327955124 ps
CPU time 1.26 seconds
Started Aug 21 08:46:17 AM UTC 24
Finished Aug 21 08:46:19 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3311166481 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt.3311166481
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.836480280
Short name T1620
Test name
Test status
Simulation time 391963537 ps
CPU time 3.67 seconds
Started Aug 21 08:46:17 AM UTC 24
Finished Aug 21 08:46:22 AM UTC 24
Peak memory 229356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=836480280 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.836480280
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.1626439137
Short name T1734
Test name
Test status
Simulation time 17602403729 ps
CPU time 294.85 seconds
Started Aug 21 08:46:16 AM UTC 24
Finished Aug 21 08:51:15 AM UTC 24
Peak memory 1552584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1626439137 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1626439137
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_override.1190824714
Short name T1611
Test name
Test status
Simulation time 190406068 ps
CPU time 0.94 seconds
Started Aug 21 08:46:14 AM UTC 24
Finished Aug 21 08:46:16 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1190824714 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.1190824714
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_perf.3513061313
Short name T1643
Test name
Test status
Simulation time 672725857 ps
CPU time 32.59 seconds
Started Aug 21 08:46:19 AM UTC 24
Finished Aug 21 08:46:53 AM UTC 24
Peak memory 241876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3513061313 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3513061313
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.2984760850
Short name T1619
Test name
Test status
Simulation time 194152385 ps
CPU time 1.48 seconds
Started Aug 21 08:46:19 AM UTC 24
Finished Aug 21 08:46:22 AM UTC 24
Peak memory 216540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2984760850 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.2984760850
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1112308345
Short name T1646
Test name
Test status
Simulation time 3566174131 ps
CPU time 41.22 seconds
Started Aug 21 08:46:12 AM UTC 24
Finished Aug 21 08:46:55 AM UTC 24
Peak memory 379036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1112308345 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1112308345
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.3491959693
Short name T1624
Test name
Test status
Simulation time 645026956 ps
CPU time 10.36 seconds
Started Aug 21 08:46:20 AM UTC 24
Finished Aug 21 08:46:32 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3491959693 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3491959693
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.1534584904
Short name T1644
Test name
Test status
Simulation time 1208891049 ps
CPU time 10.13 seconds
Started Aug 21 08:46:42 AM UTC 24
Finished Aug 21 08:46:53 AM UTC 24
Peak memory 222752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1534584904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1534584904
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.3310370352
Short name T1631
Test name
Test status
Simulation time 309838490 ps
CPU time 1.27 seconds
Started Aug 21 08:46:39 AM UTC 24
Finished Aug 21 08:46:42 AM UTC 24
Peak memory 228468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3310370352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_acq.3310370352
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.4202200580
Short name T1633
Test name
Test status
Simulation time 290342998 ps
CPU time 2.85 seconds
Started Aug 21 08:46:41 AM UTC 24
Finished Aug 21 08:46:45 AM UTC 24
Peak memory 222736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4202200580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_fifo_reset_tx.4202200580
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.2781982523
Short name T1641
Test name
Test status
Simulation time 1927137473 ps
CPU time 3.47 seconds
Started Aug 21 08:46:48 AM UTC 24
Finished Aug 21 08:46:52 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2781982523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.2781982523
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.1232927249
Short name T1638
Test name
Test status
Simulation time 1067998364 ps
CPU time 2.43 seconds
Started Aug 21 08:46:48 AM UTC 24
Finished Aug 21 08:46:51 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1232927249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.1232927249
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.745597850
Short name T1630
Test name
Test status
Simulation time 3574105816 ps
CPU time 7.79 seconds
Started Aug 21 08:46:32 AM UTC 24
Finished Aug 21 08:46:41 AM UTC 24
Peak memory 233644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=745597850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_intr_smoke.745597850
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.3790825319
Short name T1736
Test name
Test status
Simulation time 20118072760 ps
CPU time 310.86 seconds
Started Aug 21 08:46:33 AM UTC 24
Finished Aug 21 08:51:48 AM UTC 24
Peak memory 4766132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3790825319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.3790825319
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.725081741
Short name T1651
Test name
Test status
Simulation time 483025686 ps
CPU time 4.1 seconds
Started Aug 21 08:46:52 AM UTC 24
Finished Aug 21 08:46:57 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=725081741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 47.i2c_target_nack_acqfull.725081741
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.532956707
Short name T1652
Test name
Test status
Simulation time 433264773 ps
CPU time 3.7 seconds
Started Aug 21 08:46:53 AM UTC 24
Finished Aug 21 08:46:58 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=532956707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_nack_acqfull_addr.532956707
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.966047275
Short name T1649
Test name
Test status
Simulation time 139954495 ps
CPU time 2.59 seconds
Started Aug 21 08:46:53 AM UTC 24
Finished Aug 21 08:46:57 AM UTC 24
Peak memory 233372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=966047275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_nack_txstretch.966047275
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_perf.765417514
Short name T1637
Test name
Test status
Simulation time 5154124942 ps
CPU time 8.21 seconds
Started Aug 21 08:46:41 AM UTC 24
Finished Aug 21 08:46:51 AM UTC 24
Peak memory 227188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=765417514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 47.i2c_target_perf.765417514
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.3356635237
Short name T1650
Test name
Test status
Simulation time 527762146 ps
CPU time 3.79 seconds
Started Aug 21 08:46:52 AM UTC 24
Finished Aug 21 08:46:57 AM UTC 24
Peak memory 216440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3356635237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 47.i2c_target_smbus_maxlen.3356635237
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.1011316383
Short name T1635
Test name
Test status
Simulation time 2659183478 ps
CPU time 22.95 seconds
Started Aug 21 08:46:22 AM UTC 24
Finished Aug 21 08:46:47 AM UTC 24
Peak memory 227164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1011316383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_targ
et_smoke.1011316383
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.2390987048
Short name T1735
Test name
Test status
Simulation time 47952351827 ps
CPU time 291.93 seconds
Started Aug 21 08:46:42 AM UTC 24
Finished Aug 21 08:51:38 AM UTC 24
Peak memory 3020980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2390987048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 47.i2c_target_stress_all.2390987048
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.4267584216
Short name T1629
Test name
Test status
Simulation time 2365100039 ps
CPU time 12.64 seconds
Started Aug 21 08:46:27 AM UTC 24
Finished Aug 21 08:46:40 AM UTC 24
Peak memory 231260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4267584216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stress_rd.4267584216
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.2604137282
Short name T1640
Test name
Test status
Simulation time 13482850053 ps
CPU time 28.18 seconds
Started Aug 21 08:46:22 AM UTC 24
Finished Aug 21 08:46:52 AM UTC 24
Peak memory 216708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2604137282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stress_wr.2604137282
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.2627126727
Short name T1634
Test name
Test status
Simulation time 3662720751 ps
CPU time 39.74 seconds
Started Aug 21 08:46:29 AM UTC 24
Finished Aug 21 08:47:10 AM UTC 24
Peak memory 762116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2627126727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_stretch.2627126727
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.2597017791
Short name T1639
Test name
Test status
Simulation time 6043912620 ps
CPU time 12.07 seconds
Started Aug 21 08:46:38 AM UTC 24
Finished Aug 21 08:46:52 AM UTC 24
Peak memory 250028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2597017791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_timeout.2597017791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.1780827872
Short name T1655
Test name
Test status
Simulation time 696635746 ps
CPU time 9.54 seconds
Started Aug 21 08:46:50 AM UTC 24
Finished Aug 21 08:47:00 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1780827872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.1780827872
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_alert_test.2925170197
Short name T1679
Test name
Test status
Simulation time 16280933 ps
CPU time 0.82 seconds
Started Aug 21 08:47:23 AM UTC 24
Finished Aug 21 08:47:25 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2925170197 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2925170197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.3906299418
Short name T1658
Test name
Test status
Simulation time 186227748 ps
CPU time 2.17 seconds
Started Aug 21 08:46:59 AM UTC 24
Finished Aug 21 08:47:02 AM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3906299418 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3906299418
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.18587435
Short name T1660
Test name
Test status
Simulation time 529843632 ps
CPU time 5.96 seconds
Started Aug 21 08:46:57 AM UTC 24
Finished Aug 21 08:47:04 AM UTC 24
Peak memory 272672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18587435 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empty.18587435
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.3486650711
Short name T1723
Test name
Test status
Simulation time 22314507443 ps
CPU time 97.75 seconds
Started Aug 21 08:46:57 AM UTC 24
Finished Aug 21 08:48:36 AM UTC 24
Peak memory 481768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3486650711 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3486650711
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.2660926779
Short name T1690
Test name
Test status
Simulation time 2706355899 ps
CPU time 40.49 seconds
Started Aug 21 08:46:55 AM UTC 24
Finished Aug 21 08:47:37 AM UTC 24
Peak memory 514252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2660926779 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2660926779
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3175317008
Short name T1654
Test name
Test status
Simulation time 314383595 ps
CPU time 2.16 seconds
Started Aug 21 08:46:57 AM UTC 24
Finished Aug 21 08:47:00 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3175317008 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt.3175317008
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.2363979621
Short name T1656
Test name
Test status
Simulation time 481461209 ps
CPU time 3.89 seconds
Started Aug 21 08:46:57 AM UTC 24
Finished Aug 21 08:47:02 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2363979621 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.2363979621
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.3415941824
Short name T1721
Test name
Test status
Simulation time 13088015979 ps
CPU time 94.21 seconds
Started Aug 21 08:46:54 AM UTC 24
Finished Aug 21 08:48:31 AM UTC 24
Peak memory 1151452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415941824 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.3415941824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.966879546
Short name T1673
Test name
Test status
Simulation time 1325025155 ps
CPU time 6.1 seconds
Started Aug 21 08:47:15 AM UTC 24
Finished Aug 21 08:47:22 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=966879546 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.966879546
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.1410227880
Short name T1669
Test name
Test status
Simulation time 258012861 ps
CPU time 1.68 seconds
Started Aug 21 08:47:15 AM UTC 24
Finished Aug 21 08:47:18 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1410227880 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1410227880
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_override.774709987
Short name T1648
Test name
Test status
Simulation time 16659878 ps
CPU time 0.95 seconds
Started Aug 21 08:46:54 AM UTC 24
Finished Aug 21 08:46:56 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=774709987 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.774709987
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_perf.1863315720
Short name T1700
Test name
Test status
Simulation time 13724395565 ps
CPU time 47.91 seconds
Started Aug 21 08:46:58 AM UTC 24
Finished Aug 21 08:47:47 AM UTC 24
Peak memory 583948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1863315720 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1863315720
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.743181811
Short name T1657
Test name
Test status
Simulation time 109723519 ps
CPU time 3.2 seconds
Started Aug 21 08:46:58 AM UTC 24
Finished Aug 21 08:47:02 AM UTC 24
Peak memory 233612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=743181811 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.743181811
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.3682217993
Short name T1666
Test name
Test status
Simulation time 787137726 ps
CPU time 19.49 seconds
Started Aug 21 08:46:54 AM UTC 24
Finished Aug 21 08:47:15 AM UTC 24
Peak memory 309352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3682217993 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3682217993
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.293183313
Short name T1662
Test name
Test status
Simulation time 652148692 ps
CPU time 13 seconds
Started Aug 21 08:46:58 AM UTC 24
Finished Aug 21 08:47:12 AM UTC 24
Peak memory 233020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=293183313 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.293183313
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.1155247413
Short name T1672
Test name
Test status
Simulation time 2574175453 ps
CPU time 6.2 seconds
Started Aug 21 08:47:13 AM UTC 24
Finished Aug 21 08:47:20 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=1155247413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1155247413
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.3805456465
Short name T1665
Test name
Test status
Simulation time 821908418 ps
CPU time 2.34 seconds
Started Aug 21 08:47:11 AM UTC 24
Finished Aug 21 08:47:14 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3805456465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_fifo_reset_acq.3805456465
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.4015071445
Short name T1663
Test name
Test status
Simulation time 169988819 ps
CPU time 1.66 seconds
Started Aug 21 08:47:11 AM UTC 24
Finished Aug 21 08:47:13 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4015071445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_fifo_reset_tx.4015071445
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.3319592411
Short name T1670
Test name
Test status
Simulation time 611967615 ps
CPU time 1.72 seconds
Started Aug 21 08:47:16 AM UTC 24
Finished Aug 21 08:47:19 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3319592411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.3319592411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.3003873229
Short name T1671
Test name
Test status
Simulation time 478053168 ps
CPU time 1.44 seconds
Started Aug 21 08:47:17 AM UTC 24
Finished Aug 21 08:47:20 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3003873229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.3003873229
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.716538602
Short name T1497
Test name
Test status
Simulation time 646497220 ps
CPU time 7.07 seconds
Started Aug 21 08:47:03 AM UTC 24
Finished Aug 21 08:47:12 AM UTC 24
Peak memory 233820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=716538602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_intr_smoke.716538602
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.4019544650
Short name T1719
Test name
Test status
Simulation time 7975126921 ps
CPU time 68.8 seconds
Started Aug 21 08:47:03 AM UTC 24
Finished Aug 21 08:48:14 AM UTC 24
Peak memory 1776104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=4019544650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.4019544650
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.2477854765
Short name T1678
Test name
Test status
Simulation time 2480901300 ps
CPU time 3.89 seconds
Started Aug 21 08:47:20 AM UTC 24
Finished Aug 21 08:47:24 AM UTC 24
Peak memory 227144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2477854765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 48.i2c_target_nack_acqfull.2477854765
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.3103388490
Short name T1680
Test name
Test status
Simulation time 464015570 ps
CPU time 4.11 seconds
Started Aug 21 08:47:21 AM UTC 24
Finished Aug 21 08:47:26 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3103388490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_nack_acqfull_addr.3103388490
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.2540276920
Short name T1675
Test name
Test status
Simulation time 180596007 ps
CPU time 2.25 seconds
Started Aug 21 08:47:21 AM UTC 24
Finished Aug 21 08:47:24 AM UTC 24
Peak memory 233556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2540276920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.i2c_target_nack_txstretch.2540276920
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_perf.4234940260
Short name T1668
Test name
Test status
Simulation time 654455667 ps
CPU time 4.8 seconds
Started Aug 21 08:47:12 AM UTC 24
Finished Aug 21 08:47:18 AM UTC 24
Peak memory 233584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4234940260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 48.i2c_target_perf.4234940260
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.1639685884
Short name T1677
Test name
Test status
Simulation time 497625996 ps
CPU time 4.74 seconds
Started Aug 21 08:47:19 AM UTC 24
Finished Aug 21 08:47:24 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1639685884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 48.i2c_target_smbus_maxlen.1639685884
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.348466334
Short name T1664
Test name
Test status
Simulation time 4906803037 ps
CPU time 12.6 seconds
Started Aug 21 08:47:00 AM UTC 24
Finished Aug 21 08:47:14 AM UTC 24
Peak memory 233760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=348466334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_targe
t_smoke.348466334
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.1646490074
Short name T1724
Test name
Test status
Simulation time 86612888988 ps
CPU time 88.23 seconds
Started Aug 21 08:47:12 AM UTC 24
Finished Aug 21 08:48:42 AM UTC 24
Peak memory 667880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1646490074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 48.i2c_target_stress_all.1646490074
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.2614402353
Short name T1688
Test name
Test status
Simulation time 2694398854 ps
CPU time 32.87 seconds
Started Aug 21 08:47:02 AM UTC 24
Finished Aug 21 08:47:36 AM UTC 24
Peak memory 216968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2614402353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stress_rd.2614402353
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1424370513
Short name T1727
Test name
Test status
Simulation time 54970761298 ps
CPU time 141.32 seconds
Started Aug 21 08:47:01 AM UTC 24
Finished Aug 21 08:49:25 AM UTC 24
Peak memory 2224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1424370513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stress_wr.1424370513
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.3366948207
Short name T1667
Test name
Test status
Simulation time 4557641994 ps
CPU time 10.95 seconds
Started Aug 21 08:47:05 AM UTC 24
Finished Aug 21 08:47:17 AM UTC 24
Peak memory 233908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3366948207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_timeout.3366948207
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.3865928807
Short name T1676
Test name
Test status
Simulation time 345031764 ps
CPU time 4.65 seconds
Started Aug 21 08:47:18 AM UTC 24
Finished Aug 21 08:47:24 AM UTC 24
Peak memory 216792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3865928807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.3865928807
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_alert_test.2615666887
Short name T1710
Test name
Test status
Simulation time 40065900 ps
CPU time 0.87 seconds
Started Aug 21 08:47:57 AM UTC 24
Finished Aug 21 08:47:59 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2615666887 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2615666887
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.2959205444
Short name T1687
Test name
Test status
Simulation time 99439226 ps
CPU time 2.69 seconds
Started Aug 21 08:47:30 AM UTC 24
Finished Aug 21 08:47:33 AM UTC 24
Peak memory 233708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2959205444 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2959205444
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.3982102171
Short name T1689
Test name
Test status
Simulation time 4749412397 ps
CPU time 10.84 seconds
Started Aug 21 08:47:25 AM UTC 24
Finished Aug 21 08:47:37 AM UTC 24
Peak memory 317672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3982102171 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty.3982102171
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.1172391751
Short name T1731
Test name
Test status
Simulation time 4759211301 ps
CPU time 160.94 seconds
Started Aug 21 08:47:26 AM UTC 24
Finished Aug 21 08:50:10 AM UTC 24
Peak memory 753872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1172391751 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1172391751
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.1898241202
Short name T1718
Test name
Test status
Simulation time 8409013158 ps
CPU time 43.22 seconds
Started Aug 21 08:47:25 AM UTC 24
Finished Aug 21 08:48:10 AM UTC 24
Peak memory 541136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1898241202 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1898241202
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.331795872
Short name T1682
Test name
Test status
Simulation time 130830606 ps
CPU time 1.54 seconds
Started Aug 21 08:47:25 AM UTC 24
Finished Aug 21 08:47:28 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=331795872 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fmt.331795872
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.1046340989
Short name T1684
Test name
Test status
Simulation time 827440556 ps
CPU time 4.68 seconds
Started Aug 21 08:47:25 AM UTC 24
Finished Aug 21 08:47:31 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1046340989 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.1046340989
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2722044335
Short name T1728
Test name
Test status
Simulation time 4383050809 ps
CPU time 119.96 seconds
Started Aug 21 08:47:25 AM UTC 24
Finished Aug 21 08:49:27 AM UTC 24
Peak memory 1337572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2722044335 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2722044335
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.287886228
Short name T1707
Test name
Test status
Simulation time 399489724 ps
CPU time 6.73 seconds
Started Aug 21 08:47:48 AM UTC 24
Finished Aug 21 08:47:56 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=287886228 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlg
rey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.287886228
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_override.2640147453
Short name T1681
Test name
Test status
Simulation time 92166096 ps
CPU time 1.02 seconds
Started Aug 21 08:47:24 AM UTC 24
Finished Aug 21 08:47:26 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640147453 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.2640147453
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_perf.255932279
Short name T1714
Test name
Test status
Simulation time 7285832710 ps
CPU time 35.22 seconds
Started Aug 21 08:47:26 AM UTC 24
Finished Aug 21 08:48:03 AM UTC 24
Peak memory 541196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=255932279 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.255932279
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3889412643
Short name T1685
Test name
Test status
Simulation time 420276694 ps
CPU time 2.83 seconds
Started Aug 21 08:47:28 AM UTC 24
Finished Aug 21 08:47:31 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3889412643 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.3889412643
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.513911330
Short name T1722
Test name
Test status
Simulation time 1471456848 ps
CPU time 67.63 seconds
Started Aug 21 08:47:24 AM UTC 24
Finished Aug 21 08:48:33 AM UTC 24
Peak memory 401680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=513911330 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.513911330
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.2821710152
Short name T1693
Test name
Test status
Simulation time 2279325313 ps
CPU time 12.68 seconds
Started Aug 21 08:47:29 AM UTC 24
Finished Aug 21 08:47:42 AM UTC 24
Peak memory 231168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2821710152 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2821710152
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.2385409061
Short name T1709
Test name
Test status
Simulation time 1987283031 ps
CPU time 10.05 seconds
Started Aug 21 08:47:47 AM UTC 24
Finished Aug 21 08:47:58 AM UTC 24
Peak memory 233184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=2385409061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2385409061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.3008851749
Short name T1695
Test name
Test status
Simulation time 218201516 ps
CPU time 1.34 seconds
Started Aug 21 08:47:43 AM UTC 24
Finished Aug 21 08:47:46 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3008851749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_acq.3008851749
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.296581260
Short name T1696
Test name
Test status
Simulation time 136448979 ps
CPU time 1.64 seconds
Started Aug 21 08:47:44 AM UTC 24
Finished Aug 21 08:47:46 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=296581260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_fifo_reset_tx.296581260
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.2660784233
Short name T1706
Test name
Test status
Simulation time 584117568 ps
CPU time 3.27 seconds
Started Aug 21 08:47:50 AM UTC 24
Finished Aug 21 08:47:55 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2660784233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.2660784233
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.4210290054
Short name T1704
Test name
Test status
Simulation time 273693274 ps
CPU time 1.52 seconds
Started Aug 21 08:47:51 AM UTC 24
Finished Aug 21 08:47:54 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4210290054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.4210290054
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_hrst.2507858995
Short name T1703
Test name
Test status
Simulation time 1767670541 ps
CPU time 4.94 seconds
Started Aug 21 08:47:48 AM UTC 24
Finished Aug 21 08:47:54 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2507858995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 49.i2c_target_hrst.2507858995
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1994636340
Short name T1701
Test name
Test status
Simulation time 3005312767 ps
CPU time 10.04 seconds
Started Aug 21 08:47:38 AM UTC 24
Finished Aug 21 08:47:49 AM UTC 24
Peak memory 233808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1994636340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.1994636340
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.282856879
Short name T1738
Test name
Test status
Simulation time 21929133434 ps
CPU time 318.37 seconds
Started Aug 21 08:47:38 AM UTC 24
Finished Aug 21 08:53:00 AM UTC 24
Peak memory 3723692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=282856879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.282856879
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.1620758226
Short name T1713
Test name
Test status
Simulation time 565695545 ps
CPU time 4.83 seconds
Started Aug 21 08:47:55 AM UTC 24
Finished Aug 21 08:48:01 AM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1620758226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_nack_acqfull.1620758226
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.2734649037
Short name T54
Test name
Test status
Simulation time 1859259667 ps
CPU time 4.39 seconds
Started Aug 21 08:47:55 AM UTC 24
Finished Aug 21 08:48:01 AM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2734649037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_nack_acqfull_addr.2734649037
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.1136779666
Short name T1711
Test name
Test status
Simulation time 131439857 ps
CPU time 2.36 seconds
Started Aug 21 08:47:57 AM UTC 24
Finished Aug 21 08:48:00 AM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1136779666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_nack_txstretch.1136779666
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_perf.732230002
Short name T1705
Test name
Test status
Simulation time 543889983 ps
CPU time 6.58 seconds
Started Aug 21 08:47:47 AM UTC 24
Finished Aug 21 08:47:54 AM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=732230002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 49.i2c_target_perf.732230002
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.2832490786
Short name T1712
Test name
Test status
Simulation time 540111395 ps
CPU time 4.07 seconds
Started Aug 21 08:47:55 AM UTC 24
Finished Aug 21 08:48:00 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2832490786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_smbus_maxlen.2832490786
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.2133349735
Short name T1694
Test name
Test status
Simulation time 2849635641 ps
CPU time 9.82 seconds
Started Aug 21 08:47:32 AM UTC 24
Finished Aug 21 08:47:43 AM UTC 24
Peak memory 226948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2133349735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_targ
et_smoke.2133349735
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.836484109
Short name T1715
Test name
Test status
Simulation time 2023644946 ps
CPU time 33.6 seconds
Started Aug 21 08:47:34 AM UTC 24
Finished Aug 21 08:48:09 AM UTC 24
Peak memory 247936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=836484109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stress_rd.836484109
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.1509435976
Short name T1692
Test name
Test status
Simulation time 13607491850 ps
CPU time 7.23 seconds
Started Aug 21 08:47:34 AM UTC 24
Finished Aug 21 08:47:42 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1509435976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stress_wr.1509435976
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.1643278698
Short name T1697
Test name
Test status
Simulation time 4539886902 ps
CPU time 8.03 seconds
Started Aug 21 08:47:37 AM UTC 24
Finished Aug 21 08:47:46 AM UTC 24
Peak memory 227000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1643278698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_stretch.1643278698
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.3479749821
Short name T1702
Test name
Test status
Simulation time 24137716988 ps
CPU time 10.46 seconds
Started Aug 21 08:47:38 AM UTC 24
Finished Aug 21 08:47:50 AM UTC 24
Peak memory 233044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3479749821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_timeout.3479749821
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.2528698625
Short name T1708
Test name
Test status
Simulation time 115876497 ps
CPU time 4.16 seconds
Started Aug 21 08:47:52 AM UTC 24
Finished Aug 21 08:47:58 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2528698625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.2528698625
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_alert_test.1349897228
Short name T362
Test name
Test status
Simulation time 30083282 ps
CPU time 0.9 seconds
Started Aug 21 08:23:28 AM UTC 24
Finished Aug 21 08:23:29 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1349897228 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.1349897228
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.2480188787
Short name T20
Test name
Test status
Simulation time 346766019 ps
CPU time 2.14 seconds
Started Aug 21 08:23:13 AM UTC 24
Finished Aug 21 08:23:16 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2480188787 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2480188787
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.4274495903
Short name T372
Test name
Test status
Simulation time 391909161 ps
CPU time 20.64 seconds
Started Aug 21 08:23:10 AM UTC 24
Finished Aug 21 08:23:32 AM UTC 24
Peak memory 299288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4274495903 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.4274495903
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.1037122725
Short name T98
Test name
Test status
Simulation time 3866738859 ps
CPU time 102.95 seconds
Started Aug 21 08:23:12 AM UTC 24
Finished Aug 21 08:24:57 AM UTC 24
Peak memory 262340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1037122725 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1037122725
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.2026672836
Short name T210
Test name
Test status
Simulation time 2829136049 ps
CPU time 81.91 seconds
Started Aug 21 08:23:09 AM UTC 24
Finished Aug 21 08:24:33 AM UTC 24
Peak memory 884980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2026672836 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2026672836
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.2182019257
Short name T350
Test name
Test status
Simulation time 226962620 ps
CPU time 1.22 seconds
Started Aug 21 08:23:10 AM UTC 24
Finished Aug 21 08:23:13 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2182019257 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt.2182019257
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.4194233106
Short name T185
Test name
Test status
Simulation time 3219873622 ps
CPU time 6.53 seconds
Started Aug 21 08:23:11 AM UTC 24
Finished Aug 21 08:23:18 AM UTC 24
Peak memory 246000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4194233106 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.4194233106
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.1141883429
Short name T90
Test name
Test status
Simulation time 6275857129 ps
CPU time 65.27 seconds
Started Aug 21 08:23:09 AM UTC 24
Finished Aug 21 08:24:16 AM UTC 24
Peak memory 970828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1141883429 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1141883429
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.4273148088
Short name T276
Test name
Test status
Simulation time 296589830 ps
CPU time 11.47 seconds
Started Aug 21 08:23:24 AM UTC 24
Finished Aug 21 08:23:37 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4273148088 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.4273148088
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_override.3962312677
Short name T155
Test name
Test status
Simulation time 58978704 ps
CPU time 1.06 seconds
Started Aug 21 08:23:09 AM UTC 24
Finished Aug 21 08:23:11 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3962312677 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3962312677
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_perf.1463627078
Short name T260
Test name
Test status
Simulation time 8452260610 ps
CPU time 84.67 seconds
Started Aug 21 08:23:12 AM UTC 24
Finished Aug 21 08:24:38 AM UTC 24
Peak memory 372892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1463627078 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1463627078
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.1822530936
Short name T187
Test name
Test status
Simulation time 2535337437 ps
CPU time 46.49 seconds
Started Aug 21 08:23:12 AM UTC 24
Finished Aug 21 08:24:00 AM UTC 24
Peak memory 694372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1822530936 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.1822530936
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.1212269364
Short name T368
Test name
Test status
Simulation time 922944719 ps
CPU time 21.97 seconds
Started Aug 21 08:23:08 AM UTC 24
Finished Aug 21 08:23:31 AM UTC 24
Peak memory 292892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1212269364 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.1212269364
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.184861465
Short name T379
Test name
Test status
Simulation time 720792017 ps
CPU time 31.99 seconds
Started Aug 21 08:23:13 AM UTC 24
Finished Aug 21 08:23:46 AM UTC 24
Peak memory 227032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=184861465 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.184861465
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.4175854636
Short name T369
Test name
Test status
Simulation time 3252138352 ps
CPU time 9.18 seconds
Started Aug 21 08:23:22 AM UTC 24
Finished Aug 21 08:23:32 AM UTC 24
Peak memory 233760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=4175854636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.4175854636
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.1223926134
Short name T356
Test name
Test status
Simulation time 140690741 ps
CPU time 1.08 seconds
Started Aug 21 08:23:19 AM UTC 24
Finished Aug 21 08:23:22 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1223926134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_acq.1223926134
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.300781059
Short name T353
Test name
Test status
Simulation time 256127511 ps
CPU time 1.78 seconds
Started Aug 21 08:23:21 AM UTC 24
Finished Aug 21 08:23:23 AM UTC 24
Peak memory 226556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=300781059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 5.i2c_target_fifo_reset_tx.300781059
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.980932754
Short name T311
Test name
Test status
Simulation time 1924771836 ps
CPU time 5.11 seconds
Started Aug 21 08:23:24 AM UTC 24
Finished Aug 21 08:23:30 AM UTC 24
Peak memory 216716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=980932754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.980932754
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.3052503511
Short name T358
Test name
Test status
Simulation time 117444625 ps
CPU time 1.88 seconds
Started Aug 21 08:23:24 AM UTC 24
Finished Aug 21 08:23:27 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3052503511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.3052503511
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_hrst.1362960551
Short name T359
Test name
Test status
Simulation time 1067078701 ps
CPU time 3.42 seconds
Started Aug 21 08:23:23 AM UTC 24
Finished Aug 21 08:23:27 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1362960551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 5.i2c_target_hrst.1362960551
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.3777883283
Short name T354
Test name
Test status
Simulation time 2901985125 ps
CPU time 7.33 seconds
Started Aug 21 08:23:16 AM UTC 24
Finished Aug 21 08:23:25 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3777883283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.3777883283
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.3558535943
Short name T507
Test name
Test status
Simulation time 31972536393 ps
CPU time 152.55 seconds
Started Aug 21 08:23:17 AM UTC 24
Finished Aug 21 08:25:52 AM UTC 24
Peak memory 3168428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3558535943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3558535943
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.700567579
Short name T59
Test name
Test status
Simulation time 8275044506 ps
CPU time 4.96 seconds
Started Aug 21 08:23:25 AM UTC 24
Finished Aug 21 08:23:31 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=700567579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 5.i2c_target_nack_acqfull.700567579
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.21053762
Short name T363
Test name
Test status
Simulation time 1046639571 ps
CPU time 2.93 seconds
Started Aug 21 08:23:26 AM UTC 24
Finished Aug 21 08:23:30 AM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=21053762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_nack_acqfull_addr.21053762
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_perf.3408592826
Short name T331
Test name
Test status
Simulation time 4203987808 ps
CPU time 5.29 seconds
Started Aug 21 08:23:21 AM UTC 24
Finished Aug 21 08:23:27 AM UTC 24
Peak memory 231228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3408592826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 5.i2c_target_perf.3408592826
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.2441976702
Short name T361
Test name
Test status
Simulation time 607070342 ps
CPU time 2.95 seconds
Started Aug 21 08:23:25 AM UTC 24
Finished Aug 21 08:23:29 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2441976702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 5.i2c_target_smbus_maxlen.2441976702
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.3683471630
Short name T380
Test name
Test status
Simulation time 985475208 ps
CPU time 31.56 seconds
Started Aug 21 08:23:14 AM UTC 24
Finished Aug 21 08:23:47 AM UTC 24
Peak memory 226844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3683471630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targe
t_smoke.3683471630
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.248055603
Short name T265
Test name
Test status
Simulation time 41929808286 ps
CPU time 67.15 seconds
Started Aug 21 08:23:22 AM UTC 24
Finished Aug 21 08:24:30 AM UTC 24
Peak memory 692596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=248055603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_target_stress_all.248055603
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.3237945568
Short name T287
Test name
Test status
Simulation time 3356718509 ps
CPU time 13.21 seconds
Started Aug 21 08:23:14 AM UTC 24
Finished Aug 21 08:23:28 AM UTC 24
Peak memory 233764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3237945568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stress_rd.3237945568
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.1309164236
Short name T408
Test name
Test status
Simulation time 32606726576 ps
CPU time 56.79 seconds
Started Aug 21 08:23:14 AM UTC 24
Finished Aug 21 08:24:12 AM UTC 24
Peak memory 1073312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1309164236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stress_wr.1309164236
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.3346318228
Short name T357
Test name
Test status
Simulation time 1761968004 ps
CPU time 6.99 seconds
Started Aug 21 08:23:15 AM UTC 24
Finished Aug 21 08:23:23 AM UTC 24
Peak memory 299112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3346318228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_stretch.3346318228
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.70303022
Short name T322
Test name
Test status
Simulation time 4659605403 ps
CPU time 8.44 seconds
Started Aug 21 08:23:17 AM UTC 24
Finished Aug 21 08:23:27 AM UTC 24
Peak memory 243944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=70303022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_timeout.70303022
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.4235548231
Short name T365
Test name
Test status
Simulation time 185518498 ps
CPU time 4.63 seconds
Started Aug 21 08:23:25 AM UTC 24
Finished Aug 21 08:23:31 AM UTC 24
Peak memory 216540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4235548231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.4235548231
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_alert_test.1917617906
Short name T378
Test name
Test status
Simulation time 95017753 ps
CPU time 0.93 seconds
Started Aug 21 08:23:44 AM UTC 24
Finished Aug 21 08:23:46 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1917617906 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1917617906
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.1333452164
Short name T37
Test name
Test status
Simulation time 702711196 ps
CPU time 6.64 seconds
Started Aug 21 08:23:31 AM UTC 24
Finished Aug 21 08:23:39 AM UTC 24
Peak memory 237932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1333452164 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1333452164
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.2716227860
Short name T388
Test name
Test status
Simulation time 946419800 ps
CPU time 20.45 seconds
Started Aug 21 08:23:30 AM UTC 24
Finished Aug 21 08:23:52 AM UTC 24
Peak memory 309224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2716227860 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.2716227860
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.2310476636
Short name T188
Test name
Test status
Simulation time 7906001268 ps
CPU time 45 seconds
Started Aug 21 08:23:30 AM UTC 24
Finished Aug 21 08:24:17 AM UTC 24
Peak memory 327948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2310476636 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2310476636
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.1993074829
Short name T460
Test name
Test status
Simulation time 1714007940 ps
CPU time 101.56 seconds
Started Aug 21 08:23:29 AM UTC 24
Finished Aug 21 08:25:13 AM UTC 24
Peak memory 641100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1993074829 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1993074829
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.3838554042
Short name T371
Test name
Test status
Simulation time 135734497 ps
CPU time 1.32 seconds
Started Aug 21 08:23:30 AM UTC 24
Finished Aug 21 08:23:32 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3838554042 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.3838554042
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.4038513942
Short name T130
Test name
Test status
Simulation time 292118046 ps
CPU time 5.85 seconds
Started Aug 21 08:23:30 AM UTC 24
Finished Aug 21 08:23:37 AM UTC 24
Peak memory 240024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4038513942 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.4038513942
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.3862621705
Short name T627
Test name
Test status
Simulation time 18757995956 ps
CPU time 257.55 seconds
Started Aug 21 08:23:29 AM UTC 24
Finished Aug 21 08:27:50 AM UTC 24
Peak memory 1417692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3862621705 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3862621705
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_mode_toggle.733787978
Short name T31
Test name
Test status
Simulation time 105507844 ps
CPU time 2.02 seconds
Started Aug 21 08:23:39 AM UTC 24
Finished Aug 21 08:23:42 AM UTC 24
Peak memory 227096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=733787978 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.733787978
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_mode_toggle/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_override.1279928228
Short name T364
Test name
Test status
Simulation time 54392693 ps
CPU time 0.87 seconds
Started Aug 21 08:23:29 AM UTC 24
Finished Aug 21 08:23:31 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1279928228 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1279928228
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.4017841609
Short name T373
Test name
Test status
Simulation time 151885820 ps
CPU time 1.6 seconds
Started Aug 21 08:23:31 AM UTC 24
Finished Aug 21 08:23:34 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4017841609 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.4017841609
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.3413147131
Short name T453
Test name
Test status
Simulation time 2301863725 ps
CPU time 94.94 seconds
Started Aug 21 08:23:28 AM UTC 24
Finished Aug 21 08:25:05 AM UTC 24
Peak memory 428248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3413147131 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3413147131
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_stress_all.863469830
Short name T1717
Test name
Test status
Simulation time 118876031618 ps
CPU time 1673.46 seconds
Started Aug 21 08:23:32 AM UTC 24
Finished Aug 21 08:51:43 AM UTC 24
Peak memory 2754892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=863469830 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.863469830
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.1150507420
Short name T395
Test name
Test status
Simulation time 1774717638 ps
CPU time 30.52 seconds
Started Aug 21 08:23:31 AM UTC 24
Finished Aug 21 08:24:03 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1150507420 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1150507420
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.2537581548
Short name T385
Test name
Test status
Simulation time 6420490224 ps
CPU time 9.7 seconds
Started Aug 21 08:23:38 AM UTC 24
Finished Aug 21 08:23:49 AM UTC 24
Peak memory 232576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=2537581548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.2537581548
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.2079448427
Short name T132
Test name
Test status
Simulation time 228844891 ps
CPU time 2.53 seconds
Started Aug 21 08:23:35 AM UTC 24
Finished Aug 21 08:23:39 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2079448427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_acq.2079448427
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.3341780856
Short name T133
Test name
Test status
Simulation time 364950995 ps
CPU time 1.55 seconds
Started Aug 21 08:23:36 AM UTC 24
Finished Aug 21 08:23:39 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3341780856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_fifo_reset_tx.3341780856
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.3584693549
Short name T377
Test name
Test status
Simulation time 1390879807 ps
CPU time 2.5 seconds
Started Aug 21 08:23:40 AM UTC 24
Finished Aug 21 08:23:44 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3584693549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.3584693549
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.741050601
Short name T376
Test name
Test status
Simulation time 100828696 ps
CPU time 2.01 seconds
Started Aug 21 08:23:41 AM UTC 24
Finished Aug 21 08:23:44 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=741050601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.741050601
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.3887015322
Short name T135
Test name
Test status
Simulation time 2599986812 ps
CPU time 5.76 seconds
Started Aug 21 08:23:34 AM UTC 24
Finished Aug 21 08:23:41 AM UTC 24
Peak memory 233720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=3887015322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.3887015322
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.859309115
Short name T95
Test name
Test status
Simulation time 16610103723 ps
CPU time 79.58 seconds
Started Aug 21 08:23:34 AM UTC 24
Finished Aug 21 08:24:55 AM UTC 24
Peak memory 2033832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=859309115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.859309115
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.4187973029
Short name T382
Test name
Test status
Simulation time 2024415856 ps
CPU time 5.06 seconds
Started Aug 21 08:23:42 AM UTC 24
Finished Aug 21 08:23:48 AM UTC 24
Peak memory 226736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4187973029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_target_nack_acqfull.4187973029
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.1842920732
Short name T384
Test name
Test status
Simulation time 515114526 ps
CPU time 5.06 seconds
Started Aug 21 08:23:43 AM UTC 24
Finished Aug 21 08:23:49 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1842920732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_nack_acqfull_addr.1842920732
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_nack_txstretch.2630369739
Short name T201
Test name
Test status
Simulation time 552455695 ps
CPU time 2.08 seconds
Started Aug 21 08:23:43 AM UTC 24
Finished Aug 21 08:23:46 AM UTC 24
Peak memory 233756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2630369739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_nack_txstretch.2630369739
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_perf.313094185
Short name T136
Test name
Test status
Simulation time 451431123 ps
CPU time 3.88 seconds
Started Aug 21 08:23:37 AM UTC 24
Finished Aug 21 08:23:42 AM UTC 24
Peak memory 228856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=313094185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 6.i2c_target_perf.313094185
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.2844620299
Short name T381
Test name
Test status
Simulation time 4114275254 ps
CPU time 4.76 seconds
Started Aug 21 08:23:42 AM UTC 24
Finished Aug 21 08:23:47 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2844620299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_target_smbus_maxlen.2844620299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.558215401
Short name T134
Test name
Test status
Simulation time 1270229809 ps
CPU time 7.02 seconds
Started Aug 21 08:23:33 AM UTC 24
Finished Aug 21 08:23:41 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=558215401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target
_smoke.558215401
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_stress_all.2836080841
Short name T442
Test name
Test status
Simulation time 33276398286 ps
CPU time 70.99 seconds
Started Aug 21 08:23:38 AM UTC 24
Finished Aug 21 08:24:51 AM UTC 24
Peak memory 990880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2836080841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 6.i2c_target_stress_all.2836080841
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.1004789431
Short name T387
Test name
Test status
Simulation time 2958035179 ps
CPU time 16.27 seconds
Started Aug 21 08:23:33 AM UTC 24
Finished Aug 21 08:23:50 AM UTC 24
Peak memory 243948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1004789431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stress_rd.1004789431
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.1651924480
Short name T61
Test name
Test status
Simulation time 32544942163 ps
CPU time 19.07 seconds
Started Aug 21 08:23:33 AM UTC 24
Finished Aug 21 08:23:53 AM UTC 24
Peak memory 430236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1651924480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stress_wr.1651924480
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.3629237897
Short name T131
Test name
Test status
Simulation time 1214530233 ps
CPU time 4.67 seconds
Started Aug 21 08:23:33 AM UTC 24
Finished Aug 21 08:23:38 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3629237897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_stretch.3629237897
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.1230081582
Short name T375
Test name
Test status
Simulation time 1324720069 ps
CPU time 7.77 seconds
Started Aug 21 08:23:34 AM UTC 24
Finished Aug 21 08:23:43 AM UTC 24
Peak memory 233576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1230081582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_timeout.1230081582
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/6.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_alert_test.1910245655
Short name T406
Test name
Test status
Simulation time 33950687 ps
CPU time 0.82 seconds
Started Aug 21 08:24:07 AM UTC 24
Finished Aug 21 08:24:09 AM UTC 24
Peak memory 215408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1910245655 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1910245655
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_error_intr.4250797216
Short name T21
Test name
Test status
Simulation time 5358366853 ps
CPU time 9.93 seconds
Started Aug 21 08:23:50 AM UTC 24
Finished Aug 21 08:24:01 AM UTC 24
Peak memory 233816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4250797216 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.4250797216
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.4111392250
Short name T366
Test name
Test status
Simulation time 988480487 ps
CPU time 23.99 seconds
Started Aug 21 08:23:47 AM UTC 24
Finished Aug 21 08:24:12 AM UTC 24
Peak memory 327976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4111392250 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.4111392250
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_full.2119830017
Short name T35
Test name
Test status
Simulation time 13163128305 ps
CPU time 72.96 seconds
Started Aug 21 08:23:48 AM UTC 24
Finished Aug 21 08:25:03 AM UTC 24
Peak memory 346312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2119830017 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2119830017
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_overflow.3853770656
Short name T211
Test name
Test status
Simulation time 4344818923 ps
CPU time 58.6 seconds
Started Aug 21 08:23:47 AM UTC 24
Finished Aug 21 08:24:47 AM UTC 24
Peak memory 768196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3853770656 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3853770656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.4228701117
Short name T386
Test name
Test status
Simulation time 98124055 ps
CPU time 1.35 seconds
Started Aug 21 08:23:47 AM UTC 24
Finished Aug 21 08:23:50 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4228701117 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.4228701117
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.2826348200
Short name T389
Test name
Test status
Simulation time 879965941 ps
CPU time 4.02 seconds
Started Aug 21 08:23:47 AM UTC 24
Finished Aug 21 08:23:52 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2826348200 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.2826348200
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_watermark.3258085481
Short name T514
Test name
Test status
Simulation time 65244191577 ps
CPU time 129.98 seconds
Started Aug 21 08:23:45 AM UTC 24
Finished Aug 21 08:25:57 AM UTC 24
Peak memory 1552592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3258085481 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3258085481
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_override.2054327141
Short name T156
Test name
Test status
Simulation time 31420814 ps
CPU time 1.07 seconds
Started Aug 21 08:23:44 AM UTC 24
Finished Aug 21 08:23:46 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2054327141 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.2054327141
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_perf.3519233543
Short name T16
Test name
Test status
Simulation time 51610061834 ps
CPU time 114.81 seconds
Started Aug 21 08:23:48 AM UTC 24
Finished Aug 21 08:25:45 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3519233543 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3519233543
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.2740896649
Short name T390
Test name
Test status
Simulation time 199545976 ps
CPU time 3.7 seconds
Started Aug 21 08:23:48 AM UTC 24
Finished Aug 21 08:23:53 AM UTC 24
Peak memory 216500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2740896649 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.2740896649
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.2302243629
Short name T291
Test name
Test status
Simulation time 1732261290 ps
CPU time 31.7 seconds
Started Aug 21 08:23:44 AM UTC 24
Finished Aug 21 08:24:17 AM UTC 24
Peak memory 374928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2302243629 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2302243629
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_stress_all.2918971584
Short name T124
Test name
Test status
Simulation time 72570396219 ps
CPU time 428.36 seconds
Started Aug 21 08:23:50 AM UTC 24
Finished Aug 21 08:31:04 AM UTC 24
Peak memory 2771408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2918971584 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ea
rlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2918971584
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.1930761773
Short name T414
Test name
Test status
Simulation time 788084839 ps
CPU time 36.49 seconds
Started Aug 21 08:23:50 AM UTC 24
Finished Aug 21 08:24:27 AM UTC 24
Peak memory 226780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1930761773 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1930761773
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.3760279025
Short name T400
Test name
Test status
Simulation time 2990994799 ps
CPU time 7.37 seconds
Started Aug 21 08:23:59 AM UTC 24
Finished Aug 21 08:24:07 AM UTC 24
Peak memory 231132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=3760279025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3760279025
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.2265605021
Short name T177
Test name
Test status
Simulation time 301079049 ps
CPU time 1.85 seconds
Started Aug 21 08:23:54 AM UTC 24
Finished Aug 21 08:23:57 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2265605021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_acq.2265605021
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.847370828
Short name T202
Test name
Test status
Simulation time 636415627 ps
CPU time 2.19 seconds
Started Aug 21 08:23:56 AM UTC 24
Finished Aug 21 08:23:59 AM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=847370828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 7.i2c_target_fifo_reset_tx.847370828
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.1110363560
Short name T402
Test name
Test status
Simulation time 327680210 ps
CPU time 3.43 seconds
Started Aug 21 08:24:03 AM UTC 24
Finished Aug 21 08:24:07 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1110363560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.1110363560
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.2731403014
Short name T401
Test name
Test status
Simulation time 123041770 ps
CPU time 2 seconds
Started Aug 21 08:24:04 AM UTC 24
Finished Aug 21 08:24:07 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2731403014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.2731403014
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_hrst.2027273712
Short name T396
Test name
Test status
Simulation time 3368694272 ps
CPU time 3.68 seconds
Started Aug 21 08:23:59 AM UTC 24
Finished Aug 21 08:24:03 AM UTC 24
Peak memory 227144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2027273712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 7.i2c_target_hrst.2027273712
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.2776298917
Short name T397
Test name
Test status
Simulation time 891463004 ps
CPU time 9.79 seconds
Started Aug 21 08:23:53 AM UTC 24
Finished Aug 21 08:24:04 AM UTC 24
Peak memory 233512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=2776298917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_intr_smoke.2776298917
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.3896043432
Short name T462
Test name
Test status
Simulation time 13188012757 ps
CPU time 78.26 seconds
Started Aug 21 08:23:53 AM UTC 24
Finished Aug 21 08:25:13 AM UTC 24
Peak memory 1730796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3896043432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3896043432
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull.3506859642
Short name T391
Test name
Test status
Simulation time 1947575663 ps
CPU time 4.76 seconds
Started Aug 21 08:24:05 AM UTC 24
Finished Aug 21 08:24:11 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3506859642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 7.i2c_target_nack_acqfull.3506859642
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.3350567818
Short name T374
Test name
Test status
Simulation time 1120710798 ps
CPU time 5.18 seconds
Started Aug 21 08:24:06 AM UTC 24
Finished Aug 21 08:24:13 AM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3350567818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_nack_acqfull_addr.3350567818
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_nack_txstretch.3168476833
Short name T203
Test name
Test status
Simulation time 729246890 ps
CPU time 2.1 seconds
Started Aug 21 08:24:07 AM UTC 24
Finished Aug 21 08:24:11 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3168476833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_nack_txstretch.3168476833
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_perf.2553582739
Short name T399
Test name
Test status
Simulation time 2749161288 ps
CPU time 8.01 seconds
Started Aug 21 08:23:57 AM UTC 24
Finished Aug 21 08:24:06 AM UTC 24
Peak memory 233032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2553582739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 7.i2c_target_perf.2553582739
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.1616535824
Short name T403
Test name
Test status
Simulation time 357020427 ps
CPU time 3.02 seconds
Started Aug 21 08:24:04 AM UTC 24
Finished Aug 21 08:24:08 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1616535824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 7.i2c_target_smbus_maxlen.1616535824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.556889163
Short name T404
Test name
Test status
Simulation time 3707803569 ps
CPU time 17.33 seconds
Started Aug 21 08:23:50 AM UTC 24
Finished Aug 21 08:24:08 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=556889163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target
_smoke.556889163
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.1171574887
Short name T239
Test name
Test status
Simulation time 62870743335 ps
CPU time 282.31 seconds
Started Aug 21 08:23:57 AM UTC 24
Finished Aug 21 08:28:43 AM UTC 24
Peak memory 2199980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1171574887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 7.i2c_target_stress_all.1171574887
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.1851980649
Short name T392
Test name
Test status
Simulation time 1397189680 ps
CPU time 20.33 seconds
Started Aug 21 08:23:51 AM UTC 24
Finished Aug 21 08:24:12 AM UTC 24
Peak memory 235664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1851980649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stress_rd.1851980649
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_stress_wr.3646012870
Short name T481
Test name
Test status
Simulation time 53282668425 ps
CPU time 100.08 seconds
Started Aug 21 08:23:51 AM UTC 24
Finished Aug 21 08:25:33 AM UTC 24
Peak memory 1954084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3646012870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stress_wr.3646012870
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.4163712045
Short name T393
Test name
Test status
Simulation time 2867967448 ps
CPU time 6.71 seconds
Started Aug 21 08:23:51 AM UTC 24
Finished Aug 21 08:23:59 AM UTC 24
Peak memory 231060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4163712045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_stretch.4163712045
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.3345534625
Short name T398
Test name
Test status
Simulation time 7341857276 ps
CPU time 10.25 seconds
Started Aug 21 08:23:54 AM UTC 24
Finished Aug 21 08:24:06 AM UTC 24
Peak memory 233768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3345534625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_timeout.3345534625
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/7.i2c_target_tx_stretch_ctrl.3575531851
Short name T405
Test name
Test status
Simulation time 151380552 ps
CPU time 3.87 seconds
Started Aug 21 08:24:04 AM UTC 24
Finished Aug 21 08:24:09 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3575531851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.3575531851
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_alert_test.207180907
Short name T426
Test name
Test status
Simulation time 51480295 ps
CPU time 0.81 seconds
Started Aug 21 08:24:33 AM UTC 24
Finished Aug 21 08:24:35 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=207180907 -assert n
opostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.207180907
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_fmt_empty.782580960
Short name T412
Test name
Test status
Simulation time 1071318626 ps
CPU time 14.87 seconds
Started Aug 21 08:24:10 AM UTC 24
Finished Aug 21 08:24:26 AM UTC 24
Peak memory 274728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=782580960 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.782580960
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.1569262065
Short name T478
Test name
Test status
Simulation time 9638270369 ps
CPU time 72.65 seconds
Started Aug 21 08:24:12 AM UTC 24
Finished Aug 21 08:25:26 AM UTC 24
Peak memory 704800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1569262065 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1569262065
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.2201878935
Short name T532
Test name
Test status
Simulation time 28552570206 ps
CPU time 121.12 seconds
Started Aug 21 08:24:10 AM UTC 24
Finished Aug 21 08:26:13 AM UTC 24
Peak memory 729276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2201878935 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2201878935
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.630969319
Short name T407
Test name
Test status
Simulation time 125521781 ps
CPU time 1.75 seconds
Started Aug 21 08:24:10 AM UTC 24
Finished Aug 21 08:24:12 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=630969319 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.630969319
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.1463725624
Short name T411
Test name
Test status
Simulation time 544161197 ps
CPU time 11.17 seconds
Started Aug 21 08:24:12 AM UTC 24
Finished Aug 21 08:24:24 AM UTC 24
Peak memory 241812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1463725624 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.1463725624
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.4031264578
Short name T534
Test name
Test status
Simulation time 9675677652 ps
CPU time 122.21 seconds
Started Aug 21 08:24:09 AM UTC 24
Finished Aug 21 08:26:13 AM UTC 24
Peak memory 1427536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4031264578 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.4031264578
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_may_nack.4058245160
Short name T437
Test name
Test status
Simulation time 647388842 ps
CPU time 14.42 seconds
Started Aug 21 08:24:28 AM UTC 24
Finished Aug 21 08:24:44 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4058245160 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.4058245160
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_override.3890615002
Short name T157
Test name
Test status
Simulation time 44120581 ps
CPU time 1.03 seconds
Started Aug 21 08:24:08 AM UTC 24
Finished Aug 21 08:24:11 AM UTC 24
Peak memory 214992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3890615002 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3890615002
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.446508745
Short name T394
Test name
Test status
Simulation time 106980919 ps
CPU time 2.4 seconds
Started Aug 21 08:24:12 AM UTC 24
Finished Aug 21 08:24:15 AM UTC 24
Peak memory 216732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=446508745 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/e
arlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.446508745
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.3475822445
Short name T455
Test name
Test status
Simulation time 2640456203 ps
CPU time 56.98 seconds
Started Aug 21 08:24:07 AM UTC 24
Finished Aug 21 08:25:06 AM UTC 24
Peak memory 293068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3475822445 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.3475822445
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.3023427963
Short name T415
Test name
Test status
Simulation time 617213291 ps
CPU time 14.31 seconds
Started Aug 21 08:24:13 AM UTC 24
Finished Aug 21 08:24:29 AM UTC 24
Peak memory 230940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3023427963 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3023427963
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.2267096427
Short name T422
Test name
Test status
Simulation time 3476457687 ps
CPU time 7.18 seconds
Started Aug 21 08:24:24 AM UTC 24
Finished Aug 21 08:24:32 AM UTC 24
Peak memory 226960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=2267096427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2267096427
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.2595541220
Short name T204
Test name
Test status
Simulation time 250465588 ps
CPU time 3.08 seconds
Started Aug 21 08:24:19 AM UTC 24
Finished Aug 21 08:24:23 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2595541220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_acq.2595541220
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_tx.2117600481
Short name T410
Test name
Test status
Simulation time 433766595 ps
CPU time 1.58 seconds
Started Aug 21 08:24:20 AM UTC 24
Finished Aug 21 08:24:23 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2117600481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_fifo_reset_tx.2117600481
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.998871386
Short name T419
Test name
Test status
Simulation time 275397420 ps
CPU time 2.14 seconds
Started Aug 21 08:24:29 AM UTC 24
Finished Aug 21 08:24:32 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=998871386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.998871386
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.3217343936
Short name T205
Test name
Test status
Simulation time 631463792 ps
CPU time 1.85 seconds
Started Aug 21 08:24:30 AM UTC 24
Finished Aug 21 08:24:33 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3217343936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.3217343936
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_hrst.641142354
Short name T383
Test name
Test status
Simulation time 1536666068 ps
CPU time 2.83 seconds
Started Aug 21 08:24:24 AM UTC 24
Finished Aug 21 08:24:28 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=641142354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.i2c_target_hrst.641142354
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.808791641
Short name T418
Test name
Test status
Simulation time 14090431178 ps
CPU time 11.3 seconds
Started Aug 21 08:24:18 AM UTC 24
Finished Aug 21 08:24:30 AM UTC 24
Peak memory 226904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=808791641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_intr_smoke.808791641
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.3224344334
Short name T663
Test name
Test status
Simulation time 19934257149 ps
CPU time 239.14 seconds
Started Aug 21 08:24:18 AM UTC 24
Finished Aug 21 08:28:20 AM UTC 24
Peak memory 3403884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3224344334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.3224344334
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.2319460125
Short name T430
Test name
Test status
Simulation time 2202237960 ps
CPU time 4.01 seconds
Started Aug 21 08:24:31 AM UTC 24
Finished Aug 21 08:24:36 AM UTC 24
Peak memory 227196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2319460125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 8.i2c_target_nack_acqfull.2319460125
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.3160844789
Short name T427
Test name
Test status
Simulation time 372798378 ps
CPU time 2.81 seconds
Started Aug 21 08:24:31 AM UTC 24
Finished Aug 21 08:24:35 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3160844789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_nack_acqfull_addr.3160844789
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_perf.247965184
Short name T421
Test name
Test status
Simulation time 3717759184 ps
CPU time 10.15 seconds
Started Aug 21 08:24:21 AM UTC 24
Finished Aug 21 08:24:32 AM UTC 24
Peak memory 233704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=247965184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.i2c_target_perf.247965184
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.940937213
Short name T431
Test name
Test status
Simulation time 4187858858 ps
CPU time 4.63 seconds
Started Aug 21 08:24:31 AM UTC 24
Finished Aug 21 08:24:37 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=940937213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 8.i2c_target_smbus_maxlen.940937213
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.919203555
Short name T416
Test name
Test status
Simulation time 1687093798 ps
CPU time 14.84 seconds
Started Aug 21 08:24:13 AM UTC 24
Finished Aug 21 08:24:29 AM UTC 24
Peak memory 233832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=919203555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target
_smoke.919203555
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.1206177358
Short name T945
Test name
Test status
Simulation time 38522845445 ps
CPU time 518.05 seconds
Started Aug 21 08:24:23 AM UTC 24
Finished Aug 21 08:33:07 AM UTC 24
Peak memory 6308132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=1206177358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 8.i2c_target_stress_all.1206177358
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.1743408753
Short name T441
Test name
Test status
Simulation time 1392682929 ps
CPU time 32.5 seconds
Started Aug 21 08:24:15 AM UTC 24
Finished Aug 21 08:24:49 AM UTC 24
Peak memory 243804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1743408753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stress_rd.1743408753
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.3018842811
Short name T880
Test name
Test status
Simulation time 41617783883 ps
CPU time 478.99 seconds
Started Aug 21 08:24:13 AM UTC 24
Finished Aug 21 08:32:18 AM UTC 24
Peak memory 5370084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=3018842811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stress_wr.3018842811
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.252747159
Short name T413
Test name
Test status
Simulation time 1356189261 ps
CPU time 8.3 seconds
Started Aug 21 08:24:18 AM UTC 24
Finished Aug 21 08:24:27 AM UTC 24
Peak memory 230956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=252747159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_timeout.252747159
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/8.i2c_target_tx_stretch_ctrl.2113112969
Short name T424
Test name
Test status
Simulation time 118024828 ps
CPU time 2.74 seconds
Started Aug 21 08:24:30 AM UTC 24
Finished Aug 21 08:24:34 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2113112969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.2113112969
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_alert_test.48699690
Short name T102
Test name
Test status
Simulation time 49085487 ps
CPU time 0.96 seconds
Started Aug 21 08:24:58 AM UTC 24
Finished Aug 21 08:25:00 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=48699690 -assert no
postproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.48699690
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.104348223
Short name T433
Test name
Test status
Simulation time 170587630 ps
CPU time 1.86 seconds
Started Aug 21 08:24:37 AM UTC 24
Finished Aug 21 08:24:40 AM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=104348223 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.104348223
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_error_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.953694927
Short name T436
Test name
Test status
Simulation time 260624422 ps
CPU time 7.79 seconds
Started Aug 21 08:24:34 AM UTC 24
Finished Aug 21 08:24:44 AM UTC 24
Peak memory 270364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=953694927 -assert
nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.953694927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.2358478004
Short name T545
Test name
Test status
Simulation time 14575056362 ps
CPU time 112.06 seconds
Started Aug 21 08:24:34 AM UTC 24
Finished Aug 21 08:26:29 AM UTC 24
Peak memory 475412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2358478004 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/ear
lgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2358478004
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_fifo_full/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.3597678440
Short name T495
Test name
Test status
Simulation time 6214354100 ps
CPU time 71.19 seconds
Started Aug 21 08:24:33 AM UTC 24
Finished Aug 21 08:25:46 AM UTC 24
Peak memory 563692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3597678440 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3597678440
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_fifo_overflow/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.1519101625
Short name T432
Test name
Test status
Simulation time 85487554 ps
CPU time 1.4 seconds
Started Aug 21 08:24:34 AM UTC 24
Finished Aug 21 08:24:37 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1519101625 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.1519101625
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.2026813373
Short name T435
Test name
Test status
Simulation time 306798066 ps
CPU time 5.8 seconds
Started Aug 21 08:24:34 AM UTC 24
Finished Aug 21 08:24:42 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=
1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2026813373 -asser
t nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.2026813373
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_fifo_reset_rx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.2344052705
Short name T622
Test name
Test status
Simulation time 3680761995 ps
CPU time 189.89 seconds
Started Aug 21 08:24:33 AM UTC 24
Finished Aug 21 08:27:46 AM UTC 24
Peak memory 1118456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2344052705 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2344052705
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_fifo_watermark/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.2001532082
Short name T280
Test name
Test status
Simulation time 455736552 ps
CPU time 7.94 seconds
Started Aug 21 08:24:55 AM UTC 24
Finished Aug 21 08:25:04 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2001532082 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2001532082
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_may_nack/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_override.4199574290
Short name T428
Test name
Test status
Simulation time 45575734 ps
CPU time 0.94 seconds
Started Aug 21 08:24:33 AM UTC 24
Finished Aug 21 08:24:35 AM UTC 24
Peak memory 215128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4199574290 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earl
grey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.4199574290
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_override/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_perf.2308995120
Short name T454
Test name
Test status
Simulation time 6049658535 ps
CPU time 28.35 seconds
Started Aug 21 08:24:35 AM UTC 24
Finished Aug 21 08:25:05 AM UTC 24
Peak memory 397644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2308995120 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2308995120
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.1007713838
Short name T434
Test name
Test status
Simulation time 94132724 ps
CPU time 3.1 seconds
Started Aug 21 08:24:36 AM UTC 24
Finished Aug 21 08:24:41 AM UTC 24
Peak memory 233384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1007713838 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/
earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.1007713838
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_perf_precise/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.2483727115
Short name T452
Test name
Test status
Simulation time 6528184516 ps
CPU time 28.35 seconds
Started Aug 21 08:24:33 AM UTC 24
Finished Aug 21 08:25:03 AM UTC 24
Peak memory 364916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2483727115 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2483727115
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.1128445927
Short name T459
Test name
Test status
Simulation time 2684350411 ps
CPU time 33.17 seconds
Started Aug 21 08:24:37 AM UTC 24
Finished Aug 21 08:25:11 AM UTC 24
Peak memory 226964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1128445927 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1128445927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_host_stretch_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.807158760
Short name T100
Test name
Test status
Simulation time 753598791 ps
CPU time 7.89 seconds
Started Aug 21 08:24:48 AM UTC 24
Finished Aug 21 08:24:57 AM UTC 24
Peak memory 227028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/op
entitan/hw/dv/tools/sim.tcl +ntb_random_seed=807158760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_bad_addr.807158760
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_bad_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_acq.3736806538
Short name T440
Test name
Test status
Simulation time 561723977 ps
CPU time 1.9 seconds
Started Aug 21 08:24:45 AM UTC 24
Finished Aug 21 08:24:48 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3736806538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_acq.3736806538
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_fifo_reset_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_tx.1984682648
Short name T183
Test name
Test status
Simulation time 378535039 ps
CPU time 2.46 seconds
Started Aug 21 08:24:48 AM UTC 24
Finished Aug 21 08:24:52 AM UTC 24
Peak memory 216468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1984682648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_fifo_reset_tx.1984682648
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_fifo_reset_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_acq.1772573239
Short name T444
Test name
Test status
Simulation time 3182882969 ps
CPU time 3.76 seconds
Started Aug 21 08:24:56 AM UTC 24
Finished Aug 21 08:25:01 AM UTC 24
Peak memory 216672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1772573239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.1772573239
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.701467580
Short name T101
Test name
Test status
Simulation time 139360176 ps
CPU time 2.55 seconds
Started Aug 21 08:24:56 AM UTC 24
Finished Aug 21 08:25:00 AM UTC 24
Peak memory 216228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=701467580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.701467580
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_hrst.1678955132
Short name T443
Test name
Test status
Simulation time 495873939 ps
CPU time 2.99 seconds
Started Aug 21 08:24:50 AM UTC 24
Finished Aug 21 08:24:54 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=1678955132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 9.i2c_target_hrst.1678955132
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_hrst/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.837269254
Short name T439
Test name
Test status
Simulation time 2781888703 ps
CPU time 4.39 seconds
Started Aug 21 08:24:42 AM UTC 24
Finished Aug 21 08:24:47 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=837269254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_intr_smoke.837269254
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_intr_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.1358843515
Short name T446
Test name
Test status
Simulation time 5328056337 ps
CPU time 17.31 seconds
Started Aug 21 08:24:43 AM UTC 24
Finished Aug 21 08:25:02 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_in
tr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1358843515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.1358843515
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.2353011100
Short name T449
Test name
Test status
Simulation time 2178074483 ps
CPU time 4.02 seconds
Started Aug 21 08:24:57 AM UTC 24
Finished Aug 21 08:25:02 AM UTC 24
Peak memory 227132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2353011100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 9.i2c_target_nack_acqfull.2353011100
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_nack_acqfull/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.938930132
Short name T451
Test name
Test status
Simulation time 497084270 ps
CPU time 3.59 seconds
Started Aug 21 08:24:58 AM UTC 24
Finished Aug 21 08:25:03 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=938930132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_nack_acqfull_addr.938930132
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_nack_txstretch.549247106
Short name T447
Test name
Test status
Simulation time 873457153 ps
CPU time 2.31 seconds
Started Aug 21 08:24:58 AM UTC 24
Finished Aug 21 08:25:02 AM UTC 24
Peak memory 233552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=549247106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_nack_txstretch.549247106
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_perf.4159423066
Short name T97
Test name
Test status
Simulation time 2269774595 ps
CPU time 6.34 seconds
Started Aug 21 08:24:48 AM UTC 24
Finished Aug 21 08:24:56 AM UTC 24
Peak memory 227132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=4159423066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 9.i2c_target_perf.4159423066
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_perf/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.341007512
Short name T445
Test name
Test status
Simulation time 2184033119 ps
CPU time 2.86 seconds
Started Aug 21 08:24:57 AM UTC 24
Finished Aug 21 08:25:01 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=341007512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 9.i2c_target_smbus_maxlen.341007512
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_smbus_maxlen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.4197300051
Short name T93
Test name
Test status
Simulation time 2076287558 ps
CPU time 15.84 seconds
Started Aug 21 08:24:38 AM UTC 24
Finished Aug 21 08:24:55 AM UTC 24
Peak memory 230756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=4197300051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targe
t_smoke.4197300051
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.127432604
Short name T466
Test name
Test status
Simulation time 20409138978 ps
CPU time 30.91 seconds
Started Aug 21 08:24:48 AM UTC 24
Finished Aug 21 08:25:21 AM UTC 24
Peak memory 293152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_in
tr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/
sim.tcl +ntb_random_seed=127432604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_stress_all.127432604
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.1011593931
Short name T438
Test name
Test status
Simulation time 256561421 ps
CPU time 3.89 seconds
Started Aug 21 08:24:39 AM UTC 24
Finished Aug 21 08:24:44 AM UTC 24
Peak memory 216472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=1011593931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stress_rd.1011593931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_stress_rd/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.294159921
Short name T1522
Test name
Test status
Simulation time 60507181562 ps
CPU time 1179.46 seconds
Started Aug 21 08:24:38 AM UTC 24
Finished Aug 21 08:44:29 AM UTC 24
Peak memory 10123676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=294159921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stress_wr.294159921
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_stress_wr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.2953195780
Short name T601
Test name
Test status
Simulation time 3895709674 ps
CPU time 171.3 seconds
Started Aug 21 08:24:41 AM UTC 24
Finished Aug 21 08:27:35 AM UTC 24
Peak memory 1138956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_
seed=2953195780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_stretch.2953195780
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_stretch/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.3927784606
Short name T99
Test name
Test status
Simulation time 2302994952 ps
CPU time 11.86 seconds
Started Aug 21 08:24:44 AM UTC 24
Finished Aug 21 08:24:57 AM UTC 24
Peak memory 233032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=3927784606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_timeout.3927784606
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_timeout/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.2565731197
Short name T448
Test name
Test status
Simulation time 135121812 ps
CPU time 3.56 seconds
Started Aug 21 08:24:57 AM UTC 24
Finished Aug 21 08:25:02 AM UTC 24
Peak memory 216668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_int
r_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/s
im.tcl +ntb_random_seed=2565731197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.2565731197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest
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