Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
15 |
0 |
15 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[1] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[2] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[3] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[4] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[5] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[6] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[7] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[8] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[9] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[10] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[11] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[12] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[13] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[14] |
743970 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9195688 |
1 |
|
|
T1 |
15 |
|
T2 |
30 |
|
T3 |
135 |
auto[1] |
1963862 |
1 |
|
|
T4 |
5 |
|
T5 |
5 |
|
T6 |
4 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10738849 |
1 |
|
|
T1 |
15 |
|
T2 |
30 |
|
T3 |
135 |
auto[1] |
420701 |
1 |
|
|
T18 |
69 |
|
T198 |
2897 |
|
T125 |
53985 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
60 |
7 |
53 |
88.33 |
7 |
Automatically Generated Cross Bins for intr_cg_cc
Uncovered bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER | STATUS |
[all_values[3]] |
[auto[1]] |
[auto[0]] |
0 |
1 |
1 |
|
[all_values[5] , all_values[6]] |
[auto[1]] |
[auto[0]] |
-- |
-- |
2 |
|
[all_values[8]] |
[auto[1]] |
[auto[0]] |
0 |
1 |
1 |
|
[all_values[10]] |
[auto[1]] |
[auto[0]] |
0 |
1 |
1 |
|
[all_values[13] , all_values[14]] |
[auto[1]] |
[auto[0]] |
-- |
-- |
2 |
|
Covered bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
100321 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[0] |
auto[0] |
auto[1] |
6717 |
1 |
|
|
T18 |
4 |
|
T198 |
14 |
|
T125 |
325 |
all_values[0] |
auto[1] |
auto[0] |
615249 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
2 |
all_values[0] |
auto[1] |
auto[1] |
21683 |
1 |
|
|
T18 |
2 |
|
T198 |
228 |
|
T125 |
3275 |
all_values[1] |
auto[0] |
auto[0] |
715306 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[1] |
auto[0] |
auto[1] |
28247 |
1 |
|
|
T198 |
239 |
|
T125 |
3596 |
|
T199 |
324 |
all_values[1] |
auto[1] |
auto[0] |
292 |
1 |
|
|
T27 |
2 |
|
T133 |
3 |
|
T280 |
7 |
all_values[1] |
auto[1] |
auto[1] |
125 |
1 |
|
|
T198 |
1 |
|
T125 |
2 |
|
T199 |
4 |
all_values[2] |
auto[0] |
auto[0] |
715394 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[2] |
auto[0] |
auto[1] |
28250 |
1 |
|
|
T198 |
240 |
|
T125 |
3595 |
|
T199 |
323 |
all_values[2] |
auto[1] |
auto[0] |
187 |
1 |
|
|
T167 |
1 |
|
T207 |
2 |
|
T65 |
1 |
all_values[2] |
auto[1] |
auto[1] |
139 |
1 |
|
|
T198 |
1 |
|
T125 |
5 |
|
T199 |
5 |
all_values[3] |
auto[0] |
auto[0] |
715559 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[3] |
auto[0] |
auto[1] |
28247 |
1 |
|
|
T18 |
3 |
|
T198 |
238 |
|
T125 |
3596 |
all_values[3] |
auto[1] |
auto[1] |
164 |
1 |
|
|
T18 |
3 |
|
T198 |
2 |
|
T125 |
1 |
all_values[4] |
auto[0] |
auto[0] |
715802 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[4] |
auto[0] |
auto[1] |
28000 |
1 |
|
|
T18 |
3 |
|
T125 |
3595 |
|
T199 |
321 |
all_values[4] |
auto[1] |
auto[0] |
16 |
1 |
|
|
T263 |
2 |
|
T281 |
2 |
|
T265 |
1 |
all_values[4] |
auto[1] |
auto[1] |
152 |
1 |
|
|
T18 |
2 |
|
T125 |
5 |
|
T199 |
7 |
all_values[5] |
auto[0] |
auto[0] |
715560 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[5] |
auto[0] |
auto[1] |
28227 |
1 |
|
|
T18 |
5 |
|
T198 |
238 |
|
T125 |
3598 |
all_values[5] |
auto[1] |
auto[1] |
183 |
1 |
|
|
T18 |
1 |
|
T198 |
4 |
|
T125 |
1 |
all_values[6] |
auto[0] |
auto[0] |
715811 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[6] |
auto[0] |
auto[1] |
27966 |
1 |
|
|
T18 |
5 |
|
T125 |
3596 |
|
T199 |
323 |
all_values[6] |
auto[1] |
auto[1] |
193 |
1 |
|
|
T125 |
3 |
|
T199 |
5 |
|
T282 |
6 |
all_values[7] |
auto[0] |
auto[0] |
685077 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[7] |
auto[0] |
auto[1] |
26396 |
1 |
|
|
T198 |
177 |
|
T125 |
3447 |
|
T199 |
232 |
all_values[7] |
auto[1] |
auto[0] |
30486 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T14 |
240 |
all_values[7] |
auto[1] |
auto[1] |
2011 |
1 |
|
|
T198 |
65 |
|
T125 |
152 |
|
T199 |
96 |
all_values[8] |
auto[0] |
auto[0] |
715562 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[8] |
auto[0] |
auto[1] |
28220 |
1 |
|
|
T18 |
4 |
|
T198 |
240 |
|
T125 |
3594 |
all_values[8] |
auto[1] |
auto[1] |
188 |
1 |
|
|
T18 |
2 |
|
T198 |
1 |
|
T125 |
6 |
all_values[9] |
auto[0] |
auto[0] |
185001 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[9] |
auto[0] |
auto[1] |
8106 |
1 |
|
|
T18 |
4 |
|
T198 |
234 |
|
T125 |
82 |
all_values[9] |
auto[1] |
auto[0] |
530580 |
1 |
|
|
T5 |
1 |
|
T7 |
1 |
|
T14 |
5075 |
all_values[9] |
auto[1] |
auto[1] |
20283 |
1 |
|
|
T18 |
2 |
|
T198 |
8 |
|
T125 |
3517 |
all_values[10] |
auto[0] |
auto[0] |
715586 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[10] |
auto[0] |
auto[1] |
28250 |
1 |
|
|
T18 |
4 |
|
T198 |
240 |
|
T125 |
3594 |
all_values[10] |
auto[1] |
auto[1] |
134 |
1 |
|
|
T18 |
1 |
|
T198 |
2 |
|
T125 |
3 |
all_values[11] |
auto[0] |
auto[0] |
2412 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[11] |
auto[0] |
auto[1] |
297 |
1 |
|
|
T18 |
4 |
|
T198 |
7 |
|
T125 |
14 |
all_values[11] |
auto[1] |
auto[0] |
713154 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
2 |
all_values[11] |
auto[1] |
auto[1] |
28107 |
1 |
|
|
T18 |
2 |
|
T198 |
234 |
|
T125 |
3586 |
all_values[12] |
auto[0] |
auto[0] |
720038 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[12] |
auto[0] |
auto[1] |
23736 |
1 |
|
|
T18 |
4 |
|
T198 |
239 |
|
T125 |
3594 |
all_values[12] |
auto[1] |
auto[0] |
61 |
1 |
|
|
T65 |
1 |
|
T71 |
1 |
|
T72 |
1 |
all_values[12] |
auto[1] |
auto[1] |
135 |
1 |
|
|
T18 |
2 |
|
T198 |
3 |
|
T125 |
5 |
all_values[13] |
auto[0] |
auto[0] |
715593 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[13] |
auto[0] |
auto[1] |
28221 |
1 |
|
|
T18 |
2 |
|
T198 |
240 |
|
T125 |
3596 |
all_values[13] |
auto[1] |
auto[1] |
156 |
1 |
|
|
T18 |
4 |
|
T198 |
2 |
|
T125 |
2 |
all_values[14] |
auto[0] |
auto[0] |
715802 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
9 |
all_values[14] |
auto[0] |
auto[1] |
27984 |
1 |
|
|
T18 |
3 |
|
T125 |
3595 |
|
T199 |
320 |
all_values[14] |
auto[1] |
auto[1] |
184 |
1 |
|
|
T18 |
3 |
|
T125 |
5 |
|
T199 |
7 |