Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	743970	1			T1	1		T2	2		T3	9
all_pins[1]	743970	1			T1	1		T2	2		T3	9
all_pins[2]	743970	1			T1	1		T2	2		T3	9
all_pins[3]	743970	1			T1	1		T2	2		T3	9
all_pins[4]	743970	1			T1	1		T2	2		T3	9
all_pins[5]	743970	1			T1	1		T2	2		T3	9
all_pins[6]	743970	1			T1	1		T2	2		T3	9
all_pins[7]	743970	1			T1	1		T2	2		T3	9
all_pins[8]	743970	1			T1	1		T2	2		T3	9
all_pins[9]	743970	1			T1	1		T2	2		T3	9
all_pins[10]	743970	1			T1	1		T2	2		T3	9
all_pins[11]	743970	1			T1	1		T2	2		T3	9
all_pins[12]	743970	1			T1	1		T2	2		T3	9
all_pins[13]	743970	1			T1	1		T2	2		T3	9
all_pins[14]	743970	1			T1	1		T2	2		T3	9

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9201827	1			T1	15		T2	30		T3	135
values[0x1]	1957723	1			T4	5		T5	5		T6	4
transitions[0x0=>0x1]	1957069	1			T4	5		T5	5		T6	4
transitions[0x1=>0x0]	1955768	1			T4	4		T5	4		T6	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	110511	1			T1	1		T2	2		T3	9
all_pins[0]	values[0x1]	633459	1			T4	2		T5	2		T6	2
all_pins[0]	transitions[0x0=>0x1]	633107	1			T4	2		T5	2		T6	2
all_pins[0]	transitions[0x1=>0x0]	48	1			T290	1		T291	1		T199	2
all_pins[1]	values[0x0]	743570	1			T1	1		T2	2		T3	9
all_pins[1]	values[0x1]	400	1			T27	2		T133	4		T280	9
all_pins[1]	transitions[0x0=>0x1]	393	1			T27	2		T133	4		T280	9
all_pins[1]	transitions[0x1=>0x0]	111	1			T167	1		T184	1		T134	1
all_pins[2]	values[0x0]	743852	1			T1	1		T2	2		T3	9
all_pins[2]	values[0x1]	118	1			T167	1		T184	1		T134	1
all_pins[2]	transitions[0x0=>0x1]	105	1			T167	1		T184	1		T134	1
all_pins[2]	transitions[0x1=>0x0]	72	1			T18	2		T198	2		T282	2
all_pins[3]	values[0x0]	743885	1			T1	1		T2	2		T3	9
all_pins[3]	values[0x1]	85	1			T18	2		T198	2		T125	1
all_pins[3]	transitions[0x0=>0x1]	69	1			T18	2		T198	2		T282	2
all_pins[3]	transitions[0x1=>0x0]	74	1			T263	2		T281	2		T265	2
all_pins[4]	values[0x0]	743880	1			T1	1		T2	2		T3	9
all_pins[4]	values[0x1]	90	1			T263	2		T281	2		T265	2
all_pins[4]	transitions[0x0=>0x1]	71	1			T263	2		T281	2		T265	2
all_pins[4]	transitions[0x1=>0x0]	86	1			T18	1		T198	3		T199	2
all_pins[5]	values[0x0]	743865	1			T1	1		T2	2		T3	9
all_pins[5]	values[0x1]	105	1			T18	1		T198	3		T125	1
all_pins[5]	transitions[0x0=>0x1]	76	1			T18	1		T198	3		T125	1
all_pins[5]	transitions[0x1=>0x0]	79	1			T125	2		T199	2		T282	3
all_pins[6]	values[0x0]	743862	1			T1	1		T2	2		T3	9
all_pins[6]	values[0x1]	108	1			T125	2		T199	3		T282	4
all_pins[6]	transitions[0x0=>0x1]	77	1			T125	2		T199	3		T282	3
all_pins[6]	transitions[0x1=>0x0]	34919	1			T4	1		T7	1		T14	288
all_pins[7]	values[0x0]	709020	1			T1	1		T2	2		T3	9
all_pins[7]	values[0x1]	34950	1			T4	1		T7	1		T14	288
all_pins[7]	transitions[0x0=>0x1]	34929	1			T4	1		T7	1		T14	288
all_pins[7]	transitions[0x1=>0x0]	66	1			T125	3		T199	3		T282	2
all_pins[8]	values[0x0]	743883	1			T1	1		T2	2		T3	9
all_pins[8]	values[0x1]	87	1			T125	3		T199	4		T282	3
all_pins[8]	transitions[0x0=>0x1]	65	1			T125	3		T199	3		T292	4
all_pins[8]	transitions[0x1=>0x0]	550798	1			T5	1		T7	1		T14	5075
all_pins[9]	values[0x0]	193150	1			T1	1		T2	2		T3	9
all_pins[9]	values[0x1]	550820	1			T5	1		T7	1		T14	5075
all_pins[9]	transitions[0x0=>0x1]	550803	1			T5	1		T7	1		T14	5075
all_pins[9]	transitions[0x1=>0x0]	38	1			T198	1		T199	1		T136	3
all_pins[10]	values[0x0]	743915	1			T1	1		T2	2		T3	9
all_pins[10]	values[0x1]	55	1			T198	1		T199	1		T282	1
all_pins[10]	transitions[0x0=>0x1]	35	1			T198	1		T199	1		T282	1
all_pins[10]	transitions[0x1=>0x0]	737137	1			T4	2		T5	2		T6	2
all_pins[11]	values[0x0]	6813	1			T1	1		T2	2		T3	9
all_pins[11]	values[0x1]	737157	1			T4	2		T5	2		T6	2
all_pins[11]	transitions[0x0=>0x1]	737123	1			T4	2		T5	2		T6	2
all_pins[11]	transitions[0x1=>0x0]	92	1			T65	1		T71	1		T72	1
all_pins[12]	values[0x0]	743844	1			T1	1		T2	2		T3	9
all_pins[12]	values[0x1]	126	1			T65	1		T71	1		T72	1
all_pins[12]	transitions[0x0=>0x1]	117	1			T65	1		T71	1		T72	1
all_pins[12]	transitions[0x1=>0x0]	64	1			T18	1		T199	2		T293	1
all_pins[13]	values[0x0]	743897	1			T1	1		T2	2		T3	9
all_pins[13]	values[0x1]	73	1			T18	1		T199	2		T293	1
all_pins[13]	transitions[0x0=>0x1]	54	1			T18	1		T199	1		T293	1
all_pins[13]	transitions[0x1=>0x0]	71	1			T18	2		T125	4		T199	1
all_pins[14]	values[0x0]	743880	1			T1	1		T2	2		T3	9
all_pins[14]	values[0x1]	90	1			T18	2		T125	4		T199	2
all_pins[14]	transitions[0x0=>0x1]	45	1			T18	1		T125	1		T199	2
all_pins[14]	transitions[0x1=>0x0]	632113	1			T4	1		T5	1		T6	1