Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	359	1			T18	4		T198	4		T125	7
all_values[1]	359	1			T18	4		T198	4		T125	7
all_values[2]	359	1			T18	4		T198	4		T125	7
all_values[3]	359	1			T18	4		T198	4		T125	7
all_values[4]	359	1			T18	4		T198	4		T125	7
all_values[5]	359	1			T18	4		T198	4		T125	7
all_values[6]	359	1			T18	4		T198	4		T125	7
all_values[7]	359	1			T18	4		T198	4		T125	7
all_values[8]	359	1			T18	4		T198	4		T125	7
all_values[9]	359	1			T18	4		T198	4		T125	7
all_values[10]	359	1			T18	4		T198	4		T125	7
all_values[11]	359	1			T18	4		T198	4		T125	7
all_values[12]	359	1			T18	4		T198	4		T125	7
all_values[13]	359	1			T18	4		T198	4		T125	7
all_values[14]	359	1			T18	4		T198	4		T125	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2874

1

T18

37

T198

36

T125

55

auto[1]

2511

1

T18

23

T198

24

T125

50

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

891

1

T18

15

T198

19

T125

15

auto[1]

4494

1

T18

45

T198

41

T125

90

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3190

1

T18

37

T198

37

T125

52

auto[1]

2195

1

T18

23

T198

23

T125

53

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	29	1			T199	1		T282	1		T136	1
all_values[0]	auto[0]	auto[0]	auto[1]	66	1			T199	2		T282	2		T293	3
all_values[0]	auto[0]	auto[1]	auto[0]	26	1			T136	1		T292	1		T26	1
all_values[0]	auto[0]	auto[1]	auto[1]	88	1			T18	2		T198	2		T125	2
all_values[0]	auto[1]	auto[0]	auto[1]	78	1			T18	2		T198	1		T125	3
all_values[0]	auto[1]	auto[1]	auto[1]	72	1			T198	1		T125	2		T199	4
all_values[1]	auto[0]	auto[0]	auto[0]	47	1			T18	4		T198	2		T293	1
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T198	1		T125	1		T199	4
all_values[1]	auto[0]	auto[1]	auto[0]	32	1			T125	2		T293	1		T136	3
all_values[1]	auto[0]	auto[1]	auto[1]	75	1			T125	2		T199	3		T282	1
all_values[1]	auto[1]	auto[0]	auto[1]	72	1			T198	1		T125	1		T199	2
all_values[1]	auto[1]	auto[1]	auto[1]	53	1			T125	1		T199	2		T282	2
all_values[2]	auto[0]	auto[0]	auto[0]	28	1			T18	1		T198	1		T137	1
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T125	2		T199	3		T293	3
all_values[2]	auto[0]	auto[1]	auto[0]	34	1			T18	3		T294	1		T137	4
all_values[2]	auto[0]	auto[1]	auto[1]	80	1			T198	2		T199	3		T282	4
all_values[2]	auto[1]	auto[0]	auto[1]	76	1			T198	1		T125	1		T199	3
all_values[2]	auto[1]	auto[1]	auto[1]	63	1			T125	4		T199	2		T282	3
all_values[3]	auto[0]	auto[0]	auto[0]	27	1			T198	1		T282	1		T295	1
all_values[3]	auto[0]	auto[0]	auto[1]	74	1			T125	3		T199	7		T293	4
all_values[3]	auto[0]	auto[1]	auto[0]	19	1			T198	1		T125	3		T199	1
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T18	1		T198	1		T199	1
all_values[3]	auto[1]	auto[0]	auto[1]	84	1			T18	2		T125	1		T199	2
all_values[3]	auto[1]	auto[1]	auto[1]	64	1			T18	1		T198	1		T282	1
all_values[4]	auto[0]	auto[0]	auto[0]	37	1			T18	1		T198	2		T293	2
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T18	1		T199	3		T282	4
all_values[4]	auto[0]	auto[1]	auto[0]	27	1			T198	2		T282	1		T295	1
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T125	2		T199	1		T282	1
all_values[4]	auto[1]	auto[0]	auto[1]	90	1			T18	2		T125	3		T199	4
all_values[4]	auto[1]	auto[1]	auto[1]	62	1			T125	2		T199	3		T282	2
all_values[5]	auto[0]	auto[0]	auto[0]	26	1			T282	4		T137	1		T296	2
all_values[5]	auto[0]	auto[0]	auto[1]	62	1			T18	1		T125	2		T199	2
all_values[5]	auto[0]	auto[1]	auto[0]	19	1			T125	1		T293	2		T26	1
all_values[5]	auto[0]	auto[1]	auto[1]	93	1			T18	2		T198	1		T125	2
all_values[5]	auto[1]	auto[0]	auto[1]	78	1			T18	1		T198	1		T125	1
all_values[5]	auto[1]	auto[1]	auto[1]	81	1			T198	2		T125	1		T199	1
all_values[6]	auto[0]	auto[0]	auto[0]	36	1			T18	1		T198	3		T125	1
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T18	1		T125	2		T199	5
all_values[6]	auto[0]	auto[1]	auto[0]	20	1			T198	1		T282	1		T293	4
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T18	1		T125	2		T199	2
all_values[6]	auto[1]	auto[0]	auto[1]	73	1			T18	1		T125	1		T199	2
all_values[6]	auto[1]	auto[1]	auto[1]	78	1			T125	1		T199	2		T282	3
all_values[7]	auto[0]	auto[0]	auto[0]	28	1			T18	1		T125	1		T297	1
all_values[7]	auto[0]	auto[0]	auto[1]	86	1			T198	3		T125	2		T199	4
all_values[7]	auto[0]	auto[1]	auto[0]	19	1			T18	3		T136	1		T298	1
all_values[7]	auto[0]	auto[1]	auto[1]	68	1			T125	1		T199	5		T282	3
all_values[7]	auto[1]	auto[0]	auto[1]	90	1			T125	2		T199	1		T282	3
all_values[7]	auto[1]	auto[1]	auto[1]	68	1			T198	1		T125	1		T199	1
all_values[8]	auto[0]	auto[0]	auto[0]	28	1			T198	1		T26	1		T297	1
all_values[8]	auto[0]	auto[0]	auto[1]	86	1			T18	1		T199	2		T282	3
all_values[8]	auto[0]	auto[1]	auto[0]	20	1			T282	1		T26	1		T295	1
all_values[8]	auto[0]	auto[1]	auto[1]	70	1			T198	2		T125	1		T199	4
all_values[8]	auto[1]	auto[0]	auto[1]	90	1			T18	1		T198	1		T125	5
all_values[8]	auto[1]	auto[1]	auto[1]	65	1			T18	2		T125	1		T199	2
all_values[9]	auto[0]	auto[0]	auto[0]	36	1			T294	2		T297	1		T296	1
all_values[9]	auto[0]	auto[0]	auto[1]	88	1			T198	1		T125	3		T199	3
all_values[9]	auto[0]	auto[1]	auto[0]	26	1			T125	1		T293	1		T292	1
all_values[9]	auto[0]	auto[1]	auto[1]	76	1			T18	3		T199	3		T282	1
all_values[9]	auto[1]	auto[0]	auto[1]	63	1			T18	1		T198	3		T199	1
all_values[9]	auto[1]	auto[1]	auto[1]	70	1			T125	3		T199	4		T282	2
all_values[10]	auto[0]	auto[0]	auto[0]	38	1			T18	1		T125	2		T199	1
all_values[10]	auto[0]	auto[0]	auto[1]	81	1			T18	2		T198	2		T125	1
all_values[10]	auto[0]	auto[1]	auto[0]	31	1			T125	1		T199	1		T136	1
all_values[10]	auto[0]	auto[1]	auto[1]	75	1			T199	4		T282	2		T293	3
all_values[10]	auto[1]	auto[0]	auto[1]	79	1			T18	1		T198	1		T125	3
all_values[10]	auto[1]	auto[1]	auto[1]	55	1			T198	1		T199	2		T282	2
all_values[11]	auto[0]	auto[0]	auto[0]	21	1			T198	1		T26	1		T138	1
all_values[11]	auto[0]	auto[0]	auto[1]	90	1			T125	3		T199	4		T282	3
all_values[11]	auto[0]	auto[1]	auto[0]	28	1			T282	1		T26	1		T294	4
all_values[11]	auto[0]	auto[1]	auto[1]	69	1			T18	2		T198	1		T125	1
all_values[11]	auto[1]	auto[0]	auto[1]	83	1			T18	2		T198	1		T125	2
all_values[11]	auto[1]	auto[1]	auto[1]	68	1			T198	1		T125	1		T199	2
all_values[12]	auto[0]	auto[0]	auto[0]	49	1			T125	1		T282	1		T293	1
all_values[12]	auto[0]	auto[0]	auto[1]	78	1			T18	1		T198	1		T125	1
all_values[12]	auto[0]	auto[1]	auto[0]	36	1			T293	1		T136	1		T295	2
all_values[12]	auto[0]	auto[1]	auto[1]	61	1			T18	1		T199	7		T293	1
all_values[12]	auto[1]	auto[0]	auto[1]	80	1			T18	2		T198	2		T125	3
all_values[12]	auto[1]	auto[1]	auto[1]	55	1			T198	1		T125	2		T199	3
all_values[13]	auto[0]	auto[0]	auto[0]	36	1			T282	1		T293	3		T136	3
all_values[13]	auto[0]	auto[0]	auto[1]	78	1			T18	1		T198	1		T199	1
all_values[13]	auto[0]	auto[1]	auto[0]	38	1			T125	2		T199	1		T282	1
all_values[13]	auto[0]	auto[1]	auto[1]	67	1			T18	1		T125	2		T199	4
all_values[13]	auto[1]	auto[0]	auto[1]	74	1			T18	2		T198	2		T125	2
all_values[13]	auto[1]	auto[1]	auto[1]	66	1			T198	1		T125	1		T199	3
all_values[14]	auto[0]	auto[0]	auto[0]	34	1			T198	2		T199	1		T282	1
all_values[14]	auto[0]	auto[0]	auto[1]	72	1			T125	1		T199	3		T282	3
all_values[14]	auto[0]	auto[1]	auto[0]	16	1			T198	2		T292	2		T294	1
all_values[14]	auto[0]	auto[1]	auto[1]	72	1			T18	1		T125	1		T293	1
all_values[14]	auto[1]	auto[0]	auto[1]	94	1			T18	3		T125	1		T199	4
all_values[14]	auto[1]	auto[1]	auto[1]	71	1			T125	4		T199	3		T282	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal