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 LINE       3661
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T5,T6
110CoveredT224,T220,T225
111CoveredT201,T111,T226

 LINE       3662
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T5,T6
110CoveredT202,T203,T209
111CoveredT6,T9,T10

 LINE       3667
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T5,T8
110CoveredT115,T222,T227
111Not Covered

 LINE       3668
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T5,T8
110CoveredT202,T203,T209
111CoveredT11,T12,T13

 LINE       3673
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T4
110CoveredT202,T210,T211
111CoveredT1,T3,T4

 LINE       3682
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T5,T8
110CoveredT203,T211,T118
111CoveredT73,T62,T74
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