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LINE 3661
EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T224,T220,T225 |
1 | 1 | 1 | Covered | T201,T111,T226 |
LINE 3662
EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T5,T6 |
1 | 1 | 0 | Covered | T202,T203,T209 |
1 | 1 | 1 | Covered | T6,T9,T10 |
LINE 3667
EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T5,T8 |
1 | 1 | 0 | Covered | T115,T222,T227 |
1 | 1 | 1 | Not Covered | |
LINE 3668
EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T5,T8 |
1 | 1 | 0 | Covered | T202,T203,T209 |
1 | 1 | 1 | Covered | T11,T12,T13 |
LINE 3673
EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Covered | T202,T210,T211 |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 3682
EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T5,T8 |
1 | 1 | 0 | Covered | T203,T211,T118 |
1 | 1 | 1 | Covered | T73,T62,T74 |