Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	705774	1			T1	1		T2	2		T3	12
all_values[1]	705774	1			T1	1		T2	2		T3	12
all_values[2]	705774	1			T1	1		T2	2		T3	12
all_values[3]	705774	1			T1	1		T2	2		T3	12
all_values[4]	705774	1			T1	1		T2	2		T3	12
all_values[5]	705774	1			T1	1		T2	2		T3	12
all_values[6]	705774	1			T1	1		T2	2		T3	12
all_values[7]	705774	1			T1	1		T2	2		T3	12
all_values[8]	705774	1			T1	1		T2	2		T3	12
all_values[9]	705774	1			T1	1		T2	2		T3	12
all_values[10]	705774	1			T1	1		T2	2		T3	12
all_values[11]	705774	1			T1	1		T2	2		T3	12
all_values[12]	705774	1			T1	1		T2	2		T3	12
all_values[13]	705774	1			T1	1		T2	2		T3	12
all_values[14]	705774	1			T1	1		T2	2		T3	12

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8749142

1

T1

15

T2

30

T3

180

auto[1]

1837468

1

T4

4

T5

4

T6

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10360882

1

T1

15

T2

30

T3

180

auto[1]

225728

1

T134

5559

T198

4920

T199

119

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114221	1			T1	1		T2	2		T3	12
all_values[0]	auto[0]	auto[1]	2977	1			T134	23		T198	24		T199	5
all_values[0]	auto[1]	auto[0]	574422	1			T4	2		T5	2		T6	2
all_values[0]	auto[1]	auto[1]	14154	1			T134	348		T198	327		T199	4
all_values[1]	auto[0]	auto[0]	688329	1			T1	1		T2	2		T3	12
all_values[1]	auto[0]	auto[1]	17011	1			T134	367		T198	350		T199	6
all_values[1]	auto[1]	auto[0]	306	1			T203	2		T290	1		T92	48
all_values[1]	auto[1]	auto[1]	128	1			T134	4		T198	1		T199	3
all_values[2]	auto[0]	auto[0]	688470	1			T1	1		T2	2		T3	12
all_values[2]	auto[0]	auto[1]	16998	1			T134	365		T198	349		T199	4
all_values[2]	auto[1]	auto[0]	190	1			T45	1		T61	1		T173	2
all_values[2]	auto[1]	auto[1]	116	1			T134	4		T198	2		T199	3
all_values[3]	auto[0]	auto[0]	688648	1			T1	1		T2	2		T3	12
all_values[3]	auto[0]	auto[1]	16973	1			T134	365		T198	350		T199	6
all_values[3]	auto[1]	auto[1]	153	1			T134	4		T198	2		T199	1
all_values[4]	auto[0]	auto[0]	688640	1			T1	1		T2	2		T3	12
all_values[4]	auto[0]	auto[1]	16997	1			T134	367		T198	350		T199	6
all_values[4]	auto[1]	auto[0]	18	1			T12	1		T13	3		T268	1
all_values[4]	auto[1]	auto[1]	119	1			T134	3		T198	1		T199	2
all_values[5]	auto[0]	auto[0]	688625	1			T1	1		T2	2		T3	12
all_values[5]	auto[0]	auto[1]	16985	1			T134	367		T198	348		T199	2
all_values[5]	auto[1]	auto[1]	164	1			T134	3		T198	4		T199	6
all_values[6]	auto[0]	auto[0]	688969	1			T1	1		T2	2		T3	12
all_values[6]	auto[0]	auto[1]	16675	1			T134	369		T199	5		T200	5
all_values[6]	auto[1]	auto[1]	130	1			T134	2		T199	2		T121	5
all_values[7]	auto[0]	auto[0]	656634	1			T1	1		T2	2		T3	12
all_values[7]	auto[0]	auto[1]	16684	1			T134	317		T198	305		T199	4
all_values[7]	auto[1]	auto[0]	32005	1			T11	1		T19	4		T20	27
all_values[7]	auto[1]	auto[1]	451	1			T134	54		T198	46		T199	5
all_values[8]	auto[0]	auto[0]	688631	1			T1	1		T2	2		T3	12
all_values[8]	auto[0]	auto[1]	16984	1			T134	363		T198	348		T199	5
all_values[8]	auto[1]	auto[1]	159	1			T134	8		T198	4		T199	3
all_values[9]	auto[0]	auto[0]	192914	1			T1	1		T2	2		T3	12
all_values[9]	auto[0]	auto[1]	1610	1			T134	341		T198	336		T199	7
all_values[9]	auto[1]	auto[0]	495713	1			T11	1		T45	1		T19	2
all_values[9]	auto[1]	auto[1]	15537	1			T134	30		T198	16		T199	2
all_values[10]	auto[0]	auto[0]	688653	1			T1	1		T2	2		T3	12
all_values[10]	auto[0]	auto[1]	17002	1			T134	367		T198	350		T199	4
all_values[10]	auto[1]	auto[1]	119	1			T134	4		T198	1		T199	3
all_values[11]	auto[0]	auto[0]	2458	1			T1	1		T2	2		T3	12
all_values[11]	auto[0]	auto[1]	217	1			T134	2		T198	23		T199	4
all_values[11]	auto[1]	auto[0]	701648	1			T4	2		T5	2		T6	2
all_values[11]	auto[1]	auto[1]	1451	1			T134	369		T198	328		T199	3
all_values[12]	auto[0]	auto[0]	704052	1			T1	1		T2	2		T3	12
all_values[12]	auto[0]	auto[1]	1536	1			T134	369		T198	350		T199	4
all_values[12]	auto[1]	auto[0]	65	1			T61	1		T67	1		T291	1
all_values[12]	auto[1]	auto[1]	121	1			T134	2		T198	2		T199	3
all_values[13]	auto[0]	auto[0]	688633	1			T1	1		T2	2		T3	12
all_values[13]	auto[0]	auto[1]	16994	1			T134	369		T198	351		T199	6
all_values[13]	auto[1]	auto[1]	147	1			T134	2		T198	1		T199	2
all_values[14]	auto[0]	auto[0]	688638	1			T1	1		T2	2		T3	12
all_values[14]	auto[0]	auto[1]	16984	1			T134	369		T198	348		T199	7
all_values[14]	auto[1]	auto[1]	152	1			T134	2		T198	3		T199	2