Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	705774	1			T1	1		T2	2		T3	12
all_pins[1]	705774	1			T1	1		T2	2		T3	12
all_pins[2]	705774	1			T1	1		T2	2		T3	12
all_pins[3]	705774	1			T1	1		T2	2		T3	12
all_pins[4]	705774	1			T1	1		T2	2		T3	12
all_pins[5]	705774	1			T1	1		T2	2		T3	12
all_pins[6]	705774	1			T1	1		T2	2		T3	12
all_pins[7]	705774	1			T1	1		T2	2		T3	12
all_pins[8]	705774	1			T1	1		T2	2		T3	12
all_pins[9]	705774	1			T1	1		T2	2		T3	12
all_pins[10]	705774	1			T1	1		T2	2		T3	12
all_pins[11]	705774	1			T1	1		T2	2		T3	12
all_pins[12]	705774	1			T1	1		T2	2		T3	12
all_pins[13]	705774	1			T1	1		T2	2		T3	12
all_pins[14]	705774	1			T1	1		T2	2		T3	12

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8755677	1			T1	15		T2	30		T3	180
values[0x1]	1830933	1			T4	4		T5	4		T6	4
transitions[0x0=>0x1]	1830355	1			T4	4		T5	4		T6	4
transitions[0x1=>0x0]	1829054	1			T4	3		T5	3		T6	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	120897	1			T1	1		T2	2		T3	12
all_pins[0]	values[0x1]	584877	1			T4	2		T5	2		T6	2
all_pins[0]	transitions[0x0=>0x1]	584519	1			T4	2		T5	2		T6	2
all_pins[0]	transitions[0x1=>0x0]	64	1			T274	1		T134	2		T199	1
all_pins[1]	values[0x0]	705352	1			T1	1		T2	2		T3	12
all_pins[1]	values[0x1]	422	1			T203	2		T290	1		T92	64
all_pins[1]	transitions[0x0=>0x1]	404	1			T203	2		T290	1		T92	64
all_pins[1]	transitions[0x1=>0x0]	92	1			T45	1		T300	1		T291	1
all_pins[2]	values[0x0]	705664	1			T1	1		T2	2		T3	12
all_pins[2]	values[0x1]	110	1			T45	1		T300	1		T291	1
all_pins[2]	transitions[0x0=>0x1]	100	1			T45	1		T300	1		T291	1
all_pins[2]	transitions[0x1=>0x0]	41	1			T134	3		T198	1		T199	1
all_pins[3]	values[0x0]	705723	1			T1	1		T2	2		T3	12
all_pins[3]	values[0x1]	51	1			T134	4		T198	2		T199	1
all_pins[3]	transitions[0x0=>0x1]	42	1			T134	4		T198	2		T199	1
all_pins[3]	transitions[0x1=>0x0]	62	1			T12	1		T13	4		T268	1
all_pins[4]	values[0x0]	705703	1			T1	1		T2	2		T3	12
all_pins[4]	values[0x1]	71	1			T12	1		T13	4		T268	1
all_pins[4]	transitions[0x0=>0x1]	56	1			T12	1		T13	4		T268	1
all_pins[4]	transitions[0x1=>0x0]	74	1			T134	2		T199	4		T200	1
all_pins[5]	values[0x0]	705685	1			T1	1		T2	2		T3	12
all_pins[5]	values[0x1]	89	1			T134	3		T199	4		T200	1
all_pins[5]	transitions[0x0=>0x1]	78	1			T134	3		T199	3		T200	1
all_pins[5]	transitions[0x1=>0x0]	49	1			T121	2		T301	1		T302	3
all_pins[6]	values[0x0]	705714	1			T1	1		T2	2		T3	12
all_pins[6]	values[0x1]	60	1			T199	1		T121	2		T301	1
all_pins[6]	transitions[0x0=>0x1]	44	1			T199	1		T121	2		T301	1
all_pins[6]	transitions[0x1=>0x0]	34858	1			T11	1		T19	4		T20	28
all_pins[7]	values[0x0]	670900	1			T1	1		T2	2		T3	12
all_pins[7]	values[0x1]	34874	1			T11	1		T19	4		T20	28
all_pins[7]	transitions[0x0=>0x1]	34864	1			T11	1		T19	4		T20	28
all_pins[7]	transitions[0x1=>0x0]	51	1			T134	2		T198	2		T199	1
all_pins[8]	values[0x0]	705713	1			T1	1		T2	2		T3	12
all_pins[8]	values[0x1]	61	1			T134	4		T198	3		T199	1
all_pins[8]	transitions[0x0=>0x1]	50	1			T134	4		T198	3		T199	1
all_pins[8]	transitions[0x1=>0x0]	511186	1			T11	1		T45	1		T19	2
all_pins[9]	values[0x0]	194577	1			T1	1		T2	2		T3	12
all_pins[9]	values[0x1]	511197	1			T11	1		T45	1		T19	2
all_pins[9]	transitions[0x0=>0x1]	511185	1			T11	1		T45	1		T19	2
all_pins[9]	transitions[0x1=>0x0]	45	1			T134	1		T199	2		T121	3
all_pins[10]	values[0x0]	705717	1			T1	1		T2	2		T3	12
all_pins[10]	values[0x1]	57	1			T134	1		T199	2		T121	3
all_pins[10]	transitions[0x0=>0x1]	40	1			T134	1		T121	2		T301	2
all_pins[10]	transitions[0x1=>0x0]	698778	1			T4	2		T5	2		T6	2
all_pins[11]	values[0x0]	6979	1			T1	1		T2	2		T3	12
all_pins[11]	values[0x1]	698795	1			T4	2		T5	2		T6	2
all_pins[11]	transitions[0x0=>0x1]	698762	1			T4	2		T5	2		T6	2
all_pins[11]	transitions[0x1=>0x0]	95	1			T61	1		T67	1		T68	1
all_pins[12]	values[0x0]	705646	1			T1	1		T2	2		T3	12
all_pins[12]	values[0x1]	128	1			T61	1		T67	1		T291	1
all_pins[12]	transitions[0x0=>0x1]	114	1			T61	1		T67	1		T291	1
all_pins[12]	transitions[0x1=>0x0]	56	1			T134	1		T198	1		T199	2
all_pins[13]	values[0x0]	705704	1			T1	1		T2	2		T3	12
all_pins[13]	values[0x1]	70	1			T134	1		T198	1		T199	2
all_pins[13]	transitions[0x0=>0x1]	52	1			T134	1		T198	1		T199	2
all_pins[13]	transitions[0x1=>0x0]	53	1			T134	1		T198	3		T199	1
all_pins[14]	values[0x0]	705703	1			T1	1		T2	2		T3	12
all_pins[14]	values[0x1]	71	1			T134	1		T198	3		T199	1
all_pins[14]	transitions[0x0=>0x1]	45	1			T198	3		T200	1		T121	2
all_pins[14]	transitions[0x1=>0x0]	583550	1			T4	1		T5	1		T6	1