Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	325	1			T134	8		T198	4		T199	7
all_values[1]	325	1			T134	8		T198	4		T199	7
all_values[2]	325	1			T134	8		T198	4		T199	7
all_values[3]	325	1			T134	8		T198	4		T199	7
all_values[4]	325	1			T134	8		T198	4		T199	7
all_values[5]	325	1			T134	8		T198	4		T199	7
all_values[6]	325	1			T134	8		T198	4		T199	7
all_values[7]	325	1			T134	8		T198	4		T199	7
all_values[8]	325	1			T134	8		T198	4		T199	7
all_values[9]	325	1			T134	8		T198	4		T199	7
all_values[10]	325	1			T134	8		T198	4		T199	7
all_values[11]	325	1			T134	8		T198	4		T199	7
all_values[12]	325	1			T134	8		T198	4		T199	7
all_values[13]	325	1			T134	8		T198	4		T199	7
all_values[14]	325	1			T134	8		T198	4		T199	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2593

1

T134

61

T198

32

T199

45

auto[1]

2282

1

T134

59

T198

28

T199

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

869

1

T134

6

T198

12

T199

16

auto[1]

4006

1

T134

114

T198

48

T199

89

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2964

1

T134

72

T198

38

T199

62

auto[1]

1911

1

T134

48

T198

22

T199

43

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	34	1			T198	1		T303	1		T304	1
all_values[0]	auto[0]	auto[0]	auto[1]	66	1			T134	1		T198	1		T199	2
all_values[0]	auto[0]	auto[1]	auto[0]	26	1			T303	4		T305	1		T302	2
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T134	2		T198	1		T199	1
all_values[0]	auto[1]	auto[0]	auto[1]	62	1			T134	2		T198	1		T200	2
all_values[0]	auto[1]	auto[1]	auto[1]	60	1			T134	3		T199	4		T121	1
all_values[1]	auto[0]	auto[0]	auto[0]	32	1			T198	1		T306	1		T303	2
all_values[1]	auto[0]	auto[0]	auto[1]	58	1			T134	3		T198	1		T200	2
all_values[1]	auto[0]	auto[1]	auto[0]	21	1			T121	1		T306	1		T305	1
all_values[1]	auto[0]	auto[1]	auto[1]	86	1			T134	1		T198	1		T199	4
all_values[1]	auto[1]	auto[0]	auto[1]	70	1			T134	2		T198	1		T199	1
all_values[1]	auto[1]	auto[1]	auto[1]	58	1			T134	2		T199	2		T301	3
all_values[2]	auto[0]	auto[0]	auto[0]	41	1			T134	2		T198	1		T199	1
all_values[2]	auto[0]	auto[0]	auto[1]	56	1			T134	1		T121	3		T301	3
all_values[2]	auto[0]	auto[1]	auto[0]	34	1			T199	1		T200	1		T307	2
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T134	1		T198	1		T199	2
all_values[2]	auto[1]	auto[0]	auto[1]	58	1			T134	4		T199	2		T306	1
all_values[2]	auto[1]	auto[1]	auto[1]	58	1			T198	2		T199	1		T200	1
all_values[3]	auto[0]	auto[0]	auto[0]	38	1			T134	2		T199	1		T301	1
all_values[3]	auto[0]	auto[0]	auto[1]	72	1			T121	3		T301	2		T303	1
all_values[3]	auto[0]	auto[1]	auto[0]	27	1			T199	1		T200	4		T301	1
all_values[3]	auto[0]	auto[1]	auto[1]	48	1			T134	3		T198	1		T199	4
all_values[3]	auto[1]	auto[0]	auto[1]	86	1			T134	1		T198	1		T121	3
all_values[3]	auto[1]	auto[1]	auto[1]	54	1			T134	2		T198	2		T199	1
all_values[4]	auto[0]	auto[0]	auto[0]	45	1			T198	1		T306	2		T305	3
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T134	3		T198	2		T199	3
all_values[4]	auto[0]	auto[1]	auto[0]	28	1			T134	1		T199	1		T306	2
all_values[4]	auto[0]	auto[1]	auto[1]	55	1			T134	1		T199	1		T121	2
all_values[4]	auto[1]	auto[0]	auto[1]	78	1			T134	2		T198	1		T199	1
all_values[4]	auto[1]	auto[1]	auto[1]	41	1			T134	1		T199	1		T121	1
all_values[5]	auto[0]	auto[0]	auto[0]	25	1			T306	1		T308	2		T304	2
all_values[5]	auto[0]	auto[0]	auto[1]	67	1			T134	2		T198	2		T200	2
all_values[5]	auto[0]	auto[1]	auto[0]	20	1			T134	1		T199	1		T200	1
all_values[5]	auto[0]	auto[1]	auto[1]	71	1			T134	3		T199	2		T121	3
all_values[5]	auto[1]	auto[0]	auto[1]	68	1			T198	2		T199	1		T121	2
all_values[5]	auto[1]	auto[1]	auto[1]	74	1			T134	2		T199	3		T200	1
all_values[6]	auto[0]	auto[0]	auto[0]	26	1			T198	4		T199	2		T200	1
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T134	3		T199	1		T200	2
all_values[6]	auto[0]	auto[1]	auto[0]	14	1			T306	3		T307	1		T302	1
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T134	3		T199	1		T121	2
all_values[6]	auto[1]	auto[0]	auto[1]	74	1			T134	2		T200	1		T121	2
all_values[6]	auto[1]	auto[1]	auto[1]	55	1			T199	3		T121	2		T301	3
all_values[7]	auto[0]	auto[0]	auto[0]	38	1			T198	1		T306	1		T309	2
all_values[7]	auto[0]	auto[0]	auto[1]	67	1			T134	1		T199	2		T121	3
all_values[7]	auto[0]	auto[1]	auto[0]	19	1			T121	2		T303	1		T307	1
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T134	3		T198	1		T199	1
all_values[7]	auto[1]	auto[0]	auto[1]	74	1			T134	1		T199	4		T200	2
all_values[7]	auto[1]	auto[1]	auto[1]	58	1			T134	3		T198	2		T121	1
all_values[8]	auto[0]	auto[0]	auto[0]	39	1			T199	1		T306	1		T309	1
all_values[8]	auto[0]	auto[0]	auto[1]	81	1			T134	2		T199	1		T200	1
all_values[8]	auto[0]	auto[1]	auto[0]	10	1			T304	2		T310	2		T311	1
all_values[8]	auto[0]	auto[1]	auto[1]	65	1			T134	2		T198	2		T199	1
all_values[8]	auto[1]	auto[0]	auto[1]	84	1			T134	3		T198	1		T199	2
all_values[8]	auto[1]	auto[1]	auto[1]	46	1			T134	1		T198	1		T199	2
all_values[9]	auto[0]	auto[0]	auto[0]	31	1			T121	1		T302	1		T309	1
all_values[9]	auto[0]	auto[0]	auto[1]	68	1			T134	4		T199	2		T121	1
all_values[9]	auto[0]	auto[1]	auto[0]	14	1			T121	3		T305	1		T310	1
all_values[9]	auto[0]	auto[1]	auto[1]	81	1			T134	1		T198	3		T199	3
all_values[9]	auto[1]	auto[0]	auto[1]	76	1			T134	2		T198	1		T121	2
all_values[9]	auto[1]	auto[1]	auto[1]	55	1			T134	1		T199	2		T200	3
all_values[10]	auto[0]	auto[0]	auto[0]	39	1			T198	1		T199	1		T306	3
all_values[10]	auto[0]	auto[0]	auto[1]	68	1			T134	1		T198	1		T199	1
all_values[10]	auto[0]	auto[1]	auto[0]	29	1			T199	1		T306	1		T307	2
all_values[10]	auto[0]	auto[1]	auto[1]	70	1			T134	3		T198	1		T199	1
all_values[10]	auto[1]	auto[0]	auto[1]	68	1			T134	3		T198	1		T199	1
all_values[10]	auto[1]	auto[1]	auto[1]	51	1			T134	1		T199	2		T121	4
all_values[11]	auto[0]	auto[0]	auto[0]	32	1			T198	1		T199	1		T200	2
all_values[11]	auto[0]	auto[0]	auto[1]	57	1			T121	1		T306	2		T301	1
all_values[11]	auto[0]	auto[1]	auto[0]	31	1			T199	1		T121	1		T301	2
all_values[11]	auto[0]	auto[1]	auto[1]	71	1			T134	4		T198	1		T199	2
all_values[11]	auto[1]	auto[0]	auto[1]	58	1			T134	3		T198	2		T121	4
all_values[11]	auto[1]	auto[1]	auto[1]	76	1			T134	1		T199	3		T200	1
all_values[12]	auto[0]	auto[0]	auto[0]	40	1			T199	1		T200	2		T121	1
all_values[12]	auto[0]	auto[0]	auto[1]	60	1			T134	5		T199	2		T121	2
all_values[12]	auto[0]	auto[1]	auto[0]	31	1			T199	1		T200	2		T121	1
all_values[12]	auto[0]	auto[1]	auto[1]	73	1			T134	1		T198	2		T121	4
all_values[12]	auto[1]	auto[0]	auto[1]	51	1			T134	1		T198	1		T199	3
all_values[12]	auto[1]	auto[1]	auto[1]	70	1			T134	1		T198	1		T121	3
all_values[13]	auto[0]	auto[0]	auto[0]	26	1			T306	2		T310	4		T312	1
all_values[13]	auto[0]	auto[0]	auto[1]	72	1			T199	2		T200	1		T121	7
all_values[13]	auto[0]	auto[1]	auto[0]	25	1			T199	1		T200	2		T306	2
all_values[13]	auto[0]	auto[1]	auto[1]	75	1			T134	5		T198	3		T199	2
all_values[13]	auto[1]	auto[0]	auto[1]	72	1			T134	1		T198	1		T199	1
all_values[13]	auto[1]	auto[1]	auto[1]	55	1			T134	2		T199	1		T121	1
all_values[14]	auto[0]	auto[0]	auto[0]	31	1			T198	1		T306	1		T301	1
all_values[14]	auto[0]	auto[0]	auto[1]	79	1			T134	4		T199	4		T200	1
all_values[14]	auto[0]	auto[1]	auto[0]	23	1			T200	1		T306	1		T307	2
all_values[14]	auto[0]	auto[1]	auto[1]	71	1			T134	3		T198	2		T199	1
all_values[14]	auto[1]	auto[0]	auto[1]	67	1			T199	1		T200	1		T121	1
all_values[14]	auto[1]	auto[1]	auto[1]	54	1			T134	1		T198	1		T199	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal