Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	719568	1			T1	4		T2	8		T3	2
all_values[1]	719568	1			T1	4		T2	8		T3	2
all_values[2]	719568	1			T1	4		T2	8		T3	2
all_values[3]	719568	1			T1	4		T2	8		T3	2
all_values[4]	719568	1			T1	4		T2	8		T3	2
all_values[5]	719568	1			T1	4		T2	8		T3	2
all_values[6]	719568	1			T1	4		T2	8		T3	2
all_values[7]	719568	1			T1	4		T2	8		T3	2
all_values[8]	719568	1			T1	4		T2	8		T3	2
all_values[9]	719568	1			T1	4		T2	8		T3	2
all_values[10]	719568	1			T1	4		T2	8		T3	2
all_values[11]	719568	1			T1	4		T2	8		T3	2
all_values[12]	719568	1			T1	4		T2	8		T3	2
all_values[13]	719568	1			T1	4		T2	8		T3	2
all_values[14]	719568	1			T1	4		T2	8		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8867882

1

T1

60

T2

120

T3

26

auto[1]

1925638

1

T3

4

T4

4

T5

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10171275

1

T1

60

T2

120

T3

30

auto[1]

622245

1

T41

74060

T21

71812

T124

57166

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	86878	1			T1	4		T2	8		T11	2
all_values[0]	auto[0]	auto[1]	4506	1			T41	66		T21	465		T124	408
all_values[0]	auto[1]	auto[0]	590845	1			T3	2		T4	2		T5	12
all_values[0]	auto[1]	auto[1]	37339	1			T41	5221		T21	4324		T124	3401
all_values[1]	auto[0]	auto[0]	677566	1			T1	4		T2	8		T3	2
all_values[1]	auto[0]	auto[1]	41623	1			T41	5244		T21	4780		T124	3806
all_values[1]	auto[1]	auto[0]	159	1			T204	24		T281	2		T282	1
all_values[1]	auto[1]	auto[1]	220	1			T41	45		T21	8		T124	3
all_values[2]	auto[0]	auto[0]	677556	1			T1	4		T2	8		T3	2
all_values[2]	auto[0]	auto[1]	41653	1			T41	5281		T21	4780		T124	3809
all_values[2]	auto[1]	auto[0]	191	1			T171	2		T71	1		T195	1
all_values[2]	auto[1]	auto[1]	168	1			T41	8		T21	6		T124	2
all_values[3]	auto[0]	auto[0]	677733	1			T1	4		T2	8		T3	2
all_values[3]	auto[0]	auto[1]	41661	1			T41	5286		T21	4779		T124	3808
all_values[3]	auto[1]	auto[1]	174	1			T41	3		T21	7		T124	2
all_values[4]	auto[0]	auto[0]	677711	1			T1	4		T2	8		T3	2
all_values[4]	auto[0]	auto[1]	41695	1			T41	5285		T21	4781		T124	3808
all_values[4]	auto[1]	auto[0]	17	1			T14	1		T33	1		T47	1
all_values[4]	auto[1]	auto[1]	145	1			T41	4		T21	6		T124	3
all_values[5]	auto[0]	auto[0]	677731	1			T1	4		T2	8		T3	2
all_values[5]	auto[0]	auto[1]	41651	1			T41	5281		T21	4781		T124	3810
all_values[5]	auto[1]	auto[1]	186	1			T41	8		T21	6		T124	2
all_values[6]	auto[0]	auto[0]	677729	1			T1	4		T2	8		T3	2
all_values[6]	auto[0]	auto[1]	41642	1			T41	5283		T21	4783		T124	3808
all_values[6]	auto[1]	auto[1]	197	1			T41	6		T21	5		T124	4
all_values[7]	auto[0]	auto[0]	650608	1			T1	4		T2	8		T3	2
all_values[7]	auto[0]	auto[1]	39947	1			T41	5060		T21	4442		T124	3633
all_values[7]	auto[1]	auto[0]	27120	1			T12	1		T13	9		T49	1
all_values[7]	auto[1]	auto[1]	1893	1			T41	229		T21	346		T124	178
all_values[8]	auto[0]	auto[0]	677730	1			T1	4		T2	8		T3	2
all_values[8]	auto[0]	auto[1]	41651	1			T41	5287		T21	4780		T124	3810
all_values[8]	auto[1]	auto[1]	187	1			T41	2		T21	9		T138	4
all_values[9]	auto[0]	auto[0]	162958	1			T1	4		T2	8		T3	2
all_values[9]	auto[0]	auto[1]	7480	1			T41	377		T21	1184		T124	321
all_values[9]	auto[1]	auto[0]	514778	1			T81	1		T171	1		T13	4
all_values[9]	auto[1]	auto[1]	34352	1			T41	4912		T21	3602		T124	3491
all_values[10]	auto[0]	auto[0]	677727	1			T1	4		T2	8		T3	2
all_values[10]	auto[0]	auto[1]	41684	1			T41	5285		T21	4782		T124	3808
all_values[10]	auto[1]	auto[1]	157	1			T41	4		T21	7		T124	3
all_values[11]	auto[0]	auto[0]	2352	1			T1	4		T2	8		T11	2
all_values[11]	auto[0]	auto[1]	312	1			T41	15		T21	43		T124	12
all_values[11]	auto[1]	auto[0]	680658	1			T3	2		T4	2		T5	12
all_values[11]	auto[1]	auto[1]	36246	1			T41	4		T21	4746		T124	3800
all_values[12]	auto[0]	auto[0]	677668	1			T1	4		T2	8		T3	2
all_values[12]	auto[0]	auto[1]	41669	1			T41	5282		T21	4780		T124	3809
all_values[12]	auto[1]	auto[0]	63	1			T71	1		T195	1		T76	1
all_values[12]	auto[1]	auto[1]	168	1			T41	6		T21	4		T124	3
all_values[13]	auto[0]	auto[0]	677748	1			T1	4		T2	8		T3	2
all_values[13]	auto[0]	auto[1]	41632	1			T41	5282		T21	4779		T124	3806
all_values[13]	auto[1]	auto[1]	188	1			T41	5		T21	8		T124	6
all_values[14]	auto[0]	auto[0]	677749	1			T1	4		T2	8		T3	2
all_values[14]	auto[0]	auto[1]	41632	1			T41	5281		T21	4778		T124	3806
all_values[14]	auto[1]	auto[1]	187	1			T41	8		T21	11		T124	6