Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	719568	1			T1	4		T2	8		T3	2
all_pins[1]	719568	1			T1	4		T2	8		T3	2
all_pins[2]	719568	1			T1	4		T2	8		T3	2
all_pins[3]	719568	1			T1	4		T2	8		T3	2
all_pins[4]	719568	1			T1	4		T2	8		T3	2
all_pins[5]	719568	1			T1	4		T2	8		T3	2
all_pins[6]	719568	1			T1	4		T2	8		T3	2
all_pins[7]	719568	1			T1	4		T2	8		T3	2
all_pins[8]	719568	1			T1	4		T2	8		T3	2
all_pins[9]	719568	1			T1	4		T2	8		T3	2
all_pins[10]	719568	1			T1	4		T2	8		T3	2
all_pins[11]	719568	1			T1	4		T2	8		T3	2
all_pins[12]	719568	1			T1	4		T2	8		T3	2
all_pins[13]	719568	1			T1	4		T2	8		T3	2
all_pins[14]	719568	1			T1	4		T2	8		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8874830	1			T1	60		T2	120		T3	26
values[0x1]	1918690	1			T3	4		T4	4		T5	24
transitions[0x0=>0x1]	1918107	1			T3	4		T4	4		T5	24
transitions[0x1=>0x0]	1916782	1			T3	3		T4	3		T5	23

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	95060	1			T1	4		T2	8		T11	2
all_pins[0]	values[0x1]	624508	1			T3	2		T4	2		T5	12
all_pins[0]	transitions[0x0=>0x1]	624248	1			T3	2		T4	2		T5	12
all_pins[0]	transitions[0x1=>0x0]	62	1			T41	2		T21	3		T124	1
all_pins[1]	values[0x0]	719246	1			T1	4		T2	8		T3	2
all_pins[1]	values[0x1]	322	1			T204	26		T281	2		T282	1
all_pins[1]	transitions[0x0=>0x1]	295	1			T204	26		T281	2		T282	1
all_pins[1]	transitions[0x1=>0x0]	110	1			T195	1		T289	1		T290	1
all_pins[2]	values[0x0]	719431	1			T1	4		T2	8		T3	2
all_pins[2]	values[0x1]	137	1			T195	1		T289	1		T290	1
all_pins[2]	transitions[0x0=>0x1]	123	1			T195	1		T289	1		T290	1
all_pins[2]	transitions[0x1=>0x0]	68	1			T41	1		T21	2		T138	3
all_pins[3]	values[0x0]	719486	1			T1	4		T2	8		T3	2
all_pins[3]	values[0x1]	82	1			T41	2		T21	2		T124	1
all_pins[3]	transitions[0x0=>0x1]	67	1			T41	2		T21	1		T124	1
all_pins[3]	transitions[0x1=>0x0]	78	1			T14	1		T41	1		T33	1
all_pins[4]	values[0x0]	719475	1			T1	4		T2	8		T3	2
all_pins[4]	values[0x1]	93	1			T14	1		T41	1		T33	1
all_pins[4]	transitions[0x0=>0x1]	81	1			T14	1		T41	1		T33	1
all_pins[4]	transitions[0x1=>0x0]	77	1			T41	2		T21	6		T124	1
all_pins[5]	values[0x0]	719479	1			T1	4		T2	8		T3	2
all_pins[5]	values[0x1]	89	1			T41	2		T21	6		T124	1
all_pins[5]	transitions[0x0=>0x1]	60	1			T41	2		T21	6		T124	1
all_pins[5]	transitions[0x1=>0x0]	82	1			T41	4		T21	3		T124	3
all_pins[6]	values[0x0]	719457	1			T1	4		T2	8		T3	2
all_pins[6]	values[0x1]	111	1			T41	4		T21	3		T124	3
all_pins[6]	transitions[0x0=>0x1]	91	1			T41	1		T21	2		T124	2
all_pins[6]	transitions[0x1=>0x0]	31108	1			T12	1		T49	1		T174	1
all_pins[7]	values[0x0]	688440	1			T1	4		T2	8		T3	2
all_pins[7]	values[0x1]	31128	1			T12	1		T49	1		T174	1
all_pins[7]	transitions[0x0=>0x1]	31113	1			T12	1		T49	1		T174	1
all_pins[7]	transitions[0x1=>0x0]	88	1			T41	1		T21	5		T138	1
all_pins[8]	values[0x0]	719465	1			T1	4		T2	8		T3	2
all_pins[8]	values[0x1]	103	1			T41	2		T21	6		T138	2
all_pins[8]	transitions[0x0=>0x1]	73	1			T21	5		T138	2		T291	3
all_pins[8]	transitions[0x1=>0x0]	549035	1			T81	1		T171	1		T13	4
all_pins[9]	values[0x0]	170503	1			T1	4		T2	8		T3	2
all_pins[9]	values[0x1]	549065	1			T81	1		T171	1		T13	4
all_pins[9]	transitions[0x0=>0x1]	549041	1			T81	1		T171	1		T13	4
all_pins[9]	transitions[0x1=>0x0]	48	1			T41	1		T21	3		T124	2
all_pins[10]	values[0x0]	719496	1			T1	4		T2	8		T3	2
all_pins[10]	values[0x1]	72	1			T41	2		T21	3		T124	3
all_pins[10]	transitions[0x0=>0x1]	54	1			T41	2		T21	2		T124	2
all_pins[10]	transitions[0x1=>0x0]	712635	1			T3	2		T4	2		T5	12
all_pins[11]	values[0x0]	6915	1			T1	4		T2	8		T171	2
all_pins[11]	values[0x1]	712653	1			T3	2		T4	2		T5	12
all_pins[11]	transitions[0x0=>0x1]	712611	1			T3	2		T4	2		T5	12
all_pins[11]	transitions[0x1=>0x0]	107	1			T71	1		T76	1		T77	1
all_pins[12]	values[0x0]	719419	1			T1	4		T2	8		T3	2
all_pins[12]	values[0x1]	149	1			T71	1		T195	1		T76	1
all_pins[12]	transitions[0x0=>0x1]	128	1			T71	1		T195	1		T76	1
all_pins[12]	transitions[0x1=>0x0]	66	1			T41	2		T21	3		T124	3
all_pins[13]	values[0x0]	719481	1			T1	4		T2	8		T3	2
all_pins[13]	values[0x1]	87	1			T41	3		T21	3		T124	5
all_pins[13]	transitions[0x0=>0x1]	63	1			T41	2		T21	2		T124	2
all_pins[13]	transitions[0x1=>0x0]	67	1			T41	1		T21	6		T124	1
all_pins[14]	values[0x0]	719477	1			T1	4		T2	8		T3	2
all_pins[14]	values[0x1]	91	1			T41	2		T21	7		T124	4
all_pins[14]	transitions[0x0=>0x1]	59	1			T41	1		T21	4		T124	2
all_pins[14]	transitions[0x1=>0x0]	623151	1			T3	1		T4	1		T5	11