Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	378	1			T41	11		T21	14		T124	7
all_values[1]	378	1			T41	11		T21	14		T124	7
all_values[2]	378	1			T41	11		T21	14		T124	7
all_values[3]	378	1			T41	11		T21	14		T124	7
all_values[4]	378	1			T41	11		T21	14		T124	7
all_values[5]	378	1			T41	11		T21	14		T124	7
all_values[6]	378	1			T41	11		T21	14		T124	7
all_values[7]	378	1			T41	11		T21	14		T124	7
all_values[8]	378	1			T41	11		T21	14		T124	7
all_values[9]	378	1			T41	11		T21	14		T124	7
all_values[10]	378	1			T41	11		T21	14		T124	7
all_values[11]	378	1			T41	11		T21	14		T124	7
all_values[12]	378	1			T41	11		T21	14		T124	7
all_values[13]	378	1			T41	11		T21	14		T124	7
all_values[14]	378	1			T41	11		T21	14		T124	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2967

1

T41

87

T21

105

T124

41

auto[1]

2703

1

T41

78

T21

105

T124

64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

841

1

T41

10

T21

23

T124

14

auto[1]

4829

1

T41

155

T21

187

T124

91

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3263

1

T41

89

T21

124

T124

61

auto[1]

2407

1

T41

76

T21

86

T124

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	26	1			T124	3		T141	1		T292	1
all_values[0]	auto[0]	auto[0]	auto[1]	101	1			T41	4		T21	4		T124	1
all_values[0]	auto[0]	auto[1]	auto[0]	21	1			T41	2		T291	1		T293	1
all_values[0]	auto[0]	auto[1]	auto[1]	76	1			T21	3		T124	1		T138	4
all_values[0]	auto[1]	auto[0]	auto[1]	74	1			T41	4		T21	2		T124	1
all_values[0]	auto[1]	auto[1]	auto[1]	80	1			T41	1		T21	5		T124	1
all_values[1]	auto[0]	auto[0]	auto[0]	31	1			T293	2		T140	2		T292	1
all_values[1]	auto[0]	auto[0]	auto[1]	76	1			T41	2		T21	4		T138	1
all_values[1]	auto[0]	auto[1]	auto[0]	17	1			T21	1		T124	3		T139	1
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T41	2		T21	3		T124	1
all_values[1]	auto[1]	auto[0]	auto[1]	96	1			T41	5		T21	2		T124	1
all_values[1]	auto[1]	auto[1]	auto[1]	77	1			T41	2		T21	4		T124	2
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T21	2		T124	1		T139	1
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T21	2		T124	4		T138	3
all_values[2]	auto[0]	auto[1]	auto[0]	24	1			T21	1		T141	1		T294	1
all_values[2]	auto[0]	auto[1]	auto[1]	65	1			T41	3		T21	3		T138	3
all_values[2]	auto[1]	auto[0]	auto[1]	87	1			T41	4		T21	2		T124	1
all_values[2]	auto[1]	auto[1]	auto[1]	81	1			T41	4		T21	4		T124	1
all_values[3]	auto[0]	auto[0]	auto[0]	34	1			T21	3		T124	2		T291	2
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T41	2		T21	4		T124	2
all_values[3]	auto[0]	auto[1]	auto[0]	22	1			T291	3		T295	2		T296	2
all_values[3]	auto[0]	auto[1]	auto[1]	83	1			T41	5		T21	2		T138	2
all_values[3]	auto[1]	auto[0]	auto[1]	91	1			T41	3		T21	3		T124	1
all_values[3]	auto[1]	auto[1]	auto[1]	66	1			T41	1		T21	2		T124	2
all_values[4]	auto[0]	auto[0]	auto[0]	29	1			T44	2		T297	2		T298	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T41	4		T21	3		T124	1
all_values[4]	auto[0]	auto[1]	auto[0]	23	1			T21	2		T124	1		T297	1
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T41	3		T21	3		T124	2
all_values[4]	auto[1]	auto[0]	auto[1]	77	1			T41	4		T21	4		T138	1
all_values[4]	auto[1]	auto[1]	auto[1]	68	1			T21	2		T124	3		T138	4
all_values[5]	auto[0]	auto[0]	auto[0]	33	1			T21	2		T138	1		T297	1
all_values[5]	auto[0]	auto[0]	auto[1]	79	1			T41	4		T21	1		T124	2
all_values[5]	auto[0]	auto[1]	auto[0]	21	1			T139	2		T44	2		T293	1
all_values[5]	auto[0]	auto[1]	auto[1]	79	1			T41	3		T21	5		T124	2
all_values[5]	auto[1]	auto[0]	auto[1]	91	1			T41	3		T21	1		T124	1
all_values[5]	auto[1]	auto[1]	auto[1]	75	1			T41	1		T21	5		T124	2
all_values[6]	auto[0]	auto[0]	auto[0]	28	1			T21	1		T44	3		T297	2
all_values[6]	auto[0]	auto[0]	auto[1]	72	1			T41	1		T21	4		T124	2
all_values[6]	auto[0]	auto[1]	auto[0]	25	1			T138	3		T44	1		T140	2
all_values[6]	auto[0]	auto[1]	auto[1]	86	1			T41	6		T21	3		T124	2
all_values[6]	auto[1]	auto[0]	auto[1]	82	1			T41	2		T21	4		T124	1
all_values[6]	auto[1]	auto[1]	auto[1]	85	1			T41	2		T21	2		T124	2
all_values[7]	auto[0]	auto[0]	auto[0]	32	1			T21	1		T139	2		T141	2
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T41	1		T21	5		T138	1
all_values[7]	auto[0]	auto[1]	auto[0]	19	1			T124	1		T138	2		T297	1
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T41	3		T21	2		T124	3
all_values[7]	auto[1]	auto[0]	auto[1]	84	1			T41	2		T21	4		T124	1
all_values[7]	auto[1]	auto[1]	auto[1]	70	1			T41	5		T21	2		T124	2
all_values[8]	auto[0]	auto[0]	auto[0]	35	1			T124	2		T44	1		T297	2
all_values[8]	auto[0]	auto[0]	auto[1]	70	1			T41	2		T21	4		T124	1
all_values[8]	auto[0]	auto[1]	auto[0]	18	1			T44	2		T293	2		T297	1
all_values[8]	auto[0]	auto[1]	auto[1]	93	1			T41	4		T21	5		T124	3
all_values[8]	auto[1]	auto[0]	auto[1]	86	1			T41	1		T21	2		T138	1
all_values[8]	auto[1]	auto[1]	auto[1]	76	1			T41	4		T21	3		T124	1
all_values[9]	auto[0]	auto[0]	auto[0]	33	1			T139	1		T44	1		T291	1
all_values[9]	auto[0]	auto[0]	auto[1]	72	1			T41	2		T21	3		T124	1
all_values[9]	auto[0]	auto[1]	auto[0]	24	1			T21	3		T298	1		T299	2
all_values[9]	auto[0]	auto[1]	auto[1]	83	1			T41	2		T21	3		T124	3
all_values[9]	auto[1]	auto[0]	auto[1]	79	1			T41	1		T21	5		T124	1
all_values[9]	auto[1]	auto[1]	auto[1]	87	1			T41	6		T124	2		T138	2
all_values[10]	auto[0]	auto[0]	auto[0]	25	1			T124	1		T138	1		T140	2
all_values[10]	auto[0]	auto[0]	auto[1]	83	1			T41	5		T21	3		T138	5
all_values[10]	auto[0]	auto[1]	auto[0]	26	1			T138	3		T44	2		T291	1
all_values[10]	auto[0]	auto[1]	auto[1]	87	1			T41	2		T21	4		T124	3
all_values[10]	auto[1]	auto[0]	auto[1]	75	1			T21	4		T124	1		T138	1
all_values[10]	auto[1]	auto[1]	auto[1]	82	1			T41	4		T21	3		T124	2
all_values[11]	auto[0]	auto[0]	auto[0]	45	1			T41	3		T138	2		T139	1
all_values[11]	auto[0]	auto[0]	auto[1]	69	1			T41	2		T21	3		T124	1
all_values[11]	auto[0]	auto[1]	auto[0]	22	1			T41	2		T138	2		T141	2
all_values[11]	auto[0]	auto[1]	auto[1]	82	1			T21	5		T124	2		T138	2
all_values[11]	auto[1]	auto[0]	auto[1]	78	1			T41	2		T21	3		T124	1
all_values[11]	auto[1]	auto[1]	auto[1]	82	1			T41	2		T21	3		T124	3
all_values[12]	auto[0]	auto[0]	auto[0]	28	1			T21	3		T44	2		T141	1
all_values[12]	auto[0]	auto[0]	auto[1]	80	1			T41	3		T21	4		T124	1
all_values[12]	auto[0]	auto[1]	auto[0]	26	1			T41	1		T21	2		T293	3
all_values[12]	auto[0]	auto[1]	auto[1]	76	1			T41	1		T21	1		T124	3
all_values[12]	auto[1]	auto[0]	auto[1]	88	1			T41	4		T21	3		T124	1
all_values[12]	auto[1]	auto[1]	auto[1]	80	1			T41	2		T21	1		T124	2
all_values[13]	auto[0]	auto[0]	auto[0]	34	1			T41	2		T139	2		T293	1
all_values[13]	auto[0]	auto[0]	auto[1]	94	1			T41	5		T21	2		T124	1
all_values[13]	auto[0]	auto[1]	auto[0]	30	1			T21	2		T139	2		T300	2
all_values[13]	auto[0]	auto[1]	auto[1]	70	1			T41	2		T21	5		T124	4
all_values[13]	auto[1]	auto[0]	auto[1]	79	1			T41	2		T21	3		T138	3
all_values[13]	auto[1]	auto[1]	auto[1]	71	1			T21	2		T124	2		T138	5
all_values[14]	auto[0]	auto[0]	auto[0]	45	1			T138	2		T139	2		T291	2
all_values[14]	auto[0]	auto[0]	auto[1]	71	1			T41	4		T21	2		T138	2
all_values[14]	auto[0]	auto[1]	auto[0]	20	1			T139	2		T291	1		T301	2
all_values[14]	auto[0]	auto[1]	auto[1]	82	1			T41	2		T21	6		T124	1
all_values[14]	auto[1]	auto[0]	auto[1]	94	1			T41	4		T21	3		T124	4
all_values[14]	auto[1]	auto[1]	auto[1]	66	1			T41	1		T21	3		T124	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal