Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	758751	1			T1	1		T2	2		T3	11
all_values[1]	758751	1			T1	1		T2	2		T3	11
all_values[2]	758751	1			T1	1		T2	2		T3	11
all_values[3]	758751	1			T1	1		T2	2		T3	11
all_values[4]	758751	1			T1	1		T2	2		T3	11
all_values[5]	758751	1			T1	1		T2	2		T3	11
all_values[6]	758751	1			T1	1		T2	2		T3	11
all_values[7]	758751	1			T1	1		T2	2		T3	11
all_values[8]	758751	1			T1	1		T2	2		T3	11
all_values[9]	758751	1			T1	1		T2	2		T3	11
all_values[10]	758751	1			T1	1		T2	2		T3	11
all_values[11]	758751	1			T1	1		T2	2		T3	11
all_values[12]	758751	1			T1	1		T2	2		T3	11
all_values[13]	758751	1			T1	1		T2	2		T3	11
all_values[14]	758751	1			T1	1		T2	2		T3	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9347179

1

T1

15

T2

30

T3

165

auto[1]

2034086

1

T4

24

T5

4

T6

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10861781

1

T1

15

T2

30

T3

165

auto[1]

519484

1

T119

275

T202

350045

T203

514

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114979	1			T1	1		T2	2		T3	11
all_values[0]	auto[0]	auto[1]	2667	1			T119	13		T202	224		T203	26
all_values[0]	auto[1]	auto[0]	604258	1			T4	12		T5	2		T6	2
all_values[0]	auto[1]	auto[1]	36847	1			T119	5		T202	26702		T203	12
all_values[1]	auto[0]	auto[0]	724257	1			T1	1		T2	2		T3	11
all_values[1]	auto[0]	auto[1]	34092	1			T119	16		T202	26925		T203	34
all_values[1]	auto[1]	auto[0]	254	1			T168	9		T282	2		T283	8
all_values[1]	auto[1]	auto[1]	148	1			T119	2		T202	2		T203	5
all_values[2]	auto[0]	auto[0]	719072	1			T1	1		T2	2		T3	11
all_values[2]	auto[0]	auto[1]	39353	1			T119	14		T202	26925		T203	32
all_values[2]	auto[1]	auto[0]	192	1			T9	1		T210	2		T68	1
all_values[2]	auto[1]	auto[1]	134	1			T119	5		T202	2		T203	5
all_values[3]	auto[0]	auto[0]	719253	1			T1	1		T2	2		T3	11
all_values[3]	auto[0]	auto[1]	39344	1			T119	18		T202	26923		T203	34
all_values[3]	auto[1]	auto[1]	154	1			T119	1		T202	4		T203	5
all_values[4]	auto[0]	auto[0]	719246	1			T1	1		T2	2		T3	11
all_values[4]	auto[0]	auto[1]	39360	1			T119	15		T202	26926		T203	33
all_values[4]	auto[1]	auto[0]	14	1			T11	2		T12	1		T284	3
all_values[4]	auto[1]	auto[1]	131	1			T119	2		T202	1		T203	5
all_values[5]	auto[0]	auto[0]	719293	1			T1	1		T2	2		T3	11
all_values[5]	auto[0]	auto[1]	39310	1			T119	15		T202	26925		T203	3
all_values[5]	auto[1]	auto[1]	148	1			T119	4		T202	1		T203	5
all_values[6]	auto[0]	auto[0]	726160	1			T1	1		T2	2		T3	11
all_values[6]	auto[0]	auto[1]	32414	1			T119	15		T202	26923		T203	30
all_values[6]	auto[1]	auto[1]	177	1			T119	4		T202	4		T203	7
all_values[7]	auto[0]	auto[0]	691224	1			T1	1		T2	2		T3	11
all_values[7]	auto[0]	auto[1]	38077	1			T119	14		T202	26647		T203	29
all_values[7]	auto[1]	auto[0]	28032	1			T7	4		T10	1		T19	38
all_values[7]	auto[1]	auto[1]	1418	1			T119	5		T202	280		T203	10
all_values[8]	auto[0]	auto[0]	719244	1			T1	1		T2	2		T3	11
all_values[8]	auto[0]	auto[1]	39349	1			T119	15		T202	26925		T203	31
all_values[8]	auto[1]	auto[1]	158	1			T119	4		T202	2		T203	8
all_values[9]	auto[0]	auto[0]	149574	1			T1	1		T2	2		T3	11
all_values[9]	auto[0]	auto[1]	3912	1			T119	11		T202	550		T203	33
all_values[9]	auto[1]	auto[0]	569683	1			T8	1		T9	1		T10	1
all_values[9]	auto[1]	auto[1]	35582	1			T119	7		T202	26377		T203	6
all_values[10]	auto[0]	auto[0]	719242	1			T1	1		T2	2		T3	11
all_values[10]	auto[0]	auto[1]	39368	1			T119	16		T202	26924		T203	34
all_values[10]	auto[1]	auto[1]	141	1			T119	3		T202	2		T203	4
all_values[11]	auto[0]	auto[0]	2354	1			T1	1		T2	2		T3	11
all_values[11]	auto[0]	auto[1]	271	1			T119	11		T202	10		T203	26
all_values[11]	auto[1]	auto[0]	716875	1			T4	12		T5	2		T6	2
all_values[11]	auto[1]	auto[1]	39251	1			T119	4		T202	26916		T203	13
all_values[12]	auto[0]	auto[0]	719216	1			T1	1		T2	2		T3	11
all_values[12]	auto[0]	auto[1]	39327	1			T119	16		T202	26924		T203	6
all_values[12]	auto[1]	auto[0]	71	1			T68	1		T73	1		T74	1
all_values[12]	auto[1]	auto[1]	137	1			T119	3		T202	1		T203	3
all_values[13]	auto[0]	auto[0]	747829	1			T1	1		T2	2		T3	11
all_values[13]	auto[0]	auto[1]	10769	1			T119	17		T203	34		T26	5261
all_values[13]	auto[1]	auto[1]	153	1			T119	1		T203	4		T26	3
all_values[14]	auto[0]	auto[0]	751459	1			T1	1		T2	2		T3	11
all_values[14]	auto[0]	auto[1]	7164	1			T119	16		T203	29		T26	5260
all_values[14]	auto[1]	auto[1]	128	1			T119	3		T203	8		T26	3