Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	758751	1			T1	1		T2	2		T3	11
all_pins[1]	758751	1			T1	1		T2	2		T3	11
all_pins[2]	758751	1			T1	1		T2	2		T3	11
all_pins[3]	758751	1			T1	1		T2	2		T3	11
all_pins[4]	758751	1			T1	1		T2	2		T3	11
all_pins[5]	758751	1			T1	1		T2	2		T3	11
all_pins[6]	758751	1			T1	1		T2	2		T3	11
all_pins[7]	758751	1			T1	1		T2	2		T3	11
all_pins[8]	758751	1			T1	1		T2	2		T3	11
all_pins[9]	758751	1			T1	1		T2	2		T3	11
all_pins[10]	758751	1			T1	1		T2	2		T3	11
all_pins[11]	758751	1			T1	1		T2	2		T3	11
all_pins[12]	758751	1			T1	1		T2	2		T3	11
all_pins[13]	758751	1			T1	1		T2	2		T3	11
all_pins[14]	758751	1			T1	1		T2	2		T3	11

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9352964	1			T1	15		T2	30		T3	165
values[0x1]	2028301	1			T4	24		T5	4		T6	4
transitions[0x0=>0x1]	2027732	1			T4	24		T5	4		T6	4
transitions[0x1=>0x0]	2026433	1			T4	23		T5	3		T6	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	121262	1			T1	1		T2	2		T3	11
all_pins[0]	values[0x1]	637489	1			T4	12		T5	2		T6	2
all_pins[0]	transitions[0x0=>0x1]	637214	1			T4	12		T5	2		T6	2
all_pins[0]	transitions[0x1=>0x0]	80	1			T202	1		T291	1		T292	32
all_pins[1]	values[0x0]	758396	1			T1	1		T2	2		T3	11
all_pins[1]	values[0x1]	355	1			T168	11		T282	2		T283	8
all_pins[1]	transitions[0x0=>0x1]	340	1			T168	11		T282	2		T283	8
all_pins[1]	transitions[0x1=>0x0]	104	1			T9	1		T293	1		T232	1
all_pins[2]	values[0x0]	758632	1			T1	1		T2	2		T3	11
all_pins[2]	values[0x1]	119	1			T9	1		T293	1		T232	1
all_pins[2]	transitions[0x0=>0x1]	104	1			T9	1		T293	1		T232	1
all_pins[2]	transitions[0x1=>0x0]	57	1			T202	3		T203	4		T249	9
all_pins[3]	values[0x0]	758679	1			T1	1		T2	2		T3	11
all_pins[3]	values[0x1]	72	1			T119	1		T202	4		T203	4
all_pins[3]	transitions[0x0=>0x1]	56	1			T119	1		T202	3		T203	2
all_pins[3]	transitions[0x1=>0x0]	58	1			T11	2		T12	1		T284	4
all_pins[4]	values[0x0]	758677	1			T1	1		T2	2		T3	11
all_pins[4]	values[0x1]	74	1			T11	2		T12	1		T284	4
all_pins[4]	transitions[0x0=>0x1]	59	1			T11	2		T12	1		T284	4
all_pins[4]	transitions[0x1=>0x0]	53	1			T203	2		T26	3		T136	2
all_pins[5]	values[0x0]	758683	1			T1	1		T2	2		T3	11
all_pins[5]	values[0x1]	68	1			T203	2		T26	3		T249	2
all_pins[5]	transitions[0x0=>0x1]	43	1			T203	2		T26	2		T136	2
all_pins[5]	transitions[0x1=>0x0]	68	1			T119	2		T202	4		T203	3
all_pins[6]	values[0x0]	758658	1			T1	1		T2	2		T3	11
all_pins[6]	values[0x1]	93	1			T119	2		T202	4		T203	3
all_pins[6]	transitions[0x0=>0x1]	68	1			T119	2		T202	4		T203	3
all_pins[6]	transitions[0x1=>0x0]	32216	1			T7	4		T10	1		T19	47
all_pins[7]	values[0x0]	726510	1			T1	1		T2	2		T3	11
all_pins[7]	values[0x1]	32241	1			T7	4		T10	1		T19	47
all_pins[7]	transitions[0x0=>0x1]	32219	1			T7	4		T10	1		T19	47
all_pins[7]	transitions[0x1=>0x0]	59	1			T119	3		T202	1		T203	3
all_pins[8]	values[0x0]	758670	1			T1	1		T2	2		T3	11
all_pins[8]	values[0x1]	81	1			T119	3		T202	1		T203	4
all_pins[8]	transitions[0x0=>0x1]	69	1			T119	3		T202	1		T203	3
all_pins[8]	transitions[0x1=>0x0]	605204	1			T8	1		T9	1		T10	1
all_pins[9]	values[0x0]	153535	1			T1	1		T2	2		T3	11
all_pins[9]	values[0x1]	605216	1			T8	1		T9	1		T10	1
all_pins[9]	transitions[0x0=>0x1]	605197	1			T8	1		T9	1		T10	1
all_pins[9]	transitions[0x1=>0x0]	48	1			T119	1		T202	1		T203	1
all_pins[10]	values[0x0]	758684	1			T1	1		T2	2		T3	11
all_pins[10]	values[0x1]	67	1			T119	2		T202	1		T203	2
all_pins[10]	transitions[0x0=>0x1]	41	1			T119	2		T203	2		T249	3
all_pins[10]	transitions[0x1=>0x0]	752100	1			T4	12		T5	2		T6	2
all_pins[11]	values[0x0]	6625	1			T1	1		T2	2		T3	11
all_pins[11]	values[0x1]	752126	1			T4	12		T5	2		T6	2
all_pins[11]	transitions[0x0=>0x1]	752077	1			T4	12		T5	2		T6	2
all_pins[11]	transitions[0x1=>0x0]	93	1			T68	1		T73	1		T74	1
all_pins[12]	values[0x0]	758609	1			T1	1		T2	2		T3	11
all_pins[12]	values[0x1]	142	1			T68	1		T73	1		T232	1
all_pins[12]	transitions[0x0=>0x1]	128	1			T68	1		T73	1		T232	1
all_pins[12]	transitions[0x1=>0x0]	74	1			T119	1		T203	2		T26	3
all_pins[13]	values[0x0]	758663	1			T1	1		T2	2		T3	11
all_pins[13]	values[0x1]	88	1			T119	1		T203	2		T26	3
all_pins[13]	transitions[0x0=>0x1]	72	1			T119	1		T203	2		T26	2
all_pins[13]	transitions[0x1=>0x0]	54	1			T119	1		T203	3		T249	4
all_pins[14]	values[0x0]	758681	1			T1	1		T2	2		T3	11
all_pins[14]	values[0x1]	70	1			T119	1		T203	3		T26	1
all_pins[14]	transitions[0x0=>0x1]	45	1			T26	1		T249	8		T136	2
all_pins[14]	transitions[0x1=>0x0]	636165	1			T4	11		T5	1		T6	1