Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	346	1			T119	7		T202	4		T203	11
all_values[1]	346	1			T119	7		T202	4		T203	11
all_values[2]	346	1			T119	7		T202	4		T203	11
all_values[3]	346	1			T119	7		T202	4		T203	11
all_values[4]	346	1			T119	7		T202	4		T203	11
all_values[5]	346	1			T119	7		T202	4		T203	11
all_values[6]	346	1			T119	7		T202	4		T203	11
all_values[7]	346	1			T119	7		T202	4		T203	11
all_values[8]	346	1			T119	7		T202	4		T203	11
all_values[9]	346	1			T119	7		T202	4		T203	11
all_values[10]	346	1			T119	7		T202	4		T203	11
all_values[11]	346	1			T119	7		T202	4		T203	11
all_values[12]	346	1			T119	7		T202	4		T203	11
all_values[13]	346	1			T119	7		T202	4		T203	11
all_values[14]	346	1			T119	7		T202	4		T203	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2764

1

T119

61

T202

17

T203

80

auto[1]

2426

1

T119

44

T202

43

T203

85

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

864

1

T119

10

T202

14

T203

19

auto[1]

4326

1

T119

95

T202

46

T203

146

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3071

1

T119

62

T202

37

T203

97

auto[1]

2119

1

T119

43

T202

23

T203

68

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	28	1			T119	1		T137	4		T138	1
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T203	2		T26	3		T249	7
all_values[0]	auto[0]	auto[1]	auto[0]	19	1			T202	1		T203	1		T249	1
all_values[0]	auto[0]	auto[1]	auto[1]	76	1			T119	3		T202	2		T203	3
all_values[0]	auto[1]	auto[0]	auto[1]	77	1			T119	2		T202	1		T26	1
all_values[0]	auto[1]	auto[1]	auto[1]	66	1			T119	1		T203	5		T26	1
all_values[1]	auto[0]	auto[0]	auto[0]	23	1			T119	1		T294	1		T295	1
all_values[1]	auto[0]	auto[0]	auto[1]	84	1			T119	2		T202	2		T203	4
all_values[1]	auto[0]	auto[1]	auto[0]	24	1			T296	4		T297	1		T298	1
all_values[1]	auto[0]	auto[1]	auto[1]	69	1			T119	2		T202	1		T203	2
all_values[1]	auto[1]	auto[0]	auto[1]	84	1			T119	2		T203	4		T26	1
all_values[1]	auto[1]	auto[1]	auto[1]	62	1			T202	1		T203	1		T26	2
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T203	1		T249	1		T136	2
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T119	2		T202	1		T203	3
all_values[2]	auto[0]	auto[1]	auto[0]	26	1			T203	1		T26	1		T296	1
all_values[2]	auto[0]	auto[1]	auto[1]	71	1			T202	1		T203	1		T26	3
all_values[2]	auto[1]	auto[0]	auto[1]	71	1			T119	3		T203	5		T249	6
all_values[2]	auto[1]	auto[1]	auto[1]	63	1			T119	2		T202	2		T26	3
all_values[3]	auto[0]	auto[0]	auto[0]	38	1			T137	1		T138	1		T299	1
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T119	3		T203	4		T26	1
all_values[3]	auto[0]	auto[1]	auto[0]	21	1			T26	1		T249	1		T296	1
all_values[3]	auto[0]	auto[1]	auto[1]	62	1			T119	2		T202	1		T203	1
all_values[3]	auto[1]	auto[0]	auto[1]	81	1			T119	2		T203	3		T26	1
all_values[3]	auto[1]	auto[1]	auto[1]	60	1			T202	3		T203	3		T26	2
all_values[4]	auto[0]	auto[0]	auto[0]	37	1			T119	2		T136	1		T296	1
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T119	1		T202	2		T203	3
all_values[4]	auto[0]	auto[1]	auto[0]	29	1			T203	1		T296	1		T139	1
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T119	2		T202	1		T203	2
all_values[4]	auto[1]	auto[0]	auto[1]	74	1			T119	2		T203	2		T26	1
all_values[4]	auto[1]	auto[1]	auto[1]	57	1			T202	1		T203	3		T26	1
all_values[5]	auto[0]	auto[0]	auto[0]	38	1			T203	1		T138	1		T299	3
all_values[5]	auto[0]	auto[0]	auto[1]	76	1			T119	3		T203	2		T26	1
all_values[5]	auto[0]	auto[1]	auto[0]	32	1			T202	1		T203	4		T300	1
all_values[5]	auto[0]	auto[1]	auto[1]	63	1			T202	2		T203	1		T26	4
all_values[5]	auto[1]	auto[0]	auto[1]	78	1			T119	4		T202	1		T203	1
all_values[5]	auto[1]	auto[1]	auto[1]	59	1			T203	2		T249	4		T136	1
all_values[6]	auto[0]	auto[0]	auto[0]	19	1			T136	4		T296	3		T295	1
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T203	4		T26	1		T249	4
all_values[6]	auto[0]	auto[1]	auto[0]	23	1			T203	2		T26	1		T296	1
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T119	4		T202	1		T203	3
all_values[6]	auto[1]	auto[0]	auto[1]	78	1			T119	1		T203	1		T26	2
all_values[6]	auto[1]	auto[1]	auto[1]	75	1			T119	2		T202	3		T203	1
all_values[7]	auto[0]	auto[0]	auto[0]	32	1			T137	1		T299	1		T301	1
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T119	1		T202	1		T203	5
all_values[7]	auto[0]	auto[1]	auto[0]	31	1			T26	1		T249	1		T136	1
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T119	2		T202	2		T249	5
all_values[7]	auto[1]	auto[0]	auto[1]	69	1			T119	2		T203	4		T26	1
all_values[7]	auto[1]	auto[1]	auto[1]	65	1			T119	2		T202	1		T203	2
all_values[8]	auto[0]	auto[0]	auto[0]	28	1			T136	1		T301	4		T302	1
all_values[8]	auto[0]	auto[0]	auto[1]	72	1			T119	1		T203	1		T26	1
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T302	2		T303	1		T304	1
all_values[8]	auto[0]	auto[1]	auto[1]	69	1			T119	3		T202	1		T203	2
all_values[8]	auto[1]	auto[0]	auto[1]	84	1			T119	2		T202	1		T203	5
all_values[8]	auto[1]	auto[1]	auto[1]	68	1			T119	1		T202	2		T203	3
all_values[9]	auto[0]	auto[0]	auto[0]	46	1			T119	1		T26	1		T137	4
all_values[9]	auto[0]	auto[0]	auto[1]	71	1			T119	3		T203	1		T26	1
all_values[9]	auto[0]	auto[1]	auto[0]	16	1			T136	1		T138	1		T294	1
all_values[9]	auto[0]	auto[1]	auto[1]	79	1			T119	1		T202	2		T203	6
all_values[9]	auto[1]	auto[0]	auto[1]	81	1			T119	1		T202	1		T203	3
all_values[9]	auto[1]	auto[1]	auto[1]	53	1			T119	1		T202	1		T203	1
all_values[10]	auto[0]	auto[0]	auto[0]	27	1			T26	1		T138	1		T139	2
all_values[10]	auto[0]	auto[0]	auto[1]	75	1			T203	1		T26	1		T249	5
all_values[10]	auto[0]	auto[1]	auto[0]	25	1			T202	1		T203	1		T26	1
all_values[10]	auto[0]	auto[1]	auto[1]	78	1			T119	4		T202	1		T203	5
all_values[10]	auto[1]	auto[0]	auto[1]	75	1			T119	1		T202	1		T203	3
all_values[10]	auto[1]	auto[1]	auto[1]	66	1			T119	2		T202	1		T203	1
all_values[11]	auto[0]	auto[0]	auto[0]	24	1			T119	2		T139	1		T305	1
all_values[11]	auto[0]	auto[0]	auto[1]	70	1			T119	1		T203	3		T26	1
all_values[11]	auto[0]	auto[1]	auto[0]	13	1			T119	2		T202	1		T303	1
all_values[11]	auto[0]	auto[1]	auto[1]	79	1			T202	1		T203	3		T26	3
all_values[11]	auto[1]	auto[0]	auto[1]	77	1			T119	2		T202	1		T203	1
all_values[11]	auto[1]	auto[1]	auto[1]	83	1			T202	1		T203	4		T26	2
all_values[12]	auto[0]	auto[0]	auto[0]	40	1			T202	1		T26	2		T137	4
all_values[12]	auto[0]	auto[0]	auto[1]	65	1			T119	1		T203	2		T26	1
all_values[12]	auto[0]	auto[1]	auto[0]	26	1			T202	1		T203	4		T302	3
all_values[12]	auto[0]	auto[1]	auto[1]	78	1			T119	3		T202	1		T203	2
all_values[12]	auto[1]	auto[0]	auto[1]	71	1			T119	2		T203	1		T26	1
all_values[12]	auto[1]	auto[1]	auto[1]	66	1			T119	1		T202	1		T203	2
all_values[13]	auto[0]	auto[0]	auto[0]	36	1			T119	1		T202	2		T249	2
all_values[13]	auto[0]	auto[0]	auto[1]	80	1			T119	2		T203	4		T26	3
all_values[13]	auto[0]	auto[1]	auto[0]	23	1			T202	2		T203	1		T249	2
all_values[13]	auto[0]	auto[1]	auto[1]	65	1			T119	2		T203	2		T26	1
all_values[13]	auto[1]	auto[0]	auto[1]	67	1			T203	2		T249	5		T296	2
all_values[13]	auto[1]	auto[1]	auto[1]	75	1			T119	2		T203	2		T26	3
all_values[14]	auto[0]	auto[0]	auto[0]	35	1			T202	2		T249	1		T136	1
all_values[14]	auto[0]	auto[0]	auto[1]	68	1			T119	4		T203	3		T26	2
all_values[14]	auto[0]	auto[1]	auto[0]	35	1			T202	2		T203	2		T26	1
all_values[14]	auto[0]	auto[1]	auto[1]	74	1			T203	3		T249	3		T136	1
all_values[14]	auto[1]	auto[0]	auto[1]	74	1			T119	3		T203	1		T26	1
all_values[14]	auto[1]	auto[1]	auto[1]	60	1			T203	2		T26	3		T249	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal