Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	850839	1			T1	1		T2	2		T3	4
all_values[1]	850839	1			T1	1		T2	2		T3	4
all_values[2]	850839	1			T1	1		T2	2		T3	4
all_values[3]	850839	1			T1	1		T2	2		T3	4
all_values[4]	850839	1			T1	1		T2	2		T3	4
all_values[5]	850839	1			T1	1		T2	2		T3	4
all_values[6]	850839	1			T1	1		T2	2		T3	4
all_values[7]	850839	1			T1	1		T2	2		T3	4
all_values[8]	850839	1			T1	1		T2	2		T3	4
all_values[9]	850839	1			T1	1		T2	2		T3	4
all_values[10]	850839	1			T1	1		T2	2		T3	4
all_values[11]	850839	1			T1	1		T2	2		T3	4
all_values[12]	850839	1			T1	1		T2	2		T3	4
all_values[13]	850839	1			T1	1		T2	2		T3	4
all_values[14]	850839	1			T1	1		T2	2		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10479900

1

T1

15

T2

30

T3

60

auto[1]

2282685

1

T4

6

T5

6

T6

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12265055

1

T1

15

T2

30

T3

60

auto[1]

497530

1

T16

7414

T21

43097

T119

52336

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	111228	1			T1	1		T2	2		T3	4
all_values[0]	auto[0]	auto[1]	1636	1			T16	11		T21	16		T119	167
all_values[0]	auto[1]	auto[0]	706361	1			T4	2		T5	2		T6	2
all_values[0]	auto[1]	auto[1]	31614	1			T16	558		T21	2857		T119	3322
all_values[1]	auto[0]	auto[0]	817304	1			T1	1		T2	2		T3	4
all_values[1]	auto[0]	auto[1]	33091	1			T16	567		T21	2868		T119	3481
all_values[1]	auto[1]	auto[0]	289	1			T187	1		T264	1		T265	7
all_values[1]	auto[1]	auto[1]	155	1			T16	3		T21	4		T119	9
all_values[2]	auto[0]	auto[0]	817416	1			T1	1		T2	2		T3	4
all_values[2]	auto[0]	auto[1]	33095	1			T16	567		T21	2871		T119	3484
all_values[2]	auto[1]	auto[0]	193	1			T155	2		T156	1		T59	1
all_values[2]	auto[1]	auto[1]	135	1			T16	3		T21	3		T119	6
all_values[3]	auto[0]	auto[0]	817594	1			T1	1		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	33050	1			T16	565		T21	2869		T119	3483
all_values[3]	auto[1]	auto[1]	195	1			T16	4		T21	4		T119	7
all_values[4]	auto[0]	auto[0]	818145	1			T1	1		T2	2		T3	4
all_values[4]	auto[0]	auto[1]	32531	1			T16	4		T21	2869		T119	3482
all_values[4]	auto[1]	auto[0]	21	1			T244	1		T24	1		T254	1
all_values[4]	auto[1]	auto[1]	142	1			T16	2		T21	5		T119	7
all_values[5]	auto[0]	auto[0]	817576	1			T1	1		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	33090	1			T16	566		T21	2870		T119	3486
all_values[5]	auto[1]	auto[1]	173	1			T16	3		T21	1		T119	4
all_values[6]	auto[0]	auto[0]	817598	1			T1	1		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	33081	1			T16	565		T21	2870		T119	3481
all_values[6]	auto[1]	auto[1]	160	1			T16	4		T21	4		T119	9
all_values[7]	auto[0]	auto[0]	790962	1			T1	1		T2	2		T3	4
all_values[7]	auto[0]	auto[1]	32558	1			T16	564		T21	2778		T119	3356
all_values[7]	auto[1]	auto[0]	26638	1			T4	1		T5	1		T10	56
all_values[7]	auto[1]	auto[1]	681	1			T16	5		T21	94		T119	128
all_values[8]	auto[0]	auto[0]	817601	1			T1	1		T2	2		T3	4
all_values[8]	auto[0]	auto[1]	33056	1			T16	567		T21	2867		T119	3483
all_values[8]	auto[1]	auto[1]	182	1			T16	3		T21	7		T119	7
all_values[9]	auto[0]	auto[0]	181954	1			T1	1		T2	2		T3	4
all_values[9]	auto[0]	auto[1]	1966	1			T16	567		T21	111		T119	212
all_values[9]	auto[1]	auto[0]	635639	1			T4	1		T5	1		T10	21
all_values[9]	auto[1]	auto[1]	31280	1			T16	3		T21	2761		T119	3278
all_values[10]	auto[0]	auto[0]	817600	1			T1	1		T2	2		T3	4
all_values[10]	auto[0]	auto[1]	33092	1			T16	565		T21	2872		T119	3483
all_values[10]	auto[1]	auto[1]	147	1			T16	4		T21	2		T119	7
all_values[11]	auto[0]	auto[0]	2468	1			T1	1		T2	2		T3	4
all_values[11]	auto[0]	auto[1]	251	1			T16	11		T21	16		T119	16
all_values[11]	auto[1]	auto[0]	815135	1			T4	2		T5	2		T6	2
all_values[11]	auto[1]	auto[1]	32985	1			T16	558		T21	2858		T119	3473
all_values[12]	auto[0]	auto[0]	818087	1			T1	1		T2	2		T3	4
all_values[12]	auto[0]	auto[1]	32536	1			T16	4		T21	2868		T119	3484
all_values[12]	auto[1]	auto[0]	63	1			T59	1		T266	1		T60	1
all_values[12]	auto[1]	auto[1]	153	1			T16	2		T21	5		T119	5
all_values[13]	auto[0]	auto[0]	817590	1			T1	1		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	33092	1			T16	567		T21	2871		T119	3486
all_values[13]	auto[1]	auto[1]	157	1			T16	3		T21	2		T119	2
all_values[14]	auto[0]	auto[0]	817593	1			T1	1		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	33059	1			T16	565		T21	2873		T119	3486
all_values[14]	auto[1]	auto[1]	187	1			T16	4		T21	1		T119	2