Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	850839	1			T1	1		T2	2		T3	4
all_pins[1]	850839	1			T1	1		T2	2		T3	4
all_pins[2]	850839	1			T1	1		T2	2		T3	4
all_pins[3]	850839	1			T1	1		T2	2		T3	4
all_pins[4]	850839	1			T1	1		T2	2		T3	4
all_pins[5]	850839	1			T1	1		T2	2		T3	4
all_pins[6]	850839	1			T1	1		T2	2		T3	4
all_pins[7]	850839	1			T1	1		T2	2		T3	4
all_pins[8]	850839	1			T1	1		T2	2		T3	4
all_pins[9]	850839	1			T1	1		T2	2		T3	4
all_pins[10]	850839	1			T1	1		T2	2		T3	4
all_pins[11]	850839	1			T1	1		T2	2		T3	4
all_pins[12]	850839	1			T1	1		T2	2		T3	4
all_pins[13]	850839	1			T1	1		T2	2		T3	4
all_pins[14]	850839	1			T1	1		T2	2		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10485158	1			T1	15		T2	30		T3	60
values[0x1]	2277427	1			T4	6		T5	6		T6	4
transitions[0x0=>0x1]	2276750	1			T4	6		T5	6		T6	4
transitions[0x1=>0x0]	2275440	1			T4	5		T5	5		T6	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	116079	1			T1	1		T2	2		T3	4
all_pins[0]	values[0x1]	734760	1			T4	2		T5	2		T6	2
all_pins[0]	transitions[0x0=>0x1]	734374	1			T4	2		T5	2		T6	2
all_pins[0]	transitions[0x1=>0x0]	61	1			T264	1		T21	2		T119	2
all_pins[1]	values[0x0]	850392	1			T1	1		T2	2		T3	4
all_pins[1]	values[0x1]	447	1			T187	1		T264	1		T265	8
all_pins[1]	transitions[0x0=>0x1]	429	1			T187	1		T264	1		T265	8
all_pins[1]	transitions[0x1=>0x0]	100	1			T156	1		T266	1		T117	1
all_pins[2]	values[0x0]	850721	1			T1	1		T2	2		T3	4
all_pins[2]	values[0x1]	118	1			T156	1		T266	1		T117	1
all_pins[2]	transitions[0x0=>0x1]	98	1			T156	1		T266	1		T117	1
all_pins[2]	transitions[0x1=>0x0]	74	1			T16	1		T21	3		T119	3
all_pins[3]	values[0x0]	850745	1			T1	1		T2	2		T3	4
all_pins[3]	values[0x1]	94	1			T16	2		T21	3		T119	5
all_pins[3]	transitions[0x0=>0x1]	77	1			T16	2		T21	3		T119	3
all_pins[3]	transitions[0x1=>0x0]	71	1			T244	1		T24	1		T254	1
all_pins[4]	values[0x0]	850751	1			T1	1		T2	2		T3	4
all_pins[4]	values[0x1]	88	1			T244	1		T24	1		T254	1
all_pins[4]	transitions[0x0=>0x1]	71	1			T244	1		T24	1		T254	1
all_pins[4]	transitions[0x1=>0x0]	76	1			T16	1		T119	2		T272	2
all_pins[5]	values[0x0]	850746	1			T1	1		T2	2		T3	4
all_pins[5]	values[0x1]	93	1			T16	1		T119	2		T273	1
all_pins[5]	transitions[0x0=>0x1]	70	1			T16	1		T119	2		T272	1
all_pins[5]	transitions[0x1=>0x0]	56	1			T16	3		T21	1		T119	2
all_pins[6]	values[0x0]	850760	1			T1	1		T2	2		T3	4
all_pins[6]	values[0x1]	79	1			T16	3		T21	1		T119	2
all_pins[6]	transitions[0x0=>0x1]	62	1			T16	3		T21	1		T273	2
all_pins[6]	transitions[0x1=>0x0]	29973	1			T4	1		T5	1		T10	63
all_pins[7]	values[0x0]	820849	1			T1	1		T2	2		T3	4
all_pins[7]	values[0x1]	29990	1			T4	1		T5	1		T10	63
all_pins[7]	transitions[0x0=>0x1]	29975	1			T4	1		T5	1		T10	63
all_pins[7]	transitions[0x1=>0x0]	68	1			T21	2		T119	2		T273	3
all_pins[8]	values[0x0]	850756	1			T1	1		T2	2		T3	4
all_pins[8]	values[0x1]	83	1			T21	4		T119	2		T273	4
all_pins[8]	transitions[0x0=>0x1]	61	1			T21	4		T119	2		T273	2
all_pins[8]	transitions[0x1=>0x0]	666842	1			T4	1		T5	1		T10	21
all_pins[9]	values[0x0]	183975	1			T1	1		T2	2		T3	4
all_pins[9]	values[0x1]	666864	1			T4	1		T5	1		T10	21
all_pins[9]	transitions[0x0=>0x1]	666850	1			T4	1		T5	1		T10	21
all_pins[9]	transitions[0x1=>0x0]	55	1			T21	1		T119	2		T273	1
all_pins[10]	values[0x0]	850770	1			T1	1		T2	2		T3	4
all_pins[10]	values[0x1]	69	1			T21	1		T119	2		T273	1
all_pins[10]	transitions[0x0=>0x1]	56	1			T21	1		T119	2		T274	1
all_pins[10]	transitions[0x1=>0x0]	844412	1			T4	2		T5	2		T6	2
all_pins[11]	values[0x0]	6414	1			T1	1		T2	2		T3	4
all_pins[11]	values[0x1]	844425	1			T4	2		T5	2		T6	2
all_pins[11]	transitions[0x0=>0x1]	844392	1			T4	2		T5	2		T6	2
all_pins[11]	transitions[0x1=>0x0]	105	1			T59	1		T60	1		T44	1
all_pins[12]	values[0x0]	850701	1			T1	1		T2	2		T3	4
all_pins[12]	values[0x1]	138	1			T59	1		T266	1		T60	1
all_pins[12]	transitions[0x0=>0x1]	119	1			T59	1		T266	1		T60	1
all_pins[12]	transitions[0x1=>0x0]	73	1			T16	3		T272	3		T274	1
all_pins[13]	values[0x0]	850747	1			T1	1		T2	2		T3	4
all_pins[13]	values[0x1]	92	1			T16	3		T272	3		T274	2
all_pins[13]	transitions[0x0=>0x1]	64	1			T16	3		T272	3		T274	2
all_pins[13]	transitions[0x1=>0x0]	59	1			T16	1		T21	1		T119	2
all_pins[14]	values[0x0]	850752	1			T1	1		T2	2		T3	4
all_pins[14]	values[0x1]	87	1			T16	1		T21	1		T119	2
all_pins[14]	transitions[0x0=>0x1]	52	1			T16	1		T21	1		T275	1
all_pins[14]	transitions[0x1=>0x0]	733415	1			T4	1		T5	1		T6	1