Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	349	1			T16	8		T21	7		T119	15
all_values[1]	349	1			T16	8		T21	7		T119	15
all_values[2]	349	1			T16	8		T21	7		T119	15
all_values[3]	349	1			T16	8		T21	7		T119	15
all_values[4]	349	1			T16	8		T21	7		T119	15
all_values[5]	349	1			T16	8		T21	7		T119	15
all_values[6]	349	1			T16	8		T21	7		T119	15
all_values[7]	349	1			T16	8		T21	7		T119	15
all_values[8]	349	1			T16	8		T21	7		T119	15
all_values[9]	349	1			T16	8		T21	7		T119	15
all_values[10]	349	1			T16	8		T21	7		T119	15
all_values[11]	349	1			T16	8		T21	7		T119	15
all_values[12]	349	1			T16	8		T21	7		T119	15
all_values[13]	349	1			T16	8		T21	7		T119	15
all_values[14]	349	1			T16	8		T21	7		T119	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2819

1

T16

52

T21

65

T119

132

auto[1]

2416

1

T16

68

T21

40

T119

93

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

837

1

T16

16

T21

13

T119

13

auto[1]

4398

1

T16

104

T21

92

T119

212

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3045

1

T16

71

T21

61

T119

130

auto[1]

2190

1

T16

49

T21

44

T119

95

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	34	1			T21	1		T119	1		T272	1
all_values[0]	auto[0]	auto[0]	auto[1]	71	1			T16	2		T21	1		T119	3
all_values[0]	auto[0]	auto[1]	auto[0]	17	1			T16	1		T276	1		T277	1
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T16	1		T21	2		T119	5
all_values[0]	auto[1]	auto[0]	auto[1]	69	1			T16	3		T21	3		T119	1
all_values[0]	auto[1]	auto[1]	auto[1]	80	1			T16	1		T119	5		T273	2
all_values[1]	auto[0]	auto[0]	auto[0]	41	1			T21	1		T273	1		T272	2
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T21	1		T119	6		T272	1
all_values[1]	auto[0]	auto[1]	auto[0]	12	1			T21	1		T273	2		T272	3
all_values[1]	auto[0]	auto[1]	auto[1]	66	1			T16	5		T273	3		T272	1
all_values[1]	auto[1]	auto[0]	auto[1]	86	1			T16	1		T21	2		T119	5
all_values[1]	auto[1]	auto[1]	auto[1]	69	1			T16	2		T21	2		T119	4
all_values[2]	auto[0]	auto[0]	auto[0]	34	1			T272	1		T274	1		T276	1
all_values[2]	auto[0]	auto[0]	auto[1]	73	1			T16	1		T21	3		T119	5
all_values[2]	auto[0]	auto[1]	auto[0]	33	1			T272	3		T277	1		T278	2
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T16	4		T21	1		T119	4
all_values[2]	auto[1]	auto[0]	auto[1]	66	1			T16	1		T21	3		T119	4
all_values[2]	auto[1]	auto[1]	auto[1]	69	1			T16	2		T119	2		T273	2
all_values[3]	auto[0]	auto[0]	auto[0]	31	1			T21	1		T274	1		T276	1
all_values[3]	auto[0]	auto[0]	auto[1]	75	1			T16	2		T21	1		T119	2
all_values[3]	auto[0]	auto[1]	auto[0]	23	1			T16	1		T275	1		T279	2
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T16	2		T21	2		T119	4
all_values[3]	auto[1]	auto[0]	auto[1]	78	1			T21	1		T119	1		T272	4
all_values[3]	auto[1]	auto[1]	auto[1]	78	1			T16	3		T21	2		T119	8
all_values[4]	auto[0]	auto[0]	auto[0]	39	1			T119	1		T274	4		T275	2
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T16	2		T21	2		T119	6
all_values[4]	auto[0]	auto[1]	auto[0]	25	1			T16	4		T275	1		T120	1
all_values[4]	auto[0]	auto[1]	auto[1]	67	1			T119	1		T273	4		T272	3
all_values[4]	auto[1]	auto[0]	auto[1]	80	1			T16	2		T21	4		T119	5
all_values[4]	auto[1]	auto[1]	auto[1]	62	1			T21	1		T119	2		T273	3
all_values[5]	auto[0]	auto[0]	auto[0]	22	1			T21	1		T272	1		T274	1
all_values[5]	auto[0]	auto[0]	auto[1]	71	1			T16	4		T21	1		T119	5
all_values[5]	auto[0]	auto[1]	auto[0]	17	1			T16	1		T21	2		T277	1
all_values[5]	auto[0]	auto[1]	auto[1]	86	1			T21	2		T119	4		T273	2
all_values[5]	auto[1]	auto[0]	auto[1]	77	1			T16	2		T21	1		T119	4
all_values[5]	auto[1]	auto[1]	auto[1]	76	1			T16	1		T119	2		T273	1
all_values[6]	auto[0]	auto[0]	auto[0]	36	1			T276	4		T120	1		T279	1
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T16	1		T21	3		T119	3
all_values[6]	auto[0]	auto[1]	auto[0]	24	1			T16	1		T276	1		T277	1
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T16	3		T21	1		T119	3
all_values[6]	auto[1]	auto[0]	auto[1]	91	1			T16	2		T21	3		T119	8
all_values[6]	auto[1]	auto[1]	auto[1]	52	1			T16	1		T119	1		T273	2
all_values[7]	auto[0]	auto[0]	auto[0]	34	1			T21	2		T119	3		T120	1
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T16	1		T21	1		T273	3
all_values[7]	auto[0]	auto[1]	auto[0]	24	1			T16	1		T119	2		T120	1
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T16	3		T21	2		T119	3
all_values[7]	auto[1]	auto[0]	auto[1]	82	1			T16	2		T21	1		T119	2
all_values[7]	auto[1]	auto[1]	auto[1]	68	1			T16	1		T21	1		T119	5
all_values[8]	auto[0]	auto[0]	auto[0]	34	1			T274	1		T276	1		T120	1
all_values[8]	auto[0]	auto[0]	auto[1]	76	1			T16	1		T21	3		T119	3
all_values[8]	auto[0]	auto[1]	auto[0]	26	1			T275	4		T120	1		T277	2
all_values[8]	auto[0]	auto[1]	auto[1]	63	1			T16	2		T21	1		T119	4
all_values[8]	auto[1]	auto[0]	auto[1]	72	1			T16	2		T21	1		T119	6
all_values[8]	auto[1]	auto[1]	auto[1]	78	1			T16	3		T21	2		T119	2
all_values[9]	auto[0]	auto[0]	auto[0]	33	1			T21	2		T275	2		T276	1
all_values[9]	auto[0]	auto[0]	auto[1]	86	1			T16	1		T21	3		T119	5
all_values[9]	auto[0]	auto[1]	auto[0]	22	1			T275	1		T278	2		T280	2
all_values[9]	auto[0]	auto[1]	auto[1]	77	1			T16	3		T119	5		T273	1
all_values[9]	auto[1]	auto[0]	auto[1]	83	1			T16	1		T21	2		T119	4
all_values[9]	auto[1]	auto[1]	auto[1]	48	1			T16	3		T119	1		T273	1
all_values[10]	auto[0]	auto[0]	auto[0]	37	1			T273	1		T272	1		T120	3
all_values[10]	auto[0]	auto[0]	auto[1]	75	1			T16	3		T21	4		T119	4
all_values[10]	auto[0]	auto[1]	auto[0]	20	1			T16	1		T273	1		T275	1
all_values[10]	auto[0]	auto[1]	auto[1]	70	1			T21	1		T119	4		T273	2
all_values[10]	auto[1]	auto[0]	auto[1]	85	1			T16	4		T21	2		T119	6
all_values[10]	auto[1]	auto[1]	auto[1]	62	1			T119	1		T273	1		T274	1
all_values[11]	auto[0]	auto[0]	auto[0]	32	1			T272	1		T275	2		T279	1
all_values[11]	auto[0]	auto[0]	auto[1]	73	1			T16	2		T21	2		T119	6
all_values[11]	auto[0]	auto[1]	auto[0]	30	1			T16	1		T119	1		T273	1
all_values[11]	auto[0]	auto[1]	auto[1]	83	1			T16	1		T21	1		T119	4
all_values[11]	auto[1]	auto[0]	auto[1]	76	1			T16	2		T21	1		T119	2
all_values[11]	auto[1]	auto[1]	auto[1]	55	1			T16	2		T21	3		T119	2
all_values[12]	auto[0]	auto[0]	auto[0]	33	1			T21	1		T119	1		T275	2
all_values[12]	auto[0]	auto[0]	auto[1]	81	1			T119	6		T273	3		T272	2
all_values[12]	auto[0]	auto[1]	auto[0]	19	1			T16	4		T276	1		T281	2
all_values[12]	auto[0]	auto[1]	auto[1]	63	1			T16	2		T21	1		T119	3
all_values[12]	auto[1]	auto[0]	auto[1]	82	1			T21	2		T119	4		T272	1
all_values[12]	auto[1]	auto[1]	auto[1]	71	1			T16	2		T21	3		T119	1
all_values[13]	auto[0]	auto[0]	auto[0]	33	1			T21	1		T119	1		T273	2
all_values[13]	auto[0]	auto[0]	auto[1]	71	1			T16	4		T21	1		T119	7
all_values[13]	auto[0]	auto[1]	auto[0]	17	1			T119	1		T273	2		T277	1
all_values[13]	auto[0]	auto[1]	auto[1]	76	1			T16	1		T21	3		T119	1
all_values[13]	auto[1]	auto[0]	auto[1]	75	1			T16	1		T21	1		T119	4
all_values[13]	auto[1]	auto[1]	auto[1]	77	1			T16	2		T21	1		T119	1
all_values[14]	auto[0]	auto[0]	auto[0]	25	1			T119	1		T277	1		T121	1
all_values[14]	auto[0]	auto[0]	auto[1]	81	1			T16	3		T21	1		T119	6
all_values[14]	auto[0]	auto[1]	auto[0]	30	1			T16	1		T119	1		T273	1
all_values[14]	auto[0]	auto[1]	auto[1]	70	1			T16	1		T21	4		T119	5
all_values[14]	auto[1]	auto[0]	auto[1]	86	1			T16	2		T21	1		T119	1
all_values[14]	auto[1]	auto[1]	auto[1]	57	1			T16	1		T21	1		T119	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal