Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	689076	1			T1	1		T2	2		T3	26
all_values[1]	689076	1			T1	1		T2	2		T3	26
all_values[2]	689076	1			T1	1		T2	2		T3	26
all_values[3]	689076	1			T1	1		T2	2		T3	26
all_values[4]	689076	1			T1	1		T2	2		T3	26
all_values[5]	689076	1			T1	1		T2	2		T3	26
all_values[6]	689076	1			T1	1		T2	2		T3	26
all_values[7]	689076	1			T1	1		T2	2		T3	26
all_values[8]	689076	1			T1	1		T2	2		T3	26
all_values[9]	689076	1			T1	1		T2	2		T3	26
all_values[10]	689076	1			T1	1		T2	2		T3	26
all_values[11]	689076	1			T1	1		T2	2		T3	26
all_values[12]	689076	1			T1	1		T2	2		T3	26
all_values[13]	689076	1			T1	1		T2	2		T3	26
all_values[14]	689076	1			T1	1		T2	2		T3	26

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8551030

1

T1

15

T2

30

T3

342

auto[1]

1785110

1

T3

48

T4

5

T5

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9674864

1

T1

15

T2

30

T3

390

auto[1]

661276

1

T37

130097

T132

84476

T161

62

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	105333	1			T1	1		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	3558	1			T37	446		T132	1300		T133	164
all_values[0]	auto[1]	auto[0]	539584	1			T3	24		T4	2		T5	2
all_values[0]	auto[1]	auto[1]	40601	1			T37	8227		T132	4408		T133	4623
all_values[1]	auto[0]	auto[0]	644579	1			T1	1		T2	2		T3	26
all_values[1]	auto[0]	auto[1]	43978	1			T37	8639		T132	5705		T161	3
all_values[1]	auto[1]	auto[0]	331	1			T270	2		T271	1		T209	63
all_values[1]	auto[1]	auto[1]	188	1			T37	35		T132	1		T161	3
all_values[2]	auto[0]	auto[0]	645299	1			T1	1		T2	2		T3	26
all_values[2]	auto[0]	auto[1]	43447	1			T37	8666		T132	5135		T161	3
all_values[2]	auto[1]	auto[0]	192	1			T46	1		T60	1		T174	1
all_values[2]	auto[1]	auto[1]	138	1			T37	8		T132	2		T161	2
all_values[3]	auto[0]	auto[0]	644908	1			T1	1		T2	2		T3	26
all_values[3]	auto[0]	auto[1]	43994	1			T37	8665		T132	5702		T161	3
all_values[3]	auto[1]	auto[1]	174	1			T37	7		T132	5		T161	3
all_values[4]	auto[0]	auto[0]	644890	1			T1	1		T2	2		T3	26
all_values[4]	auto[0]	auto[1]	44020	1			T37	8665		T132	5705		T161	3
all_values[4]	auto[1]	auto[0]	19	1			T11	1		T13	1		T254	2
all_values[4]	auto[1]	auto[1]	147	1			T37	6		T132	3		T161	2
all_values[5]	auto[0]	auto[0]	644917	1			T1	1		T2	2		T3	26
all_values[5]	auto[0]	auto[1]	43993	1			T37	8663		T132	5707		T133	4786
all_values[5]	auto[1]	auto[1]	166	1			T37	8		T132	1		T133	1
all_values[6]	auto[0]	auto[0]	644931	1			T1	1		T2	2		T3	26
all_values[6]	auto[0]	auto[1]	43998	1			T37	8664		T132	5706		T161	2
all_values[6]	auto[1]	auto[1]	147	1			T37	10		T132	2		T161	3
all_values[7]	auto[0]	auto[0]	615963	1			T1	1		T2	2		T3	26
all_values[7]	auto[0]	auto[1]	42645	1			T37	8359		T132	5339		T133	4503
all_values[7]	auto[1]	auto[0]	28945	1			T5	1		T9	1		T39	1
all_values[7]	auto[1]	auto[1]	1523	1			T37	315		T132	369		T133	281
all_values[8]	auto[0]	auto[0]	644900	1			T1	1		T2	2		T3	26
all_values[8]	auto[0]	auto[1]	44032	1			T37	8670		T132	5705		T161	3
all_values[8]	auto[1]	auto[1]	144	1			T37	4		T132	3		T161	3
all_values[9]	auto[0]	auto[0]	198051	1			T1	1		T2	2		T3	26
all_values[9]	auto[0]	auto[1]	5338	1			T37	1473		T132	1112		T161	3
all_values[9]	auto[1]	auto[0]	446876	1			T4	1		T5	1		T9	1
all_values[9]	auto[1]	auto[1]	38811	1			T37	7201		T132	4596		T161	3
all_values[10]	auto[0]	auto[0]	644913	1			T1	1		T2	2		T3	26
all_values[10]	auto[0]	auto[1]	44025	1			T37	8668		T132	5702		T161	4
all_values[10]	auto[1]	auto[1]	138	1			T37	4		T132	6		T161	1
all_values[11]	auto[0]	auto[0]	2365	1			T1	1		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	247	1			T37	15		T132	32		T161	3
all_values[11]	auto[1]	auto[0]	642544	1			T3	24		T4	2		T5	2
all_values[11]	auto[1]	auto[1]	43920	1			T37	8659		T132	5676		T161	1
all_values[12]	auto[0]	auto[0]	644837	1			T1	1		T2	2		T3	26
all_values[12]	auto[0]	auto[1]	44027	1			T37	8665		T132	5704		T161	3
all_values[12]	auto[1]	auto[0]	66	1			T60	1		T66	1		T67	1
all_values[12]	auto[1]	auto[1]	146	1			T37	9		T132	4		T161	1
all_values[13]	auto[0]	auto[0]	645498	1			T1	1		T2	2		T3	26
all_values[13]	auto[0]	auto[1]	43433	1			T37	8667		T132	5134		T161	5
all_values[13]	auto[1]	auto[1]	145	1			T37	6		T132	4		T133	1
all_values[14]	auto[0]	auto[0]	644923	1			T1	1		T2	2		T3	26
all_values[14]	auto[0]	auto[1]	43988	1			T37	8670		T132	5705		T161	4
all_values[14]	auto[1]	auto[1]	165	1			T37	3		T132	3		T161	1