Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	689076	1			T1	1		T2	2		T3	26
all_pins[1]	689076	1			T1	1		T2	2		T3	26
all_pins[2]	689076	1			T1	1		T2	2		T3	26
all_pins[3]	689076	1			T1	1		T2	2		T3	26
all_pins[4]	689076	1			T1	1		T2	2		T3	26
all_pins[5]	689076	1			T1	1		T2	2		T3	26
all_pins[6]	689076	1			T1	1		T2	2		T3	26
all_pins[7]	689076	1			T1	1		T2	2		T3	26
all_pins[8]	689076	1			T1	1		T2	2		T3	26
all_pins[9]	689076	1			T1	1		T2	2		T3	26
all_pins[10]	689076	1			T1	1		T2	2		T3	26
all_pins[11]	689076	1			T1	1		T2	2		T3	26
all_pins[12]	689076	1			T1	1		T2	2		T3	26
all_pins[13]	689076	1			T1	1		T2	2		T3	26
all_pins[14]	689076	1			T1	1		T2	2		T3	26

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8557864	1			T1	15		T2	30		T3	342
values[0x1]	1778276	1			T3	48		T4	5		T5	6
transitions[0x0=>0x1]	1777583	1			T3	48		T4	5		T5	6
transitions[0x1=>0x0]	1776283	1			T3	47		T4	4		T5	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	112655	1			T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	576421	1			T3	24		T4	2		T5	2
all_pins[0]	transitions[0x0=>0x1]	575980	1			T3	24		T4	2		T5	2
all_pins[0]	transitions[0x1=>0x0]	56	1			T37	2		T280	1		T161	2
all_pins[1]	values[0x0]	688579	1			T1	1		T2	2		T3	26
all_pins[1]	values[0x1]	497	1			T270	2		T271	1		T209	69
all_pins[1]	transitions[0x0=>0x1]	479	1			T270	2		T271	1		T209	69
all_pins[1]	transitions[0x1=>0x0]	101	1			T46	1		T68	1		T281	1
all_pins[2]	values[0x0]	688957	1			T1	1		T2	2		T3	26
all_pins[2]	values[0x1]	119	1			T46	1		T68	1		T281	1
all_pins[2]	transitions[0x0=>0x1]	105	1			T46	1		T68	1		T281	1
all_pins[2]	transitions[0x1=>0x0]	65	1			T37	3		T132	3		T161	1
all_pins[3]	values[0x0]	688997	1			T1	1		T2	2		T3	26
all_pins[3]	values[0x1]	79	1			T37	5		T132	3		T161	1
all_pins[3]	transitions[0x0=>0x1]	65	1			T37	4		T132	3		T161	1
all_pins[3]	transitions[0x1=>0x0]	69	1			T11	1		T13	1		T254	2
all_pins[4]	values[0x0]	688993	1			T1	1		T2	2		T3	26
all_pins[4]	values[0x1]	83	1			T11	1		T13	1		T254	2
all_pins[4]	transitions[0x0=>0x1]	70	1			T11	1		T13	1		T254	2
all_pins[4]	transitions[0x1=>0x0]	71	1			T37	5		T229	3		T282	1
all_pins[5]	values[0x0]	688992	1			T1	1		T2	2		T3	26
all_pins[5]	values[0x1]	84	1			T37	6		T229	3		T282	1
all_pins[5]	transitions[0x0=>0x1]	73	1			T37	6		T229	3		T283	1
all_pins[5]	transitions[0x1=>0x0]	54	1			T37	2		T132	2		T161	1
all_pins[6]	values[0x0]	689011	1			T1	1		T2	2		T3	26
all_pins[6]	values[0x1]	65	1			T37	2		T132	2		T161	1
all_pins[6]	transitions[0x0=>0x1]	48	1			T37	1		T161	1		T133	2
all_pins[6]	transitions[0x1=>0x0]	32762	1			T5	1		T9	1		T39	1
all_pins[7]	values[0x0]	656297	1			T1	1		T2	2		T3	26
all_pins[7]	values[0x1]	32779	1			T5	1		T9	1		T39	1
all_pins[7]	transitions[0x0=>0x1]	32757	1			T5	1		T9	1		T39	1
all_pins[7]	transitions[0x1=>0x0]	53	1			T37	1		T133	2		T284	1
all_pins[8]	values[0x0]	689001	1			T1	1		T2	2		T3	26
all_pins[8]	values[0x1]	75	1			T37	2		T133	3		T229	1
all_pins[8]	transitions[0x0=>0x1]	58	1			T37	2		T133	3		T229	1
all_pins[8]	transitions[0x1=>0x0]	485604	1			T4	1		T5	1		T9	1
all_pins[9]	values[0x0]	203455	1			T1	1		T2	2		T3	26
all_pins[9]	values[0x1]	485621	1			T4	1		T5	1		T9	1
all_pins[9]	transitions[0x0=>0x1]	485611	1			T4	1		T5	1		T9	1
all_pins[9]	transitions[0x1=>0x0]	52	1			T37	2		T132	4		T161	1
all_pins[10]	values[0x0]	689014	1			T1	1		T2	2		T3	26
all_pins[10]	values[0x1]	62	1			T37	3		T132	4		T161	1
all_pins[10]	transitions[0x0=>0x1]	49	1			T37	3		T132	3		T161	1
all_pins[10]	transitions[0x1=>0x0]	682078	1			T3	24		T4	2		T5	2
all_pins[11]	values[0x0]	6985	1			T1	1		T2	2		T3	2
all_pins[11]	values[0x1]	682091	1			T3	24		T4	2		T5	2
all_pins[11]	transitions[0x0=>0x1]	682051	1			T3	24		T4	2		T5	2
all_pins[11]	transitions[0x1=>0x0]	105	1			T60	1		T66	1		T67	1
all_pins[12]	values[0x0]	688931	1			T1	1		T2	2		T3	26
all_pins[12]	values[0x1]	145	1			T60	1		T68	1		T66	1
all_pins[12]	transitions[0x0=>0x1]	134	1			T60	1		T68	1		T66	1
all_pins[12]	transitions[0x1=>0x0]	64	1			T37	2		T132	2		T284	1
all_pins[13]	values[0x0]	689001	1			T1	1		T2	2		T3	26
all_pins[13]	values[0x1]	75	1			T37	2		T132	2		T284	1
all_pins[13]	transitions[0x0=>0x1]	58	1			T37	2		T132	2		T284	1
all_pins[13]	transitions[0x1=>0x0]	63	1			T132	2		T161	1		T133	2
all_pins[14]	values[0x0]	688996	1			T1	1		T2	2		T3	26
all_pins[14]	values[0x1]	80	1			T132	2		T161	1		T133	2
all_pins[14]	transitions[0x0=>0x1]	45	1			T132	1		T161	1		T283	1
all_pins[14]	transitions[0x1=>0x0]	575086	1			T3	23		T4	1		T5	1