Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	331	1			T37	14		T132	8		T161	4
all_values[1]	331	1			T37	14		T132	8		T161	4
all_values[2]	331	1			T37	14		T132	8		T161	4
all_values[3]	331	1			T37	14		T132	8		T161	4
all_values[4]	331	1			T37	14		T132	8		T161	4
all_values[5]	331	1			T37	14		T132	8		T161	4
all_values[6]	331	1			T37	14		T132	8		T161	4
all_values[7]	331	1			T37	14		T132	8		T161	4
all_values[8]	331	1			T37	14		T132	8		T161	4
all_values[9]	331	1			T37	14		T132	8		T161	4
all_values[10]	331	1			T37	14		T132	8		T161	4
all_values[11]	331	1			T37	14		T132	8		T161	4
all_values[12]	331	1			T37	14		T132	8		T161	4
all_values[13]	331	1			T37	14		T132	8		T161	4
all_values[14]	331	1			T37	14		T132	8		T161	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2692

1

T37

112

T132

62

T161

42

auto[1]

2273

1

T37

98

T132

58

T161

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

813

1

T37

13

T132

12

T161

22

auto[1]

4152

1

T37

197

T132

108

T161

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2859

1

T37

110

T132

70

T161

39

auto[1]

2106

1

T37

100

T132

50

T161

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1			T161	2		T282	2		T283	1
all_values[0]	auto[0]	auto[0]	auto[1]	56	1			T37	1		T132	3		T133	1
all_values[0]	auto[0]	auto[1]	auto[0]	23	1			T37	1		T161	2		T283	2
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T37	4		T132	1		T133	2
all_values[0]	auto[1]	auto[0]	auto[1]	66	1			T37	5		T132	2		T229	1
all_values[0]	auto[1]	auto[1]	auto[1]	69	1			T37	3		T132	2		T133	4
all_values[1]	auto[0]	auto[0]	auto[0]	34	1			T283	2		T285	2		T134	1
all_values[1]	auto[0]	auto[0]	auto[1]	71	1			T37	4		T132	1		T161	1
all_values[1]	auto[0]	auto[1]	auto[0]	17	1			T132	2		T284	1		T134	1
all_values[1]	auto[0]	auto[1]	auto[1]	62	1			T37	2		T132	4		T133	1
all_values[1]	auto[1]	auto[0]	auto[1]	83	1			T37	7		T132	1		T161	2
all_values[1]	auto[1]	auto[1]	auto[1]	64	1			T37	1		T161	1		T133	3
all_values[2]	auto[0]	auto[0]	auto[0]	32	1			T132	3		T161	1		T283	1
all_values[2]	auto[0]	auto[0]	auto[1]	62	1			T132	1		T161	1		T133	1
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T132	2		T284	1		T286	1
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T37	6		T133	3		T284	1
all_values[2]	auto[1]	auto[0]	auto[1]	79	1			T37	4		T132	2		T161	2
all_values[2]	auto[1]	auto[1]	auto[1]	59	1			T37	4		T133	2		T284	4
all_values[3]	auto[0]	auto[0]	auto[0]	31	1			T284	1		T287	1		T134	1
all_values[3]	auto[0]	auto[0]	auto[1]	77	1			T37	4		T132	1		T161	1
all_values[3]	auto[0]	auto[1]	auto[0]	19	1			T37	2		T132	1		T284	2
all_values[3]	auto[0]	auto[1]	auto[1]	61	1			T37	2		T132	1		T161	1
all_values[3]	auto[1]	auto[0]	auto[1]	74	1			T37	1		T132	1		T161	2
all_values[3]	auto[1]	auto[1]	auto[1]	69	1			T37	5		T132	4		T133	1
all_values[4]	auto[0]	auto[0]	auto[0]	29	1			T37	2		T161	1		T282	2
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T37	4		T132	1		T161	1
all_values[4]	auto[0]	auto[1]	auto[0]	20	1			T37	1		T282	2		T288	1
all_values[4]	auto[0]	auto[1]	auto[1]	61	1			T37	1		T132	4		T133	3
all_values[4]	auto[1]	auto[0]	auto[1]	90	1			T37	3		T132	2		T161	2
all_values[4]	auto[1]	auto[1]	auto[1]	57	1			T37	3		T132	1		T133	2
all_values[5]	auto[0]	auto[0]	auto[0]	37	1			T37	1		T161	1		T284	1
all_values[5]	auto[0]	auto[0]	auto[1]	67	1			T37	2		T132	3		T284	2
all_values[5]	auto[0]	auto[1]	auto[0]	19	1			T37	2		T161	3		T284	1
all_values[5]	auto[0]	auto[1]	auto[1]	67	1			T37	5		T132	3		T133	3
all_values[5]	auto[1]	auto[0]	auto[1]	75	1			T37	2		T132	2		T133	2
all_values[5]	auto[1]	auto[1]	auto[1]	66	1			T37	2		T133	2		T229	2
all_values[6]	auto[0]	auto[0]	auto[0]	35	1			T161	1		T229	1		T284	3
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T37	5		T132	2		T161	1
all_values[6]	auto[0]	auto[1]	auto[0]	26	1			T133	5		T229	3		T284	1
all_values[6]	auto[0]	auto[1]	auto[1]	61	1			T37	1		T132	4		T133	1
all_values[6]	auto[1]	auto[0]	auto[1]	89	1			T37	7		T132	1		T161	2
all_values[6]	auto[1]	auto[1]	auto[1]	41	1			T37	1		T132	1		T282	1
all_values[7]	auto[0]	auto[0]	auto[0]	30	1			T161	3		T133	2		T282	1
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T37	5		T132	2		T133	1
all_values[7]	auto[0]	auto[1]	auto[0]	18	1			T161	1		T133	1		T289	3
all_values[7]	auto[0]	auto[1]	auto[1]	63	1			T37	3		T132	2		T229	2
all_values[7]	auto[1]	auto[0]	auto[1]	83	1			T37	3		T132	3		T133	1
all_values[7]	auto[1]	auto[1]	auto[1]	60	1			T37	3		T132	1		T133	2
all_values[8]	auto[0]	auto[0]	auto[0]	22	1			T229	1		T282	1		T287	1
all_values[8]	auto[0]	auto[0]	auto[1]	67	1			T37	6		T132	5		T161	2
all_values[8]	auto[0]	auto[1]	auto[0]	18	1			T133	2		T284	1		T134	3
all_values[8]	auto[0]	auto[1]	auto[1]	73	1			T37	1		T133	3		T284	2
all_values[8]	auto[1]	auto[0]	auto[1]	85	1			T37	6		T132	3		T161	2
all_values[8]	auto[1]	auto[1]	auto[1]	66	1			T37	1		T133	2		T229	2
all_values[9]	auto[0]	auto[0]	auto[0]	36	1			T229	1		T282	2		T287	1
all_values[9]	auto[0]	auto[0]	auto[1]	74	1			T37	4		T132	5		T133	1
all_values[9]	auto[0]	auto[1]	auto[0]	31	1			T133	4		T229	1		T285	2
all_values[9]	auto[0]	auto[1]	auto[1]	59	1			T37	5		T161	2		T229	1
all_values[9]	auto[1]	auto[0]	auto[1]	76	1			T37	2		T132	3		T161	1
all_values[9]	auto[1]	auto[1]	auto[1]	55	1			T37	3		T161	1		T133	1
all_values[10]	auto[0]	auto[0]	auto[0]	33	1			T37	2		T161	1		T283	1
all_values[10]	auto[0]	auto[0]	auto[1]	64	1			T37	1		T132	1		T161	2
all_values[10]	auto[0]	auto[1]	auto[0]	20	1			T133	1		T283	2		T285	2
all_values[10]	auto[0]	auto[1]	auto[1]	76	1			T37	7		T132	1		T133	4
all_values[10]	auto[1]	auto[0]	auto[1]	74	1			T37	2		T133	1		T229	3
all_values[10]	auto[1]	auto[1]	auto[1]	64	1			T37	2		T132	6		T161	1
all_values[11]	auto[0]	auto[0]	auto[0]	32	1			T161	2		T229	2		T134	1
all_values[11]	auto[0]	auto[0]	auto[1]	64	1			T37	2		T132	2		T229	1
all_values[11]	auto[0]	auto[1]	auto[0]	17	1			T284	2		T290	2		T291	1
all_values[11]	auto[0]	auto[1]	auto[1]	69	1			T37	1		T132	2		T161	1
all_values[11]	auto[1]	auto[0]	auto[1]	76	1			T37	6		T132	3		T133	1
all_values[11]	auto[1]	auto[1]	auto[1]	73	1			T37	5		T132	1		T161	1
all_values[12]	auto[0]	auto[0]	auto[0]	27	1			T161	1		T287	1		T292	1
all_values[12]	auto[0]	auto[0]	auto[1]	69	1			T37	1		T132	1		T161	1
all_values[12]	auto[0]	auto[1]	auto[0]	18	1			T161	1		T284	1		T285	1
all_values[12]	auto[0]	auto[1]	auto[1]	71	1			T37	4		T132	3		T133	3
all_values[12]	auto[1]	auto[0]	auto[1]	74	1			T37	5		T132	2		T161	1
all_values[12]	auto[1]	auto[1]	auto[1]	72	1			T37	4		T132	2		T133	1
all_values[13]	auto[0]	auto[0]	auto[0]	41	1			T37	1		T132	2		T161	1
all_values[13]	auto[0]	auto[0]	auto[1]	64	1			T37	1		T132	1		T284	3
all_values[13]	auto[0]	auto[1]	auto[0]	22	1			T132	2		T229	2		T134	2
all_values[13]	auto[0]	auto[1]	auto[1]	72	1			T37	7		T161	2		T133	2
all_values[13]	auto[1]	auto[0]	auto[1]	69	1			T37	3		T161	1		T133	4
all_values[13]	auto[1]	auto[1]	auto[1]	63	1			T37	2		T132	3		T133	1
all_values[14]	auto[0]	auto[0]	auto[0]	43	1			T37	1		T161	1		T284	2
all_values[14]	auto[0]	auto[0]	auto[1]	58	1			T37	5		T132	1		T161	1
all_values[14]	auto[0]	auto[1]	auto[0]	19	1			T284	2		T283	1		T134	1
all_values[14]	auto[0]	auto[1]	auto[1]	76	1			T37	3		T132	3		T133	4
all_values[14]	auto[1]	auto[0]	auto[1]	81	1			T37	4		T132	2		T161	1
all_values[14]	auto[1]	auto[1]	auto[1]	54	1			T37	1		T132	2		T161	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal