Go
back
120 always_comb begin : counter_functions
121 1/1 tcount_d = tcount_q;
Tests: T1 T2 T3
122 1/1 if (load_tcount) begin
Tests: T1 T2 T3
123 1/1 unique case (tcount_sel)
Tests: T2 T3 T4
124 1/1 tSetupStart : tcount_d = 13'(t_r_i) + 13'(tsu_sta_i);
Tests: T3 T4 T5
125 1/1 tHoldStart : tcount_d = 13'(t_f_i) + 13'(thd_sta_i);
Tests: T3 T4 T5
126 1/1 tClockStart : tcount_d = 16'(thd_dat_i);
Tests: T3 T4 T5
127 1/1 tClockLow : tcount_d = 13'(tlow_i) - 13'(thd_dat_i);
Tests: T2 T3 T4
128 1/1 tClockPulse : tcount_d = 13'(t_r_i) + 13'(thigh_i);
Tests: T3 T4 T5
129 1/1 tClockHigh : tcount_d = 16'(thigh_i);
Tests: T3 T4 T5
130 1/1 tHoldBit : tcount_d = 13'(t_f_i) + 13'(thd_dat_i);
Tests: T3 T4 T5
131 1/1 tClockStop : tcount_d = 13'(t_f_i) + 13'(tlow_i) - 13'(thd_dat_i);
Tests: T3 T4 T5
132 1/1 tSetupStop : tcount_d = 13'(t_r_i) + 13'(tsu_sto_i);
Tests: T3 T4 T5
133 1/1 tNoDelay : tcount_d = 16'h0001;
Tests: T3 T4 T5
134 default : tcount_d = 16'h0001;
135 endcase
136 1/1 end else if (
Tests: T1 T2 T3
137 host_enable_i ||
138 // If we disable Host-Mode mid-txn, keep counting until the end of
139 // byte, at which point we create a STOP condition then return to Idle.
140 (!host_idle_o && !host_enable_i)) begin
141 1/1 tcount_d = tcount_q - 1'b1;
Tests: T1 T2 T3
142 end
MISSING_ELSE
143 end
144
145 always_ff @ (posedge clk_i or negedge rst_ni) begin : clk_counter
146 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
147 1/1 tcount_q <= '1;
Tests: T1 T2 T3
148 end else begin
149 1/1 tcount_q <= tcount_d;
Tests: T1 T2 T3
150 end
151 end
152
153 // Clock stretching/idle detection when i2c_ctrl.
154 // When in host mode, this is a stretch count for how long an external target
155 // has stretched the clock.
156 // When in target mode, this is an idle count for how long an external host
157 // has kept the clock idle after a START indication.
158 always_ff @ (posedge clk_i or negedge rst_ni) begin : clk_stretch
159 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
160 1/1 stretch_idle_cnt <= '0;
Tests: T1 T2 T3
161 1/1 end else if (stretch_en && !scl_i) begin
Tests: T1 T2 T3
162 // HOST-mode count of clock stretching
163 1/1 stretch_idle_cnt <= stretch_idle_cnt + 1'b1;
Tests: T3 T4 T5
164 end else begin
165 1/1 stretch_idle_cnt <= '0;
Tests: T1 T2 T3
166 end
167 end
168
169 // The TARGET can stretch the clock during any time that the host drives SCL to 0.
170 // However, we (the HOST) cannot know it is being stretched until we release SCL,
171 // usually trying to create the next clock pulse.
172 // There is a minimum 3-cycle round trip (1-cycle output flop, 2-cycle input synchronizer),
173 // between releasing the clock and observing the effect of releasing the clock on
174 // the inputs. However, this is really '1 + t_r + 2' as the bus also needs to slew to '1
175 // before can observe it. Even if the TARGET is not stretching the clock, we cannot
176 // confirm it until at-least this amount of time has elapsed.
177 //
178 // 'stretch_predict_cnt_expired' becomes active once we have observed (4 + t_r) cycles of
179 // delay, and if !scl_i at this point we know that the TARGET is stretching the clock.
180 // > This implementation requires 'thigh >= 4' to guarantee we don't miss stretching.
181 logic [30:0] stretch_cnt_threshold;
182 1/1 assign stretch_cnt_threshold = 31'd2 + 31'(t_r_i);
Tests: T1 T2 T3
183
184 logic stretch_predict_cnt_expired;
185 always_ff @ (posedge clk_i or negedge rst_ni) begin
186 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
187 1/1 stretch_predict_cnt_expired <= 1'b0;
Tests: T1 T2 T3
188 end else begin
189 1/1 if (stretch_idle_cnt == stretch_cnt_threshold) begin
Tests: T1 T2 T3
190 1/1 stretch_predict_cnt_expired <= 1'b1;
Tests: T3 T4 T5
191 1/1 end else if (!stretch_en) begin
Tests: T1 T2 T3
192 1/1 stretch_predict_cnt_expired <= 1'b0;
Tests: T1 T2 T3
193 end
MISSING_ELSE
194 end
195 end
196
197 // While the FSM is halted due to an unhandled 'nak' irq in Host-Mode, this counter can
198 // be used to trigger a timeout which disables Host-Mode and creates a STOP condition to
199 // end the transaction.
200 logic unhandled_nak_cnt_expired;
201 always_ff @ (posedge clk_i or negedge rst_ni) begin : unhandled_nak_cnt_b
202 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
203 1/1 unhandled_nak_cnt <= '0;
Tests: T1 T2 T3
204 1/1 unhandled_nak_cnt_expired <= 1'b0;
Tests: T1 T2 T3
205 1/1 end else if (incr_nak_cnt) begin
Tests: T1 T2 T3
206 // Increment the counter while the FSM is halted in Idle.
207 1/1 unhandled_nak_cnt <= unhandled_nak_cnt + 1'b1;
Tests: T11 T12 T13
208 1/1 if (unhandled_nak_cnt > host_nack_handler_timeout_i) begin
Tests: T11 T12 T13
209 0/1 ==> unhandled_nak_cnt_expired <= 1'b1;
210 end
MISSING_ELSE
211 end else begin
212 1/1 unhandled_nak_cnt <= '0;
Tests: T1 T2 T3
213 1/1 unhandled_nak_cnt_expired <= 1'b0;
Tests: T1 T2 T3
214 end
215 end
216
217 1/1 assign event_unhandled_nak_timeout_o = unhandled_nak_cnt_expired;
Tests: T1 T2 T3
218
219 // Bit index implementation
220 always_ff @ (posedge clk_i or negedge rst_ni) begin : bit_counter
221 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
222 1/1 bit_index <= 3'd7;
Tests: T1 T2 T3
223 1/1 end else if (bit_clr) begin
Tests: T1 T2 T3
224 1/1 bit_index <= 3'd7;
Tests: T3 T4 T5
225 1/1 end else if (bit_decr) begin
Tests: T1 T2 T3
226 1/1 bit_index <= bit_index - 1'b1;
Tests: T3 T4 T5
227 end else begin
228 1/1 bit_index <= bit_index;
Tests: T1 T2 T3
229 end
230 end
231
232 // Deserializer for a byte read from the bus
233 always_ff @ (posedge clk_i or negedge rst_ni) begin : read_register
234 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
235 1/1 read_byte <= 8'h00;
Tests: T1 T2 T3
236 1/1 end else if (read_byte_clr) begin
Tests: T1 T2 T3
237 1/1 read_byte <= 8'h00;
Tests: T3 T4 T9
238 1/1 end else if (shift_data_en) begin
Tests: T1 T2 T3
239 1/1 read_byte[7:0] <= {read_byte[6:0], sda_i}; // MSB goes in first
Tests: T3 T4 T9
240 end
MISSING_ELSE
241 end
242
243 // Number of bytes to read
244 always_comb begin : byte_number
245 2/2 if (!fmt_flag_read_bytes_i) byte_num = 9'd0;
Tests: T1 T2 T3 | T1 T2 T3
246 2/2 else if (fmt_byte_i == '0) byte_num = 9'd256;
Tests: T3 T4 T9 | T14 T15 T16
247 1/1 else byte_num = 9'(fmt_byte_i);
Tests: T3 T4 T9
248 end
249
250 // Byte index implementation
251 always_ff @ (posedge clk_i or negedge rst_ni) begin : byte_counter
252 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
253 1/1 byte_index <= '0;
Tests: T1 T2 T3
254 1/1 end else if (byte_clr) begin
Tests: T1 T2 T3
255 1/1 byte_index <= byte_num;
Tests: T3 T4 T9
256 1/1 end else if (byte_decr) begin
Tests: T1 T2 T3
257 1/1 byte_index <= byte_index - 1'b1;
Tests: T3 T4 T9
258 end else begin
259 1/1 byte_index <= byte_index;
Tests: T1 T2 T3
260 end
261 end
262
263 // SDA and SCL at the previous clock edge
264 always_ff @ (posedge clk_i or negedge rst_ni) begin : bus_prev
265 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
266 1/1 scl_i_q <= 1'b1;
Tests: T1 T2 T3
267 1/1 sda_i_q <= 1'b1;
Tests: T1 T2 T3
268 end else begin
269 1/1 scl_i_q <= scl_i;
Tests: T1 T2 T3
270 1/1 sda_i_q <= sda_i;
Tests: T1 T2 T3
271 end
272 end
273
274 // SCL going low early is just clock synchronization. SCL switching so fast that the controller
275 // can't even sense its outputs is cause for a bus error.
276 1/1 assign event_arbitration_lost_o = event_sda_unstable_o || sda_interference_i ||
Tests: T1 T2 T3
277 ctrl_symbol_failed;
278
279 // Registers whether a transaction start has been observed.
280 // A transaction start does not include a "restart", but rather
281 // the first start after enabling i2c, or a start observed after a
282 // stop.
283 always_ff @(posedge clk_i or negedge rst_ni) begin
284 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
285 1/1 trans_started <= '0;
Tests: T1 T2 T3
286 1/1 end else if (trans_started && (!host_enable_i || event_arbitration_lost_o)) begin
Tests: T1 T2 T3
287 1/1 trans_started <= '0;
Tests: T6 T17 T18
288 1/1 end else if (log_start) begin
Tests: T1 T2 T3
289 1/1 trans_started <= 1'b1;
Tests: T3 T4 T5
290 1/1 end else if (log_stop) begin
Tests: T1 T2 T3
291 1/1 trans_started <= 1'b0;
Tests: T3 T4 T5
292 end
MISSING_ELSE
293 end
294
295 always_ff @(posedge clk_i or negedge rst_ni) begin
296 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
297 1/1 pend_restart <= '0;
Tests: T1 T2 T3
298 1/1 end else if (pend_restart && !host_enable_i) begin
Tests: T1 T2 T3
299 0/1 ==> pend_restart <= '0;
300 1/1 end else if (req_restart) begin
Tests: T1 T2 T3
301 1/1 pend_restart <= 1'b1;
Tests: T11 T12 T13
302 1/1 end else if (log_start) begin
Tests: T1 T2 T3
303 1/1 pend_restart <= '0;
Tests: T3 T4 T5
304 end
MISSING_ELSE
305 end
306
307 always_ff @(posedge clk_i or negedge rst_ni) begin
308 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
309 1/1 auto_stop_q <= 1'b0;
Tests: T1 T2 T3
310 end else begin
311 1/1 auto_stop_q <= auto_stop_d;
Tests: T1 T2 T3
312 end
313 end
314
315 // State definitions
316 typedef enum logic [4:0] {
317 Idle,
318 ///////////////////////
319 // Host function states
320 ///////////////////////
321 Active, PopFmtFifo,
322 // Host function starts a transaction
323 SetupStart, HoldStart, ClockStart,
324 // Host function stops a transaction
325 SetupStop, HoldStop, ClockStop,
326 // Host function transmits a bit to the external target
327 ClockLow, ClockPulse, HoldBit,
328 // Host function recevies an ack from the external target
329 ClockLowAck, ClockPulseAck, HoldDevAck,
330 // Host function reads a bit from the external target
331 ReadClockLow, ReadClockPulse, ReadHoldBit,
332 // Host function transmits an ack to the external target
333 HostClockLowAck, HostClockPulseAck, HostHoldBitAck
334 } state_e;
335
336 state_e state_q, state_d;
337
338
339 // Increment the NACK timeout count if the controller is halted in Idle and
340 // the timeout hasn't yet occurred.
341 1/1 assign incr_nak_cnt = unhandled_unexp_nak_i && host_enable_i && (state_q == Idle) &&
Tests: T1 T2 T3
342 host_nack_handler_timeout_en_i && !unhandled_nak_timeout_i;
343
344 // Outputs for each state
345 always_comb begin : state_outputs
346 1/1 host_idle_o = 1'b1;
Tests: T1 T2 T3
347 1/1 sda_d = 1'b1;
Tests: T1 T2 T3
348 1/1 scl_d = 1'b1;
Tests: T1 T2 T3
349 1/1 transmitting_o = 1'b0;
Tests: T1 T2 T3
350 1/1 log_start = 1'b0;
Tests: T1 T2 T3
351 1/1 log_stop = 1'b0;
Tests: T1 T2 T3
352 1/1 fmt_fifo_rready_o = 1'b0;
Tests: T1 T2 T3
353 1/1 rx_fifo_wvalid_o = 1'b0;
Tests: T1 T2 T3
354 1/1 rx_fifo_wdata_o = RX_FIFO_WIDTH'(0);
Tests: T1 T2 T3
355 1/1 event_nak_o = 1'b0;
Tests: T1 T2 T3
356 1/1 event_scl_interference_o = 1'b0;
Tests: T1 T2 T3
357 1/1 ctrl_symbol_failed = 1'b0;
Tests: T1 T2 T3
358 1/1 event_sda_unstable_o = 1'b0;
Tests: T1 T2 T3
359 1/1 event_cmd_complete_o = 1'b0;
Tests: T1 T2 T3
360 1/1 stretch_en = 1'b0;
Tests: T1 T2 T3
361 1/1 unique case (state_q)
Tests: T1 T2 T3
362 // Idle: initial state, SDA is released (high), SCL is released if the
363 // bus is idle. Otherwise, if no STOP condition has been sent yet,
364 // continue pulling SCL low in host mode.
365 Idle : begin
366 1/1 sda_d = 1'b1;
Tests: T1 T2 T3
367 1/1 if (trans_started) begin
Tests: T1 T2 T3
368 1/1 host_idle_o = 1'b0;
Tests: T11 T12 T13
369 1/1 scl_d = 1'b0;
Tests: T11 T12 T13
370 end else begin
371 1/1 host_idle_o = 1'b1;
Tests: T1 T2 T3
372 1/1 scl_d = 1'b1;
Tests: T1 T2 T3
373 end
374 end
375
376 ///////////////
377 // HOST MODE //
378 ///////////////
379
380 // SetupStart: SDA and SCL are released
381 SetupStart : begin
382 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
383 1/1 sda_d = 1'b1;
Tests: T3 T4 T5
384 1/1 scl_d = 1'b1;
Tests: T3 T4 T5
385 1/1 transmitting_o = 1'b1;
Tests: T3 T4 T5
386 // If this is a restart, SCL was last low, and a target could be stretching the clock.
387 1/1 stretch_en = trans_started;
Tests: T3 T4 T5
388 1/1 if (trans_started && !scl_i && scl_i_q) begin
Tests: T3 T4 T5
389 // If this is a repeated Start, an early clock prevents issuing the symbol. If it's not
390 // a repeated start, the FSM will just go back to Idle and wait for the bus to go free
391 // again.
392 0/1 ==> ctrl_symbol_failed = 1'b1;
393 1/1 end else if (tcount_q == 20'd1) begin
Tests: T3 T4 T5
394 1/1 log_start = 1'b1;
Tests: T3 T4 T5
395 1/1 event_cmd_complete_o = pend_restart;
Tests: T3 T4 T5
396 end
MISSING_ELSE
397 end
398 // HoldStart: SDA is pulled low, SCL is released
399 HoldStart : begin
400 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
401 1/1 sda_d = 1'b0;
Tests: T3 T4 T5
402 1/1 scl_d = 1'b1;
Tests: T3 T4 T5
403 1/1 transmitting_o = 1'b1;
Tests: T3 T4 T5
404 1/2 ==> if (scl_i_q && !scl_i) event_scl_interference_o = 1'b1;
Tests: T3 T4 T5
MISSING_ELSE
405 end
406 // ClockStart: SCL is pulled low, SDA stays low
407 ClockStart : begin
408 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
409 1/1 sda_d = 1'b0;
Tests: T3 T4 T5
410 1/1 scl_d = 1'b0;
Tests: T3 T4 T5
411 1/1 transmitting_o = 1'b1;
Tests: T3 T4 T5
412 end
413 ClockLow : begin
414 1/1 host_idle_o = 1'b0;
Tests: T2 T3 T4
415 1/1 if (pend_restart) begin
Tests: T2 T3 T4
416 1/1 sda_d = 1'b1;
Tests: T11 T12 T13
417 end else begin
418 1/1 sda_d = fmt_byte_i[bit_index];
Tests: T2 T3 T4
419 end
420 1/1 scl_d = 1'b0;
Tests: T2 T3 T4
421 1/1 transmitting_o = 1'b1;
Tests: T2 T3 T4
422 end
423 // ClockPulse: SCL is released, SDA keeps the indexed bit value
424 ClockPulse : begin
425 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
426 1/1 sda_d = fmt_byte_i[bit_index];
Tests: T3 T4 T5
427 1/1 scl_d = 1'b1;
Tests: T3 T4 T5
428 1/1 transmitting_o = 1'b1;
Tests: T3 T4 T5
429 1/1 stretch_en = 1'b1;
Tests: T3 T4 T5
430 1/2 ==> if (scl_i_q && !scl_i) event_scl_interference_o = 1'b1;
Tests: T3 T4 T5
MISSING_ELSE
431 1/1 if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
Tests: T3 T4 T5
432 // Unexpected Stop / Start
433 1/1 event_sda_unstable_o = 1'b1;
Tests: T6 T18 T19
434 end
MISSING_ELSE
435 end
436 // HoldBit: SCL is pulled low
437 HoldBit : begin
438 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
439 1/1 sda_d = fmt_byte_i[bit_index];
Tests: T3 T4 T5
440 1/1 scl_d = 1'b0;
Tests: T3 T4 T5
441 1/1 transmitting_o = 1'b1;
Tests: T3 T4 T5
442 end
443 // ClockLowAck: SCL pulled low, SDA is released
444 ClockLowAck : begin
445 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
446 1/1 sda_d = 1'b1;
Tests: T3 T4 T5
447 1/1 scl_d = 1'b0;
Tests: T3 T4 T5
448 end
449 // ClockPulseAck: SCL is released
450 ClockPulseAck : begin
451 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
452 1/1 sda_d = 1'b1;
Tests: T3 T4 T5
453 1/1 scl_d = 1'b1;
Tests: T3 T4 T5
454 2/2 if (!scl_i_q && scl_i && sda_i && !fmt_flag_nak_ok_i) event_nak_o = 1'b1;
Tests: T3 T4 T5 | T11 T20 T12
MISSING_ELSE
455 1/1 stretch_en = 1'b1;
Tests: T3 T4 T5
456 2/2 if (scl_i_q && !scl_i) event_scl_interference_o = 1'b1;
Tests: T3 T4 T5 | T6 T18 T20
MISSING_ELSE
457 1/1 if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
Tests: T3 T4 T5
458 // Unexpected Stop / Start
459 1/1 event_sda_unstable_o = 1'b1;
Tests: T6 T18 T20
460 end
MISSING_ELSE
461 end
462 // HoldDevAck: SCL is pulled low
463 HoldDevAck : begin
464 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
465 1/1 sda_d = 1'b1;
Tests: T3 T4 T5
466 1/1 scl_d = 1'b0;
Tests: T3 T4 T5
467 end
468 // ReadClockLow: SCL is pulled low, SDA is released
469 ReadClockLow : begin
470 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T9
471 1/1 sda_d = 1'b1;
Tests: T3 T4 T9
472 1/1 scl_d = 1'b0;
Tests: T3 T4 T9
473 end
474 // ReadClockPulse: SCL is released, the indexed bit value is read off SDA
475 ReadClockPulse : begin
476 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T9
477 1/1 scl_d = 1'b1;
Tests: T3 T4 T9
478 1/1 stretch_en = 1'b1;
Tests: T3 T4 T9
479 1/2 ==> if (scl_i_q && !scl_i) event_scl_interference_o = 1'b1;
Tests: T3 T4 T9
MISSING_ELSE
480 1/1 if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
Tests: T3 T4 T9
481 // Unexpected Stop / Start
482 0/1 ==> event_sda_unstable_o = 1'b1;
483 end
MISSING_ELSE
484 end
485 // ReadHoldBit: SCL is pulled low
486 ReadHoldBit : begin
487 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T9
488 1/1 scl_d = 1'b0;
Tests: T3 T4 T9
489 1/1 if (bit_index == '0 && tcount_q == 20'd1) begin
Tests: T3 T4 T9
490 1/1 rx_fifo_wvalid_o = 1'b1; // assert that rx_fifo has valid data
Tests: T3 T4 T9
491 1/1 rx_fifo_wdata_o = read_byte; // transfer read data to rx_fifo
Tests: T3 T4 T9
492 end
MISSING_ELSE
493 end
494 // HostClockLowAck: SCL pulled low, SDA is conditional
495 HostClockLowAck : begin
496 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T9
497 1/1 scl_d = 1'b0;
Tests: T3 T4 T9
498 1/1 transmitting_o = 1'b1;
Tests: T3 T4 T9
499
500 // If it is the last byte of a read, send a NAK before the stop.
501 // Otherwise send the ack.
502 2/2 if (fmt_flag_read_continue_i) sda_d = 1'b0;
Tests: T3 T4 T9 | T18 T21 T11
503 2/2 else if (byte_index == 9'd1) sda_d = 1'b1;
Tests: T3 T4 T9 | T3 T4 T9
504 1/1 else sda_d = 1'b0;
Tests: T3 T4 T9
505 end
506 // HostClockPulseAck: SCL is released
507 HostClockPulseAck : begin
508 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T9
509 2/2 if (fmt_flag_read_continue_i) sda_d = 1'b0;
Tests: T3 T4 T9 | T18 T21 T11
510 2/2 else if (byte_index == 9'd1) sda_d = 1'b1;
Tests: T3 T4 T9 | T3 T4 T9
511 1/1 else sda_d = 1'b0;
Tests: T3 T4 T9
512 1/1 scl_d = 1'b1;
Tests: T3 T4 T9
513 1/1 transmitting_o = 1'b1;
Tests: T3 T4 T9
514 1/1 stretch_en = 1'b1;
Tests: T3 T4 T9
515 1/2 ==> if (scl_i_q && !scl_i) event_scl_interference_o = 1'b1;
Tests: T3 T4 T9
MISSING_ELSE
516 1/1 if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
Tests: T3 T4 T9
517 // Unexpected Stop / Start
518 0/1 ==> event_sda_unstable_o = 1'b1;
519 end
MISSING_ELSE
520 end
521 // HostHoldBitAck: SCL is pulled low
522 HostHoldBitAck : begin
523 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T9
524 2/2 if (fmt_flag_read_continue_i) sda_d = 1'b0;
Tests: T3 T4 T9 | T18 T21 T11
525 2/2 else if (byte_index == 9'd1) sda_d = 1'b1;
Tests: T3 T4 T9 | T3 T4 T9
526 1/1 else sda_d = 1'b0;
Tests: T3 T4 T9
527 1/1 scl_d = 1'b0;
Tests: T3 T4 T9
528 1/1 transmitting_o = 1'b1;
Tests: T3 T4 T9
529 end
530 // ClockStop: SCL is pulled low, SDA stays low
531 ClockStop : begin
532 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
533 1/1 sda_d = 1'b0;
Tests: T3 T4 T5
534 1/1 scl_d = 1'b0;
Tests: T3 T4 T5
535 1/1 transmitting_o = 1'b1;
Tests: T3 T4 T5
536 end
537 // SetupStop: SDA is pulled low, SCL is released
538 SetupStop : begin
539 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
540 1/1 sda_d = 1'b0;
Tests: T3 T4 T5
541 1/1 scl_d = 1'b1;
Tests: T3 T4 T5
542 1/1 transmitting_o = 1'b1;
Tests: T3 T4 T5
543 1/1 stretch_en = 1'b1;
Tests: T3 T4 T5
544 1/1 if (!scl_i && scl_i_q) begin
Tests: T3 T4 T5
545 // Failed to issue Stop before some other device could pull SCL low.
546 0/1 ==> ctrl_symbol_failed = 1'b1;
547 end
MISSING_ELSE
548 end
549 // HoldStop: SDA and SCL are released
550 HoldStop : begin
551 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
552 1/1 sda_d = 1'b1;
Tests: T3 T4 T5
553 1/1 scl_d = 1'b1;
Tests: T3 T4 T5
554 1/1 event_cmd_complete_o = 1'b1;
Tests: T3 T4 T5
555 1/1 if (!sda_i && !scl_i) begin
Tests: T3 T4 T5
556 // Failed to issue Stop before some other device could pull SCL low.
557 0/1 ==> ctrl_symbol_failed = 1'b1;
558 1/1 end else if (sda_i) begin
Tests: T3 T4 T5
559 1/1 log_stop = 1'b1;
Tests: T3 T4 T5
560 end
MISSING_ELSE
561 end
562 // Active: continue while keeping SCL low
563 Active : begin
564 1/1 host_idle_o = 1'b0;
Tests: T2 T3 T4
565
566 // If this is a transaction start, do not drive scl low
567 // since in the next state we will drive it high to initiate
568 // the start bit.
569 // If this is a restart, continue driving the clock low.
570 1/1 scl_d = fmt_flag_start_before_i && !trans_started;
Tests: T2 T3 T4
571 end
572 // PopFmtFifo: populate fmt_fifo
573 PopFmtFifo : begin
574 1/1 host_idle_o = 1'b0;
Tests: T3 T4 T5
575 2/2 if (fmt_flag_stop_after_i) scl_d = 1'b1;
Tests: T3 T4 T5 | T3 T4 T5
576 1/1 else scl_d = 1'b0;
Tests: T3 T4 T5
577 1/1 fmt_fifo_rready_o = 1'b1;
Tests: T3 T4 T5
578 end
579
580 // default
581 default : begin
582 host_idle_o = 1'b1;
583 sda_d = 1'b1;
584 scl_d = 1'b1;
585 transmitting_o = 1'b0;
586 log_start = 1'b0;
587 log_stop = 1'b0;
588 event_scl_interference_o = 1'b0;
589 ctrl_symbol_failed = 1'b0;
590 fmt_fifo_rready_o = 1'b0;
591 rx_fifo_wvalid_o = 1'b0;
592 rx_fifo_wdata_o = RX_FIFO_WIDTH'(0);
593 event_nak_o = 1'b0;
594 event_sda_unstable_o = 1'b0;
595 event_cmd_complete_o = 1'b0;
596 end
597 endcase // unique case (state_q)
598 end
599
600 // Conditional state transition
601 always_comb begin : state_functions
602 1/1 state_d = state_q;
Tests: T1 T2 T3
603 1/1 load_tcount = 1'b0;
Tests: T1 T2 T3
604 1/1 tcount_sel = tNoDelay;
Tests: T1 T2 T3
605 1/1 bit_decr = 1'b0;
Tests: T1 T2 T3
606 1/1 bit_clr = 1'b0;
Tests: T1 T2 T3
607 1/1 byte_decr = 1'b0;
Tests: T1 T2 T3
608 1/1 byte_clr = 1'b0;
Tests: T1 T2 T3
609 1/1 read_byte_clr = 1'b0;
Tests: T1 T2 T3
610 1/1 shift_data_en = 1'b0;
Tests: T1 T2 T3
611 1/1 req_restart = 1'b0;
Tests: T1 T2 T3
612 1/1 auto_stop_d = auto_stop_q;
Tests: T1 T2 T3
613
614 1/1 unique case (state_q)
Tests: T1 T2 T3
615 // Idle: initial state, SDA is released (high), and SCL is released if there is no ongoing
616 // transaction.
617 Idle : begin
618 1/1 if (host_enable_i) begin
Tests: T1 T2 T3
619 1/1 if (unhandled_unexp_nak_i || unhandled_nak_timeout_i || halt_controller_i) begin
Tests: T1 T2 T3
620 // If we are awaiting software to handle an unexpected NACK, halt the FSM here.
621 // The current transaction does not end, and SCL remains in its current state.
622 // Software typically should handle an unexpected NACK by either disabling the
623 // controller (causing host_enable_i to fall) or by the following sequence:
624 // 1. Clear and/or populate the FMT FIFO.
625 // 2. Clear CONTROLLER_EVENTS.NACK
626 // Note that if the timeout feature is enabled, the controller will be forced to
627 // issue a Stop if software takes too long to address the NACK. A short timeout
628 // could also be used to automatically issue a Stop whenever an unexpected NACK
629 // occurs.
630 // Note that we may also halt here on a bus timeout or if arbitration was lost, so
631 // software may fix up the FIFOs before beginning a new transaction.
632 1/1 if (trans_started && unhandled_nak_cnt_expired) begin
Tests: T6 T18 T11
633 // If our timeout counter expires, generate a STOP condition automatically.
634 0/1 ==> auto_stop_d = 1'b1;
635 0/1 ==> state_d = ClockStop;
636 0/1 ==> load_tcount = 1'b1;
637 0/1 ==> tcount_sel = tClockStop;
638 end
MISSING_ELSE
639 1/1 end else if (fmt_fifo_rvalid_i) begin
Tests: T1 T2 T3
640 1/1 if (trans_started || bus_free_i) begin
Tests: T2 T3 T4
641 1/1 state_d = Active;
Tests: T2 T3 T4
642 end
MISSING_ELSE
643 end
MISSING_ELSE
644 1/1 end else if (trans_started && !host_enable_i) begin
Tests: T1 T2 T3
645 0/1 ==> auto_stop_d = 1'b1;
646 0/1 ==> state_d = ClockStop;
647 0/1 ==> load_tcount = 1'b1;
648 0/1 ==> tcount_sel = tClockStop;
649 end
MISSING_ELSE
650 end
651
652 ///////////////
653 // HOST MODE //
654 ///////////////
655
656 // SetupStart: SDA and SCL are released
657 SetupStart : begin
658 1/1 if (!trans_started && !scl_i) begin
Tests: T3 T4 T5
659 // This was the start of a transaction, but another device beat us to access. Go back to
660 // Idle, and wait for the next turn.
661 0/1 ==> state_d = Idle;
662 1/1 end else if (trans_started && !scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
Tests: T3 T4 T5
663 // Saw stretching. Remain in this state and don't count down until we see SCL high.
664 0/1 ==> state_d = SetupStart;
665 0/1 ==> load_tcount = 1'b1;
666 // This double-counts the rise time, unfortunately.
667 0/1 ==> tcount_sel = tSetupStart;
668 1/1 end else if (trans_started && !scl_i && scl_i_q) begin
Tests: T3 T4 T5
669 // Failed to issue repeated Start. Effectively lost arbitration.
670 0/1 ==> state_d = Idle;
671 1/1 end else if (tcount_q == 20'd1) begin
Tests: T3 T4 T5
672 1/1 state_d = HoldStart;
Tests: T3 T4 T5
673 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
674 1/1 tcount_sel = tHoldStart;
Tests: T3 T4 T5
675 end
MISSING_ELSE
676 end
677 // HoldStart: SDA is pulled low, SCL is released
678 HoldStart : begin
679 1/1 if (tcount_q == 20'd1 || (!scl_i && scl_i_q)) begin
Tests: T3 T4 T5
680 1/1 state_d = ClockStart;
Tests: T3 T4 T5
681 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
682 1/1 tcount_sel = tClockStart;
Tests: T3 T4 T5
683 end
MISSING_ELSE
684 end
685 // ClockStart: SCL is pulled low, SDA stays low
686 ClockStart : begin
687 1/1 if (tcount_q == 20'd1) begin
Tests: T3 T4 T5
688 1/1 state_d = ClockLow;
Tests: T3 T4 T5
689 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
690 1/1 tcount_sel = tClockLow;
Tests: T3 T4 T5
691 end
MISSING_ELSE
692 end
693 // ClockLow: SCL stays low, shift indexed bit onto SDA
694 ClockLow : begin
695 1/1 if (tcount_q == 20'd1) begin
Tests: T2 T3 T4
696 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
697 1/1 if (pend_restart) begin
Tests: T3 T4 T5
698 1/1 state_d = SetupStart;
Tests: T11 T12 T13
699 1/1 tcount_sel = tSetupStart;
Tests: T11 T12 T13
700 end else begin
701 1/1 state_d = ClockPulse;
Tests: T3 T4 T5
702 1/1 tcount_sel = tClockPulse;
Tests: T3 T4 T5
703 end
704 end
MISSING_ELSE
705 end
706 // ClockPulse: SCL is released, SDA keeps the indexed bit value
707 ClockPulse : begin
708 1/1 if (!scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
Tests: T3 T4 T5
709 // Saw stretching. Remain in this state and don't count down until we see SCL high.
710 0/1 ==> load_tcount = 1'b1;
711 0/1 ==> tcount_sel = tClockHigh;
712 1/1 end else if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
Tests: T3 T4 T5
713 // Unexpected Stop / Start
714 1/1 state_d = Idle;
Tests: T6 T18 T19
715 1/1 end else if (tcount_q == 20'd1 || (!scl_i && scl_i_q)) begin
Tests: T3 T4 T5
716 // Transition either when we finish counting our high period or
717 // another controller pulls clock low.
718 1/1 state_d = HoldBit;
Tests: T3 T4 T5
719 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
720 1/1 tcount_sel = tHoldBit;
Tests: T3 T4 T5
721 end
MISSING_ELSE
722 end
723 // HoldBit: SCL is pulled low
724 HoldBit : begin
725 1/1 if (tcount_q == 20'd1) begin
Tests: T3 T4 T5
726 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
727 1/1 tcount_sel = tClockLow;
Tests: T3 T4 T5
728 1/1 if (bit_index == '0) begin
Tests: T3 T4 T5
729 1/1 state_d = ClockLowAck;
Tests: T3 T4 T5
730 1/1 bit_clr = 1'b1;
Tests: T3 T4 T5
731 end else begin
732 1/1 state_d = ClockLow;
Tests: T3 T4 T5
733 1/1 bit_decr = 1'b1;
Tests: T3 T4 T5
734 end
735 end
MISSING_ELSE
736 end
737 // ClockLowAck: Target is allowed to drive ack back
738 // to host (dut)
739 ClockLowAck : begin
740 1/1 if (tcount_q == 20'd1) begin
Tests: T3 T4 T5
741 1/1 state_d = ClockPulseAck;
Tests: T3 T4 T5
742 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
743 1/1 tcount_sel = tClockPulse;
Tests: T3 T4 T5
744 end
MISSING_ELSE
745 end
746 // ClockPulseAck: SCL is released
747 ClockPulseAck : begin
748 1/1 if (!scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
Tests: T3 T4 T5
749 // Saw stretching. Remain in this state and don't count down until we see SCL high.
750 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
751 1/1 tcount_sel = tClockHigh;
Tests: T3 T4 T5
752 1/1 end else if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
Tests: T3 T4 T5
753 // Unexpected Stop / Start
754 1/1 state_d = Idle;
Tests: T6 T18 T20
755 end else begin
756 1/1 if (tcount_q == 20'd1 || (!scl_i && scl_i_q)) begin
Tests: T3 T4 T5
757 1/1 state_d = HoldDevAck;
Tests: T3 T4 T5
758 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
759 1/1 tcount_sel = tHoldBit;
Tests: T3 T4 T5
760 end
MISSING_ELSE
761 end
762 end
763 // HoldDevAck: SCL is pulled low
764 HoldDevAck : begin
765 1/1 if (tcount_q == 20'd1) begin
Tests: T3 T4 T5
766 1/1 if (fmt_flag_stop_after_i) begin
Tests: T3 T4 T5
767 1/1 state_d = ClockStop;
Tests: T5 T17 T22
768 1/1 load_tcount = 1'b1;
Tests: T5 T17 T22
769 1/1 tcount_sel = tClockStop;
Tests: T5 T17 T22
770 end else begin
771 1/1 state_d = PopFmtFifo;
Tests: T3 T4 T5
772 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
773 1/1 tcount_sel = tNoDelay;
Tests: T3 T4 T5
774 end
775 end
MISSING_ELSE
776 end
777 // ReadClockLow: SCL is pulled low, SDA is released
778 ReadClockLow : begin
779 1/1 if (tcount_q == 20'd1) begin
Tests: T3 T4 T9
780 1/1 state_d = ReadClockPulse;
Tests: T3 T4 T9
781 1/1 load_tcount = 1'b1;
Tests: T3 T4 T9
782 1/1 tcount_sel = tClockPulse;
Tests: T3 T4 T9
783 end
MISSING_ELSE
784 end
785 // ReadClockPulse: SCL is released, the indexed bit value is read off SDA
786 ReadClockPulse : begin
787 1/1 if (!scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
Tests: T3 T4 T9
788 // Saw stretching. Remain in this state and don't count down until we see SCL high.
789 0/1 ==> load_tcount = 1'b1;
790 0/1 ==> tcount_sel = tClockHigh;
791 1/1 end else if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
Tests: T3 T4 T9
792 // Unexpected Stop / Start
793 0/1 ==> state_d = Idle;
794 1/1 end else if (tcount_q == 20'd1 || (!scl_i && scl_i_q)) begin
Tests: T3 T4 T9
795 1/1 state_d = ReadHoldBit;
Tests: T3 T4 T9
796 1/1 load_tcount = 1'b1;
Tests: T3 T4 T9
797 1/1 tcount_sel = tHoldBit;
Tests: T3 T4 T9
798 1/1 shift_data_en = 1'b1; // SDA is sampled on the final clk_i cycle of the SCL pulse.
Tests: T3 T4 T9
799 end
MISSING_ELSE
800 end
801 // ReadHoldBit: SCL is pulled low
802 ReadHoldBit : begin
803 1/1 if (tcount_q == 20'd1) begin
Tests: T3 T4 T9
804 1/1 load_tcount = 1'b1;
Tests: T3 T4 T9
805 1/1 tcount_sel = tClockLow;
Tests: T3 T4 T9
806 1/1 if (bit_index == '0) begin
Tests: T3 T4 T9
807 1/1 state_d = HostClockLowAck;
Tests: T3 T4 T9
808 1/1 bit_clr = 1'b1;
Tests: T3 T4 T9
809 1/1 read_byte_clr = 1'b1;
Tests: T3 T4 T9
810 end else begin
811 1/1 state_d = ReadClockLow;
Tests: T3 T4 T9
812 1/1 bit_decr = 1'b1;
Tests: T3 T4 T9
813 end
814 end
MISSING_ELSE
815 end
816 // HostClockLowAck: SCL is pulled low, SDA is conditional based on
817 // byte position
818 HostClockLowAck : begin
819 1/1 if (tcount_q == 20'd1) begin
Tests: T3 T4 T9
820 1/1 state_d = HostClockPulseAck;
Tests: T3 T4 T9
821 1/1 load_tcount = 1'b1;
Tests: T3 T4 T9
822 1/1 tcount_sel = tClockPulse;
Tests: T3 T4 T9
823 end
MISSING_ELSE
824 end
825 // HostClockPulseAck: SCL is released
826 HostClockPulseAck : begin
827 1/1 if (!scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
Tests: T3 T4 T9
828 // Saw stretching. Remain in this state and don't count down until we see SCL high.
829 0/1 ==> load_tcount = 1'b1;
830 0/1 ==> tcount_sel = tClockHigh;
831 1/1 end else if (scl_i_q && scl_i && (sda_i_q != sda_i)) begin
Tests: T3 T4 T9
832 // Unexpected Stop / Start
833 0/1 ==> state_d = Idle;
834 1/1 end else if (tcount_q == 20'd1 || (!scl_i && scl_i_q)) begin
Tests: T3 T4 T9
835 1/1 state_d = HostHoldBitAck;
Tests: T3 T4 T9
836 1/1 load_tcount = 1'b1;
Tests: T3 T4 T9
837 1/1 tcount_sel = tHoldBit;
Tests: T3 T4 T9
838 end
MISSING_ELSE
839 end
840 // HostHoldBitAck: SCL is pulled low
841 HostHoldBitAck : begin
842 1/1 if (tcount_q == 20'd1) begin
Tests: T3 T4 T9
843 1/1 if (byte_index == 9'd1) begin
Tests: T3 T4 T9
844 1/1 if (fmt_flag_stop_after_i) begin
Tests: T3 T4 T9
845 1/1 state_d = ClockStop;
Tests: T3 T4 T9
846 1/1 load_tcount = 1'b1;
Tests: T3 T4 T9
847 1/1 tcount_sel = tClockStop;
Tests: T3 T4 T9
848 end else begin
849 1/1 state_d = PopFmtFifo;
Tests: T18 T21 T11
850 1/1 load_tcount = 1'b1;
Tests: T18 T21 T11
851 1/1 tcount_sel = tNoDelay;
Tests: T18 T21 T11
852 end
853 end else begin
854 1/1 state_d = ReadClockLow;
Tests: T3 T4 T9
855 1/1 load_tcount = 1'b1;
Tests: T3 T4 T9
856 1/1 tcount_sel = tClockLow;
Tests: T3 T4 T9
857 1/1 byte_decr = 1'b1;
Tests: T3 T4 T9
858 end
859 end
MISSING_ELSE
860 end
861 // ClockStop: SCL is pulled low, SDA stays low
862 ClockStop : begin
863 1/1 if (tcount_q == 20'd1) begin
Tests: T3 T4 T5
864 1/1 state_d = SetupStop;
Tests: T3 T4 T5
865 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
866 1/1 tcount_sel = tSetupStop;
Tests: T3 T4 T5
867 end
MISSING_ELSE
868 end
869 // SetupStop: SDA is pulled low, SCL is released
870 SetupStop : begin
871 1/1 if (!scl_i && !scl_i_q && stretch_predict_cnt_expired) begin
Tests: T3 T4 T5
872 // Saw stretching. Remain in this state and don't count down until we see SCL high.
873 0/1 ==> load_tcount = 1'b1;
874 0/1 ==> tcount_sel = tSetupStop;
875 1/1 end else if (!scl_i && scl_i_q) begin
Tests: T3 T4 T5
876 // Failed to issue Stop before some other device could pull SCL low.
877 0/1 ==> state_d = Idle;
878 1/1 end else if (tcount_q == 20'd1) begin
Tests: T3 T4 T5
879 1/1 state_d = HoldStop;
Tests: T3 T4 T5
880 end
MISSING_ELSE
881 end
882 // HoldStop: SDA and SCL are released
883 HoldStop : begin
884 1/1 if (!sda_i && !scl_i) begin
Tests: T3 T4 T5
885 // Failed to issue Stop before some other device could pull SCL low.
886 0/1 ==> state_d = Idle;
887 0/1 ==> auto_stop_d = 1'b0;
888 1/1 end else if (sda_i) begin
Tests: T3 T4 T5
889 1/1 auto_stop_d = 1'b0;
Tests: T3 T4 T5
890 1/1 if (auto_stop_q) begin
Tests: T3 T4 T5
891 // If this Stop symbol was generated automatically, go back to Idle.
892 0/1 ==> state_d = Idle;
893 0/1 ==> load_tcount = 1'b1;
894 0/1 ==> tcount_sel = tNoDelay;
895 end else begin
896 1/1 state_d = PopFmtFifo;
Tests: T3 T4 T5
897 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
898 1/1 tcount_sel = tNoDelay;
Tests: T3 T4 T5
899 end
900 end
MISSING_ELSE
901 end
902 // Active: continue while keeping SCL low
903 Active : begin
904 1/1 if (fmt_flag_read_bytes_i) begin
Tests: T2 T3 T4
905 1/1 byte_clr = 1'b1;
Tests: T3 T4 T9
906 1/1 state_d = ReadClockLow;
Tests: T3 T4 T9
907 1/1 load_tcount = 1'b1;
Tests: T3 T4 T9
908 1/1 tcount_sel = tClockLow;
Tests: T3 T4 T9
909 1/1 end else if (fmt_flag_start_before_i && !trans_started) begin
Tests: T2 T3 T4
910 1/1 state_d = SetupStart;
Tests: T3 T4 T5
911 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
912 1/1 tcount_sel = tSetupStart;
Tests: T3 T4 T5
913 end else begin
914 1/1 state_d = ClockLow;
Tests: T2 T5 T6
915 1/1 load_tcount = 1'b1;
Tests: T2 T5 T6
916 1/1 req_restart = fmt_flag_start_before_i;
Tests: T2 T5 T6
917 1/1 tcount_sel = tClockLow;
Tests: T2 T5 T6
918 end
919 end
920 // PopFmtFifo: pop fmt_fifo item
921 PopFmtFifo : begin
922 1/1 if (!host_enable_i && trans_started) begin
Tests: T3 T4 T5
923 0/1 ==> auto_stop_d = 1'b1;
924 0/1 ==> state_d = ClockStop;
925 0/1 ==> load_tcount = 1'b1;
926 0/1 ==> tcount_sel = tClockStop;
927 1/1 end else if (!host_enable_i || (fmt_fifo_depth_i == 7'h1) ||
Tests: T3 T4 T5
928 unhandled_unexp_nak_i || !trans_started) begin
929 1/1 state_d = Idle;
Tests: T3 T4 T5
930 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
931 1/1 tcount_sel = tNoDelay;
Tests: T3 T4 T5
932 end else begin
933 1/1 state_d = Active;
Tests: T3 T4 T5
934 1/1 load_tcount = 1'b1;
Tests: T3 T4 T5
935 1/1 tcount_sel = tNoDelay;
Tests: T3 T4 T5
936 end
937 end
938
939 // default
940 default : begin
941 state_d = Idle;
942 load_tcount = 1'b0;
943 tcount_sel = tNoDelay;
944 bit_decr = 1'b0;
945 bit_clr = 1'b0;
946 byte_decr = 1'b0;
947 byte_clr = 1'b0;
948 read_byte_clr = 1'b0;
949 shift_data_en = 1'b0;
950 auto_stop_d = 1'b0;
951 end
952 endcase // unique case (state_q)
953
954 1/1 if (trans_started && (sda_interference_i || ctrl_symbol_failed)) begin
Tests: T1 T2 T3
955 1/1 state_d = Idle;
Tests: T6 T18 T20
956 end
MISSING_ELSE
957 end
958
959 // Synchronous state transition
960 always_ff @ (posedge clk_i or negedge rst_ni) begin : state_transition
961 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
962 1/1 state_q <= Idle;
Tests: T1 T2 T3
963 end else begin
964 1/1 state_q <= state_d;
Tests: T1 T2 T3
965 end
966 end
967
968 1/1 assign scl_o = scl_d;
Tests: T1 T2 T3
969 1/1 assign sda_o = sda_d;
Tests: T1 T2 T3
970
971 // Target stretched clock beyond timeout
972 1/1 assign event_stretch_timeout_o = stretch_en && timeout_enable_i &&
Tests: T1 T2 T3