Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	750210	1			T1	7		T2	2		T3	2
all_values[1]	750210	1			T1	7		T2	2		T3	2
all_values[2]	750210	1			T1	7		T2	2		T3	2
all_values[3]	750210	1			T1	7		T2	2		T3	2
all_values[4]	750210	1			T1	7		T2	2		T3	2
all_values[5]	750210	1			T1	7		T2	2		T3	2
all_values[6]	750210	1			T1	7		T2	2		T3	2
all_values[7]	750210	1			T1	7		T2	2		T3	2
all_values[8]	750210	1			T1	7		T2	2		T3	2
all_values[9]	750210	1			T1	7		T2	2		T3	2
all_values[10]	750210	1			T1	7		T2	2		T3	2
all_values[11]	750210	1			T1	7		T2	2		T3	2
all_values[12]	750210	1			T1	7		T2	2		T3	2
all_values[13]	750210	1			T1	7		T2	2		T3	2
all_values[14]	750210	1			T1	7		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9285039

1

T1

105

T2

26

T3

26

auto[1]

1968111

1

T2

4

T3

4

T5

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10629317

1

T1

105

T2

30

T3

30

auto[1]

623833

1

T123

4348

T194

86087

T132

14899

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104183	1			T1	7		T4	1		T6	2
all_values[0]	auto[0]	auto[1]	8476	1			T123	4		T194	579		T132	459
all_values[0]	auto[1]	auto[0]	604289	1			T2	2		T3	2		T5	2
all_values[0]	auto[1]	auto[1]	33262	1			T123	286		T194	5159		T132	686
all_values[1]	auto[0]	auto[0]	708244	1			T1	7		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	41598	1			T123	285		T194	5737		T132	1139
all_values[1]	auto[1]	auto[0]	224	1			T34	3		T274	18		T275	9
all_values[1]	auto[1]	auto[1]	144	1			T123	5		T194	2		T132	6
all_values[2]	auto[0]	auto[0]	709407	1			T1	7		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	40480	1			T123	288		T194	5734		T132	10
all_values[2]	auto[1]	auto[0]	193	1			T172	1		T201	2		T62	1
all_values[2]	auto[1]	auto[1]	130	1			T123	3		T194	2		T132	2
all_values[3]	auto[0]	auto[0]	708487	1			T1	7		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	41557	1			T123	279		T194	5737		T132	1137
all_values[3]	auto[1]	auto[1]	166	1			T123	2		T194	3		T132	7
all_values[4]	auto[0]	auto[0]	708459	1			T1	7		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	41594	1			T123	285		T194	5734		T132	1139
all_values[4]	auto[1]	auto[0]	14	1			T29	1		T261	1		T262	1
all_values[4]	auto[1]	auto[1]	143	1			T123	6		T194	5		T132	6
all_values[5]	auto[0]	auto[0]	708466	1			T1	7		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	41565	1			T123	288		T194	5733		T132	1141
all_values[5]	auto[1]	auto[1]	179	1			T123	2		T194	6		T132	3
all_values[6]	auto[0]	auto[0]	708471	1			T1	7		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	41578	1			T123	286		T194	5736		T132	1138
all_values[6]	auto[1]	auto[1]	161	1			T123	4		T194	4		T132	5
all_values[7]	auto[0]	auto[0]	678260	1			T1	7		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	39953	1			T123	233		T194	5483		T132	1092
all_values[7]	auto[1]	auto[0]	30210	1			T8	1		T11	245		T25	1
all_values[7]	auto[1]	auto[1]	1787	1			T123	58		T194	256		T132	51
all_values[8]	auto[0]	auto[0]	708498	1			T1	7		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	41560	1			T123	287		T194	5733		T132	1143
all_values[8]	auto[1]	auto[1]	152	1			T123	4		T194	6		T132	2
all_values[9]	auto[0]	auto[0]	191776	1			T1	7		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	9635	1			T123	272		T194	305		T132	1124
all_values[9]	auto[1]	auto[0]	516679	1			T8	1		T10	1		T11	4737
all_values[9]	auto[1]	auto[1]	32120	1			T123	18		T194	5435		T132	20
all_values[10]	auto[0]	auto[0]	708456	1			T1	7		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	41616	1			T123	287		T194	5736		T132	1144
all_values[10]	auto[1]	auto[1]	138	1			T123	4		T194	2		T132	1
all_values[11]	auto[0]	auto[0]	2338	1			T1	7		T4	1		T6	2
all_values[11]	auto[0]	auto[1]	287	1			T194	31		T132	3		T40	15
all_values[11]	auto[1]	auto[0]	706125	1			T2	2		T3	2		T5	2
all_values[11]	auto[1]	auto[1]	41460	1			T123	291		T194	5709		T132	1140
all_values[12]	auto[0]	auto[0]	708416	1			T1	7		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	41592	1			T123	285		T194	5736		T132	1140
all_values[12]	auto[1]	auto[0]	65	1			T62	1		T68	1		T276	1
all_values[12]	auto[1]	auto[1]	137	1			T123	5		T194	4		T132	5
all_values[13]	auto[0]	auto[0]	709606	1			T1	7		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	40444	1			T123	284		T194	5736		T132	8
all_values[13]	auto[1]	auto[1]	160	1			T123	6		T194	4		T132	3
all_values[14]	auto[0]	auto[0]	708451	1			T1	7		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	41586	1			T123	286		T194	5735		T132	1145
all_values[14]	auto[1]	auto[1]	173	1			T123	5		T194	5		T40	1