Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	750210	1			T1	7		T2	2		T3	2
all_pins[1]	750210	1			T1	7		T2	2		T3	2
all_pins[2]	750210	1			T1	7		T2	2		T3	2
all_pins[3]	750210	1			T1	7		T2	2		T3	2
all_pins[4]	750210	1			T1	7		T2	2		T3	2
all_pins[5]	750210	1			T1	7		T2	2		T3	2
all_pins[6]	750210	1			T1	7		T2	2		T3	2
all_pins[7]	750210	1			T1	7		T2	2		T3	2
all_pins[8]	750210	1			T1	7		T2	2		T3	2
all_pins[9]	750210	1			T1	7		T2	2		T3	2
all_pins[10]	750210	1			T1	7		T2	2		T3	2
all_pins[11]	750210	1			T1	7		T2	2		T3	2
all_pins[12]	750210	1			T1	7		T2	2		T3	2
all_pins[13]	750210	1			T1	7		T2	2		T3	2
all_pins[14]	750210	1			T1	7		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9291262	1			T1	105		T2	26		T3	26
values[0x1]	1961888	1			T2	4		T3	4		T5	4
transitions[0x0=>0x1]	1961315	1			T2	4		T3	4		T5	4
transitions[0x1=>0x0]	1960015	1			T2	3		T3	3		T5	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	116228	1			T1	7		T4	1		T6	2
all_pins[0]	values[0x1]	633982	1			T2	2		T3	2		T5	2
all_pins[0]	transitions[0x0=>0x1]	633701	1			T2	2		T3	2		T5	2
all_pins[0]	transitions[0x1=>0x0]	52	1			T194	1		T132	2		T285	5
all_pins[1]	values[0x0]	749877	1			T1	7		T2	2		T3	2
all_pins[1]	values[0x1]	333	1			T34	3		T274	21		T275	11
all_pins[1]	transitions[0x0=>0x1]	318	1			T34	3		T274	21		T275	11
all_pins[1]	transitions[0x1=>0x0]	94	1			T172	1		T286	1		T276	1
all_pins[2]	values[0x0]	750101	1			T1	7		T2	2		T3	2
all_pins[2]	values[0x1]	109	1			T172	1		T286	1		T276	1
all_pins[2]	transitions[0x0=>0x1]	98	1			T172	1		T286	1		T276	1
all_pins[2]	transitions[0x1=>0x0]	68	1			T123	2		T194	1		T132	4
all_pins[3]	values[0x0]	750131	1			T1	7		T2	2		T3	2
all_pins[3]	values[0x1]	79	1			T123	2		T194	2		T132	4
all_pins[3]	transitions[0x0=>0x1]	62	1			T123	1		T194	1		T132	4
all_pins[3]	transitions[0x1=>0x0]	77	1			T29	1		T261	1		T262	1
all_pins[4]	values[0x0]	750116	1			T1	7		T2	2		T3	2
all_pins[4]	values[0x1]	94	1			T29	1		T261	1		T262	1
all_pins[4]	transitions[0x0=>0x1]	72	1			T29	1		T261	1		T262	1
all_pins[4]	transitions[0x1=>0x0]	77	1			T123	2		T40	3		T242	1
all_pins[5]	values[0x0]	750111	1			T1	7		T2	2		T3	2
all_pins[5]	values[0x1]	99	1			T123	2		T194	3		T40	5
all_pins[5]	transitions[0x0=>0x1]	76	1			T123	2		T194	3		T40	1
all_pins[5]	transitions[0x1=>0x0]	51	1			T132	2		T40	2		T242	1
all_pins[6]	values[0x0]	750136	1			T1	7		T2	2		T3	2
all_pins[6]	values[0x1]	74	1			T132	2		T40	6		T242	1
all_pins[6]	transitions[0x0=>0x1]	60	1			T132	2		T40	5		T242	1
all_pins[6]	transitions[0x1=>0x0]	34468	1			T8	1		T11	256		T25	1
all_pins[7]	values[0x0]	715728	1			T1	7		T2	2		T3	2
all_pins[7]	values[0x1]	34482	1			T8	1		T11	256		T25	1
all_pins[7]	transitions[0x0=>0x1]	34460	1			T8	1		T11	256		T25	1
all_pins[7]	transitions[0x1=>0x0]	52	1			T123	2		T194	1		T40	1
all_pins[8]	values[0x0]	750136	1			T1	7		T2	2		T3	2
all_pins[8]	values[0x1]	74	1			T123	3		T194	4		T40	1
all_pins[8]	transitions[0x0=>0x1]	52	1			T123	3		T194	2		T40	1
all_pins[8]	transitions[0x1=>0x0]	548702	1			T8	1		T10	1		T11	4737
all_pins[9]	values[0x0]	201486	1			T1	7		T2	2		T3	2
all_pins[9]	values[0x1]	548724	1			T8	1		T10	1		T11	4737
all_pins[9]	transitions[0x0=>0x1]	548706	1			T8	1		T10	1		T11	4737
all_pins[9]	transitions[0x1=>0x0]	45	1			T123	1		T132	1		T40	1
all_pins[10]	values[0x0]	750147	1			T1	7		T2	2		T3	2
all_pins[10]	values[0x1]	63	1			T123	1		T132	1		T40	1
all_pins[10]	transitions[0x0=>0x1]	46	1			T40	1		T242	2		T287	2
all_pins[10]	transitions[0x1=>0x0]	743454	1			T2	2		T3	2		T5	2
all_pins[11]	values[0x0]	6739	1			T1	7		T4	1		T6	2
all_pins[11]	values[0x1]	743471	1			T2	2		T3	2		T5	2
all_pins[11]	transitions[0x0=>0x1]	743438	1			T2	2		T3	2		T5	2
all_pins[11]	transitions[0x1=>0x0]	101	1			T62	1		T68	1		T69	1
all_pins[12]	values[0x0]	750076	1			T1	7		T2	2		T3	2
all_pins[12]	values[0x1]	134	1			T62	1		T68	1		T276	1
all_pins[12]	transitions[0x0=>0x1]	116	1			T62	1		T68	1		T276	1
all_pins[12]	transitions[0x1=>0x0]	60	1			T123	2		T132	1		T40	3
all_pins[13]	values[0x0]	750132	1			T1	7		T2	2		T3	2
all_pins[13]	values[0x1]	78	1			T123	4		T194	1		T132	1
all_pins[13]	transitions[0x0=>0x1]	50	1			T123	4		T194	1		T132	1
all_pins[13]	transitions[0x1=>0x0]	64	1			T123	2		T194	2		T40	1
all_pins[14]	values[0x0]	750118	1			T1	7		T2	2		T3	2
all_pins[14]	values[0x1]	92	1			T123	2		T194	2		T40	1
all_pins[14]	transitions[0x0=>0x1]	60	1			T123	1		T194	2		T242	1
all_pins[14]	transitions[0x1=>0x0]	632650	1			T2	1		T3	1		T5	1