Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	346	1			T123	11		T194	7		T132	11
all_values[1]	346	1			T123	11		T194	7		T132	11
all_values[2]	346	1			T123	11		T194	7		T132	11
all_values[3]	346	1			T123	11		T194	7		T132	11
all_values[4]	346	1			T123	11		T194	7		T132	11
all_values[5]	346	1			T123	11		T194	7		T132	11
all_values[6]	346	1			T123	11		T194	7		T132	11
all_values[7]	346	1			T123	11		T194	7		T132	11
all_values[8]	346	1			T123	11		T194	7		T132	11
all_values[9]	346	1			T123	11		T194	7		T132	11
all_values[10]	346	1			T123	11		T194	7		T132	11
all_values[11]	346	1			T123	11		T194	7		T132	11
all_values[12]	346	1			T123	11		T194	7		T132	11
all_values[13]	346	1			T123	11		T194	7		T132	11
all_values[14]	346	1			T123	11		T194	7		T132	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2885

1

T123

74

T194

59

T132

73

auto[1]

2305

1

T123

91

T194

46

T132

92

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

848

1

T123

16

T194

13

T132

18

auto[1]

4342

1

T123

149

T194

92

T132

147

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3072

1

T123

99

T194

57

T132

99

auto[1]

2118

1

T123

66

T194

48

T132

66

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	44	1			T194	1		T133	1		T253	1
all_values[0]	auto[0]	auto[0]	auto[1]	69	1			T123	2		T194	1		T132	5
all_values[0]	auto[0]	auto[1]	auto[0]	13	1			T123	1		T194	1		T288	1
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T123	2		T194	2		T132	2
all_values[0]	auto[1]	auto[0]	auto[1]	76	1			T123	2		T194	1		T132	2
all_values[0]	auto[1]	auto[1]	auto[1]	64	1			T123	4		T194	1		T132	2
all_values[1]	auto[0]	auto[0]	auto[0]	31	1			T123	1		T194	1		T40	1
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T123	4		T194	4		T132	1
all_values[1]	auto[0]	auto[1]	auto[0]	22	1			T288	3		T289	3		T290	1
all_values[1]	auto[0]	auto[1]	auto[1]	63	1			T123	1		T132	4		T40	2
all_values[1]	auto[1]	auto[0]	auto[1]	77	1			T123	3		T194	1		T132	2
all_values[1]	auto[1]	auto[1]	auto[1]	67	1			T123	2		T194	1		T132	4
all_values[2]	auto[0]	auto[0]	auto[0]	28	1			T194	1		T291	1		T292	2
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T123	4		T132	1		T40	3
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T194	3		T132	4		T242	1
all_values[2]	auto[0]	auto[1]	auto[1]	67	1			T123	4		T194	1		T132	4
all_values[2]	auto[1]	auto[0]	auto[1]	73	1			T40	3		T242	1		T287	4
all_values[2]	auto[1]	auto[1]	auto[1]	57	1			T123	3		T194	2		T132	2
all_values[3]	auto[0]	auto[0]	auto[0]	41	1			T123	3		T40	1		T287	2
all_values[3]	auto[0]	auto[0]	auto[1]	69	1			T194	3		T132	2		T40	3
all_values[3]	auto[0]	auto[1]	auto[0]	30	1			T123	6		T132	1		T253	2
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T123	1		T194	1		T132	3
all_values[3]	auto[1]	auto[0]	auto[1]	80	1			T194	2		T132	2		T40	5
all_values[3]	auto[1]	auto[1]	auto[1]	57	1			T123	1		T194	1		T132	3
all_values[4]	auto[0]	auto[0]	auto[0]	39	1			T194	1		T40	1		T242	1
all_values[4]	auto[0]	auto[0]	auto[1]	92	1			T123	1		T132	5		T40	4
all_values[4]	auto[0]	auto[1]	auto[0]	18	1			T242	1		T287	2		T289	2
all_values[4]	auto[0]	auto[1]	auto[1]	54	1			T123	4		T194	1		T40	1
all_values[4]	auto[1]	auto[0]	auto[1]	74	1			T123	2		T132	3		T40	3
all_values[4]	auto[1]	auto[1]	auto[1]	69	1			T123	4		T194	5		T132	3
all_values[5]	auto[0]	auto[0]	auto[0]	35	1			T194	1		T287	1		T134	1
all_values[5]	auto[0]	auto[0]	auto[1]	67	1			T123	4		T194	2		T132	3
all_values[5]	auto[0]	auto[1]	auto[0]	16	1			T123	1		T132	1		T293	1
all_values[5]	auto[0]	auto[1]	auto[1]	78	1			T123	4		T194	2		T132	2
all_values[5]	auto[1]	auto[0]	auto[1]	88	1			T194	1		T132	3		T40	2
all_values[5]	auto[1]	auto[1]	auto[1]	62	1			T123	2		T194	1		T132	2
all_values[6]	auto[0]	auto[0]	auto[0]	34	1			T242	4		T287	1		T294	1
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T123	4		T194	4		T132	1
all_values[6]	auto[0]	auto[1]	auto[0]	23	1			T123	1		T132	2		T134	1
all_values[6]	auto[0]	auto[1]	auto[1]	68	1			T123	4		T132	3		T40	3
all_values[6]	auto[1]	auto[0]	auto[1]	82	1			T194	3		T132	2		T40	2
all_values[6]	auto[1]	auto[1]	auto[1]	56	1			T123	2		T132	3		T40	4
all_values[7]	auto[0]	auto[0]	auto[0]	25	1			T194	1		T132	1		T242	1
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T123	3		T132	1		T40	5
all_values[7]	auto[0]	auto[1]	auto[0]	30	1			T132	1		T287	2		T295	2
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T123	2		T194	2		T132	1
all_values[7]	auto[1]	auto[0]	auto[1]	78	1			T123	2		T132	4		T40	2
all_values[7]	auto[1]	auto[1]	auto[1]	64	1			T123	4		T194	4		T132	3
all_values[8]	auto[0]	auto[0]	auto[0]	55	1			T194	1		T40	4		T242	1
all_values[8]	auto[0]	auto[0]	auto[1]	77	1			T123	4		T194	1		T132	4
all_values[8]	auto[0]	auto[1]	auto[0]	28	1			T242	1		T287	1		T295	2
all_values[8]	auto[0]	auto[1]	auto[1]	48	1			T123	2		T194	1		T132	2
all_values[8]	auto[1]	auto[0]	auto[1]	74	1			T123	2		T194	2		T132	3
all_values[8]	auto[1]	auto[1]	auto[1]	64	1			T123	3		T194	2		T132	2
all_values[9]	auto[0]	auto[0]	auto[0]	25	1			T123	1		T40	2		T242	1
all_values[9]	auto[0]	auto[0]	auto[1]	84	1			T123	5		T194	1		T132	2
all_values[9]	auto[0]	auto[1]	auto[0]	19	1			T132	1		T40	1		T253	1
all_values[9]	auto[0]	auto[1]	auto[1]	72	1			T123	1		T194	2		T132	3
all_values[9]	auto[1]	auto[0]	auto[1]	82	1			T123	4		T194	3		T132	1
all_values[9]	auto[1]	auto[1]	auto[1]	64	1			T194	1		T132	4		T40	2
all_values[10]	auto[0]	auto[0]	auto[0]	31	1			T194	2		T133	1		T253	2
all_values[10]	auto[0]	auto[0]	auto[1]	100	1			T123	3		T194	3		T132	5
all_values[10]	auto[0]	auto[1]	auto[0]	14	1			T294	2		T296	1		T297	1
all_values[10]	auto[0]	auto[1]	auto[1]	63	1			T123	4		T132	5		T40	1
all_values[10]	auto[1]	auto[0]	auto[1]	83	1			T123	3		T194	2		T40	5
all_values[10]	auto[1]	auto[1]	auto[1]	55	1			T123	1		T132	1		T242	4
all_values[11]	auto[0]	auto[0]	auto[0]	23	1			T287	1		T293	1		T295	2
all_values[11]	auto[0]	auto[0]	auto[1]	70	1			T194	1		T132	3		T40	3
all_values[11]	auto[0]	auto[1]	auto[0]	28	1			T132	2		T295	5		T298	1
all_values[11]	auto[0]	auto[1]	auto[1]	79	1			T123	4		T194	4		T132	2
all_values[11]	auto[1]	auto[0]	auto[1]	80	1			T123	3		T194	1		T132	3
all_values[11]	auto[1]	auto[1]	auto[1]	66	1			T123	4		T194	1		T132	1
all_values[12]	auto[0]	auto[0]	auto[0]	36	1			T242	2		T287	1		T133	1
all_values[12]	auto[0]	auto[0]	auto[1]	65	1			T123	2		T194	2		T132	3
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T123	1		T242	3		T287	1
all_values[12]	auto[0]	auto[1]	auto[1]	79	1			T123	3		T194	1		T132	3
all_values[12]	auto[1]	auto[0]	auto[1]	81	1			T123	1		T194	4		T132	2
all_values[12]	auto[1]	auto[1]	auto[1]	56	1			T123	4		T132	3		T242	1
all_values[13]	auto[0]	auto[0]	auto[0]	38	1			T132	1		T40	1		T242	1
all_values[13]	auto[0]	auto[0]	auto[1]	78	1			T123	2		T194	2		T132	2
all_values[13]	auto[0]	auto[1]	auto[0]	25	1			T123	1		T132	4		T291	3
all_values[13]	auto[0]	auto[1]	auto[1]	68	1			T123	3		T194	2		T132	1
all_values[13]	auto[1]	auto[0]	auto[1]	76	1			T123	2		T194	2		T132	2
all_values[13]	auto[1]	auto[1]	auto[1]	61	1			T123	3		T194	1		T132	1
all_values[14]	auto[0]	auto[0]	auto[0]	29	1			T289	2		T299	1		T298	3
all_values[14]	auto[0]	auto[0]	auto[1]	72	1			T123	5		T194	1		T132	3
all_values[14]	auto[0]	auto[1]	auto[0]	8	1			T294	1		T298	1		T300	1
all_values[14]	auto[0]	auto[1]	auto[1]	85	1			T123	1		T132	5		T40	5
all_values[14]	auto[1]	auto[0]	auto[1]	88	1			T123	2		T194	3		T132	1
all_values[14]	auto[1]	auto[1]	auto[1]	64	1			T123	3		T194	3		T132	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal