Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	654709	1			T1	1		T2	2		T3	9
all_values[1]	654709	1			T1	1		T2	2		T3	9
all_values[2]	654709	1			T1	1		T2	2		T3	9
all_values[3]	654709	1			T1	1		T2	2		T3	9
all_values[4]	654709	1			T1	1		T2	2		T3	9
all_values[5]	654709	1			T1	1		T2	2		T3	9
all_values[6]	654709	1			T1	1		T2	2		T3	9
all_values[7]	654709	1			T1	1		T2	2		T3	9
all_values[8]	654709	1			T1	1		T2	2		T3	9
all_values[9]	654709	1			T1	1		T2	2		T3	9
all_values[10]	654709	1			T1	1		T2	2		T3	9
all_values[11]	654709	1			T1	1		T2	2		T3	9
all_values[12]	654709	1			T1	1		T2	2		T3	9
all_values[13]	654709	1			T1	1		T2	2		T3	9
all_values[14]	654709	1			T1	1		T2	2		T3	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8123590

1

T1

15

T2

30

T3

121

auto[1]

1697045

1

T3

14

T4

6

T5

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9587245

1

T1

15

T2

30

T3

135

auto[1]

233390

1

T191

13221

T23

213

T35

103692

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99131	1			T1	1		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	2393	1			T191	371		T23	10		T35	1352
all_values[0]	auto[1]	auto[0]	539218	1			T3	7		T4	2		T5	2
all_values[0]	auto[1]	auto[1]	13967	1			T191	511		T23	5		T35	6055
all_values[1]	auto[0]	auto[0]	638153	1			T1	1		T2	2		T3	9
all_values[1]	auto[0]	auto[1]	16243	1			T191	878		T23	13		T35	7404
all_values[1]	auto[1]	auto[0]	192	1			T25	4		T36	2		T273	2
all_values[1]	auto[1]	auto[1]	121	1			T191	3		T23	1		T35	3
all_values[2]	auto[0]	auto[0]	638163	1			T1	1		T2	2		T3	9
all_values[2]	auto[0]	auto[1]	16224	1			T191	878		T35	7405		T42	7
all_values[2]	auto[1]	auto[0]	194	1			T70	1		T153	2		T62	1
all_values[2]	auto[1]	auto[1]	128	1			T191	4		T35	2		T42	2
all_values[3]	auto[0]	auto[0]	640683	1			T1	1		T2	2		T3	9
all_values[3]	auto[0]	auto[1]	13880	1			T191	880		T23	12		T35	7403
all_values[3]	auto[1]	auto[1]	146	1			T23	4		T35	3		T42	4
all_values[4]	auto[0]	auto[0]	638311	1			T1	1		T2	2		T3	9
all_values[4]	auto[0]	auto[1]	16241	1			T191	878		T23	14		T35	7406
all_values[4]	auto[1]	auto[0]	22	1			T29	1		T254	1		T44	1
all_values[4]	auto[1]	auto[1]	135	1			T191	3		T23	1		T35	1
all_values[5]	auto[0]	auto[0]	640706	1			T1	1		T2	2		T3	9
all_values[5]	auto[0]	auto[1]	13876	1			T191	881		T23	12		T35	7403
all_values[5]	auto[1]	auto[1]	127	1			T191	1		T23	3		T35	3
all_values[6]	auto[0]	auto[0]	638331	1			T1	1		T2	2		T3	9
all_values[6]	auto[0]	auto[1]	16225	1			T191	878		T23	12		T35	7403
all_values[6]	auto[1]	auto[1]	153	1			T191	4		T23	3		T35	4
all_values[7]	auto[0]	auto[0]	611465	1			T1	1		T2	2		T3	9
all_values[7]	auto[0]	auto[1]	15266	1			T191	662		T23	14		T35	6965
all_values[7]	auto[1]	auto[0]	26871	1			T4	1		T17	175		T26	1
all_values[7]	auto[1]	auto[1]	1107	1			T191	219		T23	2		T35	442
all_values[8]	auto[0]	auto[0]	638331	1			T1	1		T2	2		T3	9
all_values[8]	auto[0]	auto[1]	16228	1			T191	881		T23	12		T35	7405
all_values[8]	auto[1]	auto[1]	150	1			T191	1		T23	2		T35	2
all_values[9]	auto[0]	auto[0]	188506	1			T1	1		T2	2		T3	9
all_values[9]	auto[0]	auto[1]	4540	1			T191	845		T23	11		T42	7
all_values[9]	auto[1]	auto[0]	457246	1			T4	1		T17	3560		T48	1
all_values[9]	auto[1]	auto[1]	4417	1			T191	36		T23	3		T42	1
all_values[10]	auto[0]	auto[0]	638345	1			T1	1		T2	2		T3	9
all_values[10]	auto[0]	auto[1]	16241	1			T191	879		T23	14		T35	7406
all_values[10]	auto[1]	auto[1]	123	1			T191	2		T23	1		T35	1
all_values[11]	auto[0]	auto[0]	2259	1			T1	1		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	228	1			T191	8		T23	11		T35	28
all_values[11]	auto[1]	auto[0]	636086	1			T3	7		T4	2		T5	2
all_values[11]	auto[1]	auto[1]	16136	1			T191	874		T23	5		T35	7378
all_values[12]	auto[0]	auto[0]	638299	1			T1	1		T2	2		T3	9
all_values[12]	auto[0]	auto[1]	16223	1			T191	876		T23	14		T35	7405
all_values[12]	auto[1]	auto[0]	60	1			T70	1		T62	1		T63	1
all_values[12]	auto[1]	auto[1]	127	1			T191	6		T23	2		T35	2
all_values[13]	auto[0]	auto[0]	638345	1			T1	1		T2	2		T3	9
all_values[13]	auto[0]	auto[1]	16216	1			T191	878		T23	14		T35	7403
all_values[13]	auto[1]	auto[1]	148	1			T191	2		T23	2		T35	3
all_values[14]	auto[0]	auto[0]	638328	1			T1	1		T2	2		T3	9
all_values[14]	auto[0]	auto[1]	16210	1			T191	879		T23	13		T35	7403
all_values[14]	auto[1]	auto[1]	171	1			T191	3		T23	3		T35	2