Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	654709	1			T1	1		T2	2		T3	9
all_pins[1]	654709	1			T1	1		T2	2		T3	9
all_pins[2]	654709	1			T1	1		T2	2		T3	9
all_pins[3]	654709	1			T1	1		T2	2		T3	9
all_pins[4]	654709	1			T1	1		T2	2		T3	9
all_pins[5]	654709	1			T1	1		T2	2		T3	9
all_pins[6]	654709	1			T1	1		T2	2		T3	9
all_pins[7]	654709	1			T1	1		T2	2		T3	9
all_pins[8]	654709	1			T1	1		T2	2		T3	9
all_pins[9]	654709	1			T1	1		T2	2		T3	9
all_pins[10]	654709	1			T1	1		T2	2		T3	9
all_pins[11]	654709	1			T1	1		T2	2		T3	9
all_pins[12]	654709	1			T1	1		T2	2		T3	9
all_pins[13]	654709	1			T1	1		T2	2		T3	9
all_pins[14]	654709	1			T1	1		T2	2		T3	9

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8129232	1			T1	15		T2	30		T3	121
values[0x1]	1691403	1			T3	14		T4	6		T5	4
transitions[0x0=>0x1]	1690906	1			T3	14		T4	6		T5	4
transitions[0x1=>0x0]	1689598	1			T3	13		T4	5		T5	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	104775	1			T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	549934	1			T3	7		T4	2		T5	2
all_pins[0]	transitions[0x0=>0x1]	549704	1			T3	7		T4	2		T5	2
all_pins[0]	transitions[0x1=>0x0]	45	1			T191	1		T23	1		T35	1
all_pins[1]	values[0x0]	654434	1			T1	1		T2	2		T3	9
all_pins[1]	values[0x1]	275	1			T25	4		T36	2		T273	2
all_pins[1]	transitions[0x0=>0x1]	262	1			T25	4		T36	2		T273	2
all_pins[1]	transitions[0x1=>0x0]	94	1			T70	1		T278	1		T167	1
all_pins[2]	values[0x0]	654602	1			T1	1		T2	2		T3	9
all_pins[2]	values[0x1]	107	1			T70	1		T278	1		T167	1
all_pins[2]	transitions[0x0=>0x1]	99	1			T70	1		T278	1		T167	1
all_pins[2]	transitions[0x1=>0x0]	66	1			T23	2		T35	1		T42	3
all_pins[3]	values[0x0]	654635	1			T1	1		T2	2		T3	9
all_pins[3]	values[0x1]	74	1			T23	2		T35	1		T42	4
all_pins[3]	transitions[0x0=>0x1]	59	1			T23	2		T35	1		T42	3
all_pins[3]	transitions[0x1=>0x0]	85	1			T29	1		T254	1		T44	1
all_pins[4]	values[0x0]	654609	1			T1	1		T2	2		T3	9
all_pins[4]	values[0x1]	100	1			T29	1		T254	1		T44	1
all_pins[4]	transitions[0x0=>0x1]	85	1			T29	1		T254	1		T44	1
all_pins[4]	transitions[0x1=>0x0]	50	1			T191	1		T35	2		T133	4
all_pins[5]	values[0x0]	654644	1			T1	1		T2	2		T3	9
all_pins[5]	values[0x1]	65	1			T191	1		T35	2		T133	6
all_pins[5]	transitions[0x0=>0x1]	45	1			T133	6		T252	3		T279	2
all_pins[5]	transitions[0x1=>0x0]	58	1			T191	3		T23	1		T35	1
all_pins[6]	values[0x0]	654631	1			T1	1		T2	2		T3	9
all_pins[6]	values[0x1]	78	1			T191	4		T23	1		T35	3
all_pins[6]	transitions[0x0=>0x1]	60	1			T191	4		T35	3		T133	3
all_pins[6]	transitions[0x1=>0x0]	30097	1			T4	1		T17	213		T26	1
all_pins[7]	values[0x0]	624594	1			T1	1		T2	2		T3	9
all_pins[7]	values[0x1]	30115	1			T4	1		T17	213		T26	1
all_pins[7]	transitions[0x0=>0x1]	30094	1			T4	1		T17	213		T26	1
all_pins[7]	transitions[0x1=>0x0]	57	1			T191	1		T35	1		T133	1
all_pins[8]	values[0x0]	654631	1			T1	1		T2	2		T3	9
all_pins[8]	values[0x1]	78	1			T191	1		T35	1		T133	1
all_pins[8]	transitions[0x0=>0x1]	54	1			T191	1		T35	1		T133	1
all_pins[8]	transitions[0x1=>0x0]	461576	1			T4	1		T17	3560		T48	1
all_pins[9]	values[0x0]	193109	1			T1	1		T2	2		T3	9
all_pins[9]	values[0x1]	461600	1			T4	1		T17	3560		T48	1
all_pins[9]	transitions[0x0=>0x1]	461588	1			T4	1		T17	3560		T48	1
all_pins[9]	transitions[0x1=>0x0]	48	1			T191	1		T280	1		T252	1
all_pins[10]	values[0x0]	654649	1			T1	1		T2	2		T3	9
all_pins[10]	values[0x1]	60	1			T191	1		T280	2		T252	1
all_pins[10]	transitions[0x0=>0x1]	46	1			T191	1		T280	1		T252	1
all_pins[10]	transitions[0x1=>0x0]	648602	1			T3	7		T4	2		T5	2
all_pins[11]	values[0x0]	6093	1			T1	1		T2	2		T3	2
all_pins[11]	values[0x1]	648616	1			T3	7		T4	2		T5	2
all_pins[11]	transitions[0x0=>0x1]	648585	1			T3	7		T4	2		T5	2
all_pins[11]	transitions[0x1=>0x0]	95	1			T62	1		T63	1		T68	1
all_pins[12]	values[0x0]	654583	1			T1	1		T2	2		T3	9
all_pins[12]	values[0x1]	126	1			T70	1		T62	1		T63	1
all_pins[12]	transitions[0x0=>0x1]	105	1			T70	1		T62	1		T63	1
all_pins[12]	transitions[0x1=>0x0]	64	1			T23	1		T133	2		T280	3
all_pins[13]	values[0x0]	654624	1			T1	1		T2	2		T3	9
all_pins[13]	values[0x1]	85	1			T191	1		T23	1		T42	1
all_pins[13]	transitions[0x0=>0x1]	61	1			T191	1		T42	1		T133	2
all_pins[13]	transitions[0x1=>0x0]	66	1			T23	2		T42	1		T133	2
all_pins[14]	values[0x0]	654619	1			T1	1		T2	2		T3	9
all_pins[14]	values[0x1]	90	1			T23	3		T42	1		T133	2
all_pins[14]	transitions[0x0=>0x1]	59	1			T23	2		T133	1		T280	1
all_pins[14]	transitions[0x1=>0x0]	548595	1			T3	6		T4	1		T5	1