Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	321	1			T191	7		T23	4		T35	4
all_values[1]	321	1			T191	7		T23	4		T35	4
all_values[2]	321	1			T191	7		T23	4		T35	4
all_values[3]	321	1			T191	7		T23	4		T35	4
all_values[4]	321	1			T191	7		T23	4		T35	4
all_values[5]	321	1			T191	7		T23	4		T35	4
all_values[6]	321	1			T191	7		T23	4		T35	4
all_values[7]	321	1			T191	7		T23	4		T35	4
all_values[8]	321	1			T191	7		T23	4		T35	4
all_values[9]	321	1			T191	7		T23	4		T35	4
all_values[10]	321	1			T191	7		T23	4		T35	4
all_values[11]	321	1			T191	7		T23	4		T35	4
all_values[12]	321	1			T191	7		T23	4		T35	4
all_values[13]	321	1			T191	7		T23	4		T35	4
all_values[14]	321	1			T191	7		T23	4		T35	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2591

1

T191

61

T23

39

T35

33

auto[1]

2224

1

T191

44

T23

21

T35

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

875

1

T191

9

T23

15

T35

10

auto[1]

3940

1

T191

96

T23

45

T35

50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2847

1

T191

60

T23

37

T35

34

auto[1]

1968

1

T191

45

T23

23

T35

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	35	1			T23	1		T280	2		T281	1
all_values[0]	auto[0]	auto[0]	auto[1]	64	1			T191	1		T23	1		T35	2
all_values[0]	auto[0]	auto[1]	auto[0]	28	1			T133	1		T134	1		T135	3
all_values[0]	auto[0]	auto[1]	auto[1]	66	1			T191	2		T42	2		T133	2
all_values[0]	auto[1]	auto[0]	auto[1]	71	1			T191	2		T35	1		T42	1
all_values[0]	auto[1]	auto[1]	auto[1]	57	1			T191	2		T23	2		T35	1
all_values[1]	auto[0]	auto[0]	auto[0]	32	1			T23	1		T42	1		T133	2
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T191	2		T35	1		T133	6
all_values[1]	auto[0]	auto[1]	auto[0]	23	1			T191	1		T23	1		T42	3
all_values[1]	auto[0]	auto[1]	auto[1]	59	1			T191	1		T23	1		T133	3
all_values[1]	auto[1]	auto[0]	auto[1]	68	1			T191	1		T133	2		T280	2
all_values[1]	auto[1]	auto[1]	auto[1]	53	1			T191	2		T23	1		T35	3
all_values[2]	auto[0]	auto[0]	auto[0]	32	1			T23	3		T135	1		T279	1
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T191	2		T35	1		T42	1
all_values[2]	auto[0]	auto[1]	auto[0]	29	1			T23	1		T133	2		T280	1
all_values[2]	auto[0]	auto[1]	auto[1]	62	1			T191	1		T35	1		T42	1
all_values[2]	auto[1]	auto[0]	auto[1]	72	1			T191	4		T42	1		T133	4
all_values[2]	auto[1]	auto[1]	auto[1]	56	1			T35	2		T42	1		T133	1
all_values[3]	auto[0]	auto[0]	auto[0]	48	1			T191	2		T35	1		T280	6
all_values[3]	auto[0]	auto[0]	auto[1]	50	1			T191	1		T23	1		T35	1
all_values[3]	auto[0]	auto[1]	auto[0]	19	1			T280	1		T252	1		T281	2
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T191	2		T23	1		T42	2
all_values[3]	auto[1]	auto[0]	auto[1]	83	1			T191	2		T23	2		T42	1
all_values[3]	auto[1]	auto[1]	auto[1]	51	1			T35	2		T42	1		T133	2
all_values[4]	auto[0]	auto[0]	auto[0]	36	1			T23	1		T135	1		T282	1
all_values[4]	auto[0]	auto[0]	auto[1]	71	1			T191	1		T23	2		T35	1
all_values[4]	auto[0]	auto[1]	auto[0]	13	1			T191	1		T133	2		T283	2
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T191	2		T35	2		T42	1
all_values[4]	auto[1]	auto[0]	auto[1]	63	1			T191	1		T23	1		T35	1
all_values[4]	auto[1]	auto[1]	auto[1]	72	1			T191	2		T42	1		T133	5
all_values[5]	auto[0]	auto[0]	auto[0]	49	1			T23	1		T42	3		T280	4
all_values[5]	auto[0]	auto[0]	auto[1]	61	1			T191	3		T23	1		T133	3
all_values[5]	auto[0]	auto[1]	auto[0]	37	1			T35	1		T42	1		T280	3
all_values[5]	auto[0]	auto[1]	auto[1]	63	1			T191	1		T35	1		T133	4
all_values[5]	auto[1]	auto[0]	auto[1]	54	1			T191	1		T23	2		T35	2
all_values[5]	auto[1]	auto[1]	auto[1]	57	1			T191	2		T133	4		T252	4
all_values[6]	auto[0]	auto[0]	auto[0]	25	1			T23	1		T42	1		T252	2
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T191	2		T23	1		T133	3
all_values[6]	auto[0]	auto[1]	auto[0]	23	1			T280	1		T134	1		T135	2
all_values[6]	auto[0]	auto[1]	auto[1]	59	1			T191	1		T35	1		T42	1
all_values[6]	auto[1]	auto[0]	auto[1]	81	1			T191	2		T35	1		T133	5
all_values[6]	auto[1]	auto[1]	auto[1]	65	1			T191	2		T23	2		T35	2
all_values[7]	auto[0]	auto[0]	auto[0]	28	1			T191	1		T281	1		T279	1
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T191	2		T23	1		T35	2
all_values[7]	auto[0]	auto[1]	auto[0]	24	1			T133	2		T252	1		T279	3
all_values[7]	auto[0]	auto[1]	auto[1]	56	1			T191	1		T23	1		T133	4
all_values[7]	auto[1]	auto[0]	auto[1]	76	1			T191	2		T23	1		T35	2
all_values[7]	auto[1]	auto[1]	auto[1]	61	1			T191	1		T23	1		T133	1
all_values[8]	auto[0]	auto[0]	auto[0]	31	1			T23	1		T282	3		T284	1
all_values[8]	auto[0]	auto[0]	auto[1]	74	1			T191	4		T23	1		T35	1
all_values[8]	auto[0]	auto[1]	auto[0]	14	1			T23	1		T281	1		T282	1
all_values[8]	auto[0]	auto[1]	auto[1]	70	1			T191	1		T35	1		T133	1
all_values[8]	auto[1]	auto[0]	auto[1]	68	1			T191	1		T35	1		T42	2
all_values[8]	auto[1]	auto[1]	auto[1]	64	1			T191	1		T23	1		T35	1
all_values[9]	auto[0]	auto[0]	auto[0]	34	1			T191	1		T23	2		T35	1
all_values[9]	auto[0]	auto[0]	auto[1]	65	1			T191	3		T133	7		T280	2
all_values[9]	auto[0]	auto[1]	auto[0]	30	1			T35	3		T285	1		T286	2
all_values[9]	auto[0]	auto[1]	auto[1]	63	1			T191	2		T23	1		T42	1
all_values[9]	auto[1]	auto[0]	auto[1]	69	1			T23	1		T42	2		T133	4
all_values[9]	auto[1]	auto[1]	auto[1]	60	1			T191	1		T133	1		T280	2
all_values[10]	auto[0]	auto[0]	auto[0]	31	1			T23	1		T42	2		T133	2
all_values[10]	auto[0]	auto[0]	auto[1]	83	1			T191	2		T23	2		T35	1
all_values[10]	auto[0]	auto[1]	auto[0]	25	1			T191	1		T133	2		T252	1
all_values[10]	auto[0]	auto[1]	auto[1]	59	1			T191	2		T35	2		T133	1
all_values[10]	auto[1]	auto[0]	auto[1]	74	1			T191	1		T23	1		T35	1
all_values[10]	auto[1]	auto[1]	auto[1]	49	1			T191	1		T133	1		T280	2
all_values[11]	auto[0]	auto[0]	auto[0]	34	1			T280	1		T281	1		T282	1
all_values[11]	auto[0]	auto[0]	auto[1]	58	1			T191	2		T23	1		T35	2
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T35	1		T252	1		T281	1
all_values[11]	auto[0]	auto[1]	auto[1]	64	1			T191	3		T23	1		T133	5
all_values[11]	auto[1]	auto[0]	auto[1]	78	1			T23	1		T35	1		T42	2
all_values[11]	auto[1]	auto[1]	auto[1]	63	1			T191	2		T23	1		T133	5
all_values[12]	auto[0]	auto[0]	auto[0]	39	1			T282	1		T284	3		T287	1
all_values[12]	auto[0]	auto[0]	auto[1]	65	1			T191	1		T23	2		T35	1
all_values[12]	auto[0]	auto[1]	auto[0]	31	1			T280	1		T281	1		T279	1
all_values[12]	auto[0]	auto[1]	auto[1]	59	1			T35	1		T42	1		T133	4
all_values[12]	auto[1]	auto[0]	auto[1]	62	1			T191	3		T23	2		T35	1
all_values[12]	auto[1]	auto[1]	auto[1]	65	1			T191	3		T35	1		T42	1
all_values[13]	auto[0]	auto[0]	auto[0]	37	1			T191	2		T133	6		T283	1
all_values[13]	auto[0]	auto[0]	auto[1]	58	1			T191	2		T23	1		T35	1
all_values[13]	auto[0]	auto[1]	auto[0]	19	1			T35	1		T133	2		T252	1
all_values[13]	auto[0]	auto[1]	auto[1]	65	1			T23	2		T133	1		T280	1
all_values[13]	auto[1]	auto[0]	auto[1]	65	1			T191	2		T23	1		T35	2
all_values[13]	auto[1]	auto[1]	auto[1]	77	1			T191	1		T133	2		T280	4
all_values[14]	auto[0]	auto[0]	auto[0]	26	1			T35	2		T134	1		T135	3
all_values[14]	auto[0]	auto[0]	auto[1]	65	1			T191	2		T35	1		T42	1
all_values[14]	auto[0]	auto[1]	auto[0]	19	1			T133	1		T280	1		T281	2
all_values[14]	auto[0]	auto[1]	auto[1]	77	1			T191	2		T23	1		T42	1
all_values[14]	auto[1]	auto[0]	auto[1]	76	1			T191	3		T23	1		T35	1
all_values[14]	auto[1]	auto[1]	auto[1]	58	1			T23	2		T42	1		T133	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal