Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	693575	1			T1	1		T2	2		T3	3
all_values[1]	693575	1			T1	1		T2	2		T3	3
all_values[2]	693575	1			T1	1		T2	2		T3	3
all_values[3]	693575	1			T1	1		T2	2		T3	3
all_values[4]	693575	1			T1	1		T2	2		T3	3
all_values[5]	693575	1			T1	1		T2	2		T3	3
all_values[6]	693575	1			T1	1		T2	2		T3	3
all_values[7]	693575	1			T1	1		T2	2		T3	3
all_values[8]	693575	1			T1	1		T2	2		T3	3
all_values[9]	693575	1			T1	1		T2	2		T3	3
all_values[10]	693575	1			T1	1		T2	2		T3	3
all_values[11]	693575	1			T1	1		T2	2		T3	3
all_values[12]	693575	1			T1	1		T2	2		T3	3
all_values[13]	693575	1			T1	1		T2	2		T3	3
all_values[14]	693575	1			T1	1		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8576696

1

T1

15

T2

30

T3

40

auto[1]

1826929

1

T3

5

T5

6

T7

192

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10093518

1

T1

15

T2

30

T3

45

auto[1]

310107

1

T35

36239

T183

13907

T184

30817

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	109025	1			T1	1		T2	2		T3	1
all_values[0]	auto[0]	auto[1]	3542	1			T35	13		T183	760		T184	115
all_values[0]	auto[1]	auto[0]	562219	1			T3	2		T5	2		T7	96
all_values[0]	auto[1]	auto[1]	18789	1			T35	1483		T183	234		T184	2256
all_values[1]	auto[0]	auto[0]	669743	1			T1	1		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	23323	1			T35	2642		T183	991		T184	2370
all_values[1]	auto[1]	auto[0]	337	1			T125	33		T147	8		T269	5
all_values[1]	auto[1]	auto[1]	172	1			T35	3		T183	3		T184	1
all_values[2]	auto[0]	auto[0]	669917	1			T1	1		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	23337	1			T35	2642		T183	992		T184	2369
all_values[2]	auto[1]	auto[0]	190	1			T43	2		T69	1		T162	1
all_values[2]	auto[1]	auto[1]	131	1			T35	4		T183	1		T184	2
all_values[3]	auto[0]	auto[0]	686542	1			T1	1		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	6886	1			T35	2639		T183	990		T184	2370
all_values[3]	auto[1]	auto[1]	147	1			T35	7		T183	3		T233	6
all_values[4]	auto[0]	auto[0]	670073	1			T1	1		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	23338	1			T35	2641		T183	993		T184	2369
all_values[4]	auto[1]	auto[0]	19	1			T11	1		T12	3		T13	1
all_values[4]	auto[1]	auto[1]	145	1			T35	5		T183	1		T184	1
all_values[5]	auto[0]	auto[0]	687697	1			T1	1		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	5708	1			T35	1490		T183	992		T184	2371
all_values[5]	auto[1]	auto[1]	170	1			T35	6		T183	1		T233	4
all_values[6]	auto[0]	auto[0]	670076	1			T1	1		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	23313	1			T35	2641		T183	990		T184	2370
all_values[6]	auto[1]	auto[1]	186	1			T35	6		T183	3		T184	1
all_values[7]	auto[0]	auto[0]	643474	1			T1	1		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	19904	1			T35	2393		T183	810		T233	3
all_values[7]	auto[1]	auto[0]	29005	1			T5	1		T8	153		T9	93
all_values[7]	auto[1]	auto[1]	1192	1			T35	252		T183	183		T233	8
all_values[8]	auto[0]	auto[0]	670102	1			T1	1		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	23306	1			T35	2643		T183	990		T184	2367
all_values[8]	auto[1]	auto[1]	167	1			T35	3		T183	2		T184	2
all_values[9]	auto[0]	auto[0]	164312	1			T1	1		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	6783	1			T35	2594		T183	976		T233	2
all_values[9]	auto[1]	auto[0]	508153	1			T3	1		T5	1		T8	9345
all_values[9]	auto[1]	auto[1]	14327	1			T35	53		T183	17		T233	3
all_values[10]	auto[0]	auto[0]	671100	1			T1	1		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	22330	1			T35	2640		T184	2368		T233	6
all_values[10]	auto[1]	auto[1]	145	1			T35	7		T184	3		T233	4
all_values[11]	auto[0]	auto[0]	2360	1			T1	1		T2	2		T3	1
all_values[11]	auto[0]	auto[1]	275	1			T35	24		T183	1		T184	16
all_values[11]	auto[1]	auto[0]	667733	1			T3	2		T5	2		T7	96
all_values[11]	auto[1]	auto[1]	23207	1			T35	2622		T183	993		T184	2355
all_values[12]	auto[0]	auto[0]	670024	1			T1	1		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	23359	1			T35	2642		T183	992		T184	2369
all_values[12]	auto[1]	auto[0]	64	1			T69	1		T64	1		T65	1
all_values[12]	auto[1]	auto[1]	128	1			T35	3		T183	2		T184	1
all_values[13]	auto[0]	auto[0]	671269	1			T1	1		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	22163	1			T35	1492		T183	992		T184	2368
all_values[13]	auto[1]	auto[1]	143	1			T35	4		T183	1		T184	3
all_values[14]	auto[0]	auto[0]	670084	1			T1	1		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	23331	1			T35	2641		T183	990		T184	2368
all_values[14]	auto[1]	auto[1]	160	1			T35	4		T183	4		T184	2