Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	693575	1			T1	1		T2	2		T3	3
all_pins[1]	693575	1			T1	1		T2	2		T3	3
all_pins[2]	693575	1			T1	1		T2	2		T3	3
all_pins[3]	693575	1			T1	1		T2	2		T3	3
all_pins[4]	693575	1			T1	1		T2	2		T3	3
all_pins[5]	693575	1			T1	1		T2	2		T3	3
all_pins[6]	693575	1			T1	1		T2	2		T3	3
all_pins[7]	693575	1			T1	1		T2	2		T3	3
all_pins[8]	693575	1			T1	1		T2	2		T3	3
all_pins[9]	693575	1			T1	1		T2	2		T3	3
all_pins[10]	693575	1			T1	1		T2	2		T3	3
all_pins[11]	693575	1			T1	1		T2	2		T3	3
all_pins[12]	693575	1			T1	1		T2	2		T3	3
all_pins[13]	693575	1			T1	1		T2	2		T3	3
all_pins[14]	693575	1			T1	1		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8583196	1			T1	15		T2	30		T3	40
values[0x1]	1820429	1			T3	5		T5	6		T7	192
transitions[0x0=>0x1]	1819695	1			T3	5		T5	6		T7	192
transitions[0x1=>0x0]	1818388	1			T3	4		T5	5		T7	191

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	116208	1			T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	577367	1			T3	2		T5	2		T7	96
all_pins[0]	transitions[0x0=>0x1]	576919	1			T3	2		T5	2		T7	96
all_pins[0]	transitions[0x1=>0x0]	55	1			T275	2		T35	2		T183	1
all_pins[1]	values[0x0]	693072	1			T1	1		T2	2		T3	3
all_pins[1]	values[0x1]	503	1			T125	37		T147	8		T269	5
all_pins[1]	transitions[0x0=>0x1]	482	1			T125	37		T147	8		T269	5
all_pins[1]	transitions[0x1=>0x0]	96	1			T69	1		T215	1		T276	1
all_pins[2]	values[0x0]	693458	1			T1	1		T2	2		T3	3
all_pins[2]	values[0x1]	117	1			T69	1		T215	1		T276	1
all_pins[2]	transitions[0x0=>0x1]	104	1			T69	1		T215	1		T276	1
all_pins[2]	transitions[0x1=>0x0]	58	1			T35	1		T233	2		T120	3
all_pins[3]	values[0x0]	693504	1			T1	1		T2	2		T3	3
all_pins[3]	values[0x1]	71	1			T35	1		T233	2		T120	4
all_pins[3]	transitions[0x0=>0x1]	61	1			T35	1		T233	1		T120	4
all_pins[3]	transitions[0x1=>0x0]	71	1			T11	1		T12	3		T13	1
all_pins[4]	values[0x0]	693494	1			T1	1		T2	2		T3	3
all_pins[4]	values[0x1]	81	1			T11	1		T12	3		T13	1
all_pins[4]	transitions[0x0=>0x1]	68	1			T11	1		T12	3		T13	1
all_pins[4]	transitions[0x1=>0x0]	63	1			T35	3		T183	1		T233	2
all_pins[5]	values[0x0]	693499	1			T1	1		T2	2		T3	3
all_pins[5]	values[0x1]	76	1			T35	3		T183	1		T233	2
all_pins[5]	transitions[0x0=>0x1]	50	1			T35	3		T183	1		T233	2
all_pins[5]	transitions[0x1=>0x0]	57	1			T183	2		T233	2		T245	3
all_pins[6]	values[0x0]	693492	1			T1	1		T2	2		T3	3
all_pins[6]	values[0x1]	83	1			T183	2		T233	2		T120	2
all_pins[6]	transitions[0x0=>0x1]	66	1			T183	2		T233	1		T120	2
all_pins[6]	transitions[0x1=>0x0]	32563	1			T5	1		T8	180		T9	105
all_pins[7]	values[0x0]	660995	1			T1	1		T2	2		T3	3
all_pins[7]	values[0x1]	32580	1			T5	1		T8	180		T9	105
all_pins[7]	transitions[0x0=>0x1]	32556	1			T5	1		T8	180		T9	105
all_pins[7]	transitions[0x1=>0x0]	59	1			T35	1		T183	2		T184	2
all_pins[8]	values[0x0]	693492	1			T1	1		T2	2		T3	3
all_pins[8]	values[0x1]	83	1			T35	1		T183	2		T184	2
all_pins[8]	transitions[0x0=>0x1]	66	1			T35	1		T183	2		T184	2
all_pins[8]	transitions[0x1=>0x0]	522420	1			T3	1		T5	1		T8	9345
all_pins[9]	values[0x0]	171138	1			T1	1		T2	2		T3	2
all_pins[9]	values[0x1]	522437	1			T3	1		T5	1		T8	9345
all_pins[9]	transitions[0x0=>0x1]	522414	1			T3	1		T5	1		T8	9345
all_pins[9]	transitions[0x1=>0x0]	47	1			T35	2		T184	1		T233	2
all_pins[10]	values[0x0]	693505	1			T1	1		T2	2		T3	3
all_pins[10]	values[0x1]	70	1			T35	4		T184	1		T233	2
all_pins[10]	transitions[0x0=>0x1]	53	1			T35	4		T184	1		T233	2
all_pins[10]	transitions[0x1=>0x0]	686668	1			T3	2		T5	2		T7	96
all_pins[11]	values[0x0]	6890	1			T1	1		T2	2		T3	1
all_pins[11]	values[0x1]	686685	1			T3	2		T5	2		T7	96
all_pins[11]	transitions[0x0=>0x1]	686648	1			T3	2		T5	2		T7	96
all_pins[11]	transitions[0x1=>0x0]	96	1			T64	1		T65	1		T68	1
all_pins[12]	values[0x0]	693442	1			T1	1		T2	2		T3	3
all_pins[12]	values[0x1]	133	1			T69	1		T64	1		T65	1
all_pins[12]	transitions[0x0=>0x1]	121	1			T69	1		T64	1		T65	1
all_pins[12]	transitions[0x1=>0x0]	46	1			T35	2		T183	1		T184	2
all_pins[13]	values[0x0]	693517	1			T1	1		T2	2		T3	3
all_pins[13]	values[0x1]	58	1			T35	2		T183	1		T184	2
all_pins[13]	transitions[0x0=>0x1]	41	1			T35	1		T183	1		T122	5
all_pins[13]	transitions[0x1=>0x0]	68	1			T183	1		T120	1		T128	1
all_pins[14]	values[0x0]	693490	1			T1	1		T2	2		T3	3
all_pins[14]	values[0x1]	85	1			T35	1		T183	1		T184	2
all_pins[14]	transitions[0x0=>0x1]	46	1			T35	1		T184	1		T122	1
all_pins[14]	transitions[0x1=>0x0]	576021	1			T3	1		T5	1		T7	95