Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	352	1			T35	12		T183	4		T184	4
all_values[1]	352	1			T35	12		T183	4		T184	4
all_values[2]	352	1			T35	12		T183	4		T184	4
all_values[3]	352	1			T35	12		T183	4		T184	4
all_values[4]	352	1			T35	12		T183	4		T184	4
all_values[5]	352	1			T35	12		T183	4		T184	4
all_values[6]	352	1			T35	12		T183	4		T184	4
all_values[7]	352	1			T35	12		T183	4		T184	4
all_values[8]	352	1			T35	12		T183	4		T184	4
all_values[9]	352	1			T35	12		T183	4		T184	4
all_values[10]	352	1			T35	12		T183	4		T184	4
all_values[11]	352	1			T35	12		T183	4		T184	4
all_values[12]	352	1			T35	12		T183	4		T184	4
all_values[13]	352	1			T35	12		T183	4		T184	4
all_values[14]	352	1			T35	12		T183	4		T184	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2881

1

T35

107

T183

30

T184

20

auto[1]

2399

1

T35

73

T183

30

T184

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T35

28

T183

13

T184

14

auto[1]

4289

1

T35

152

T183

47

T184

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3174

1

T35

109

T183

38

T184

39

auto[1]

2106

1

T35

71

T183

22

T184

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	47	1			T35	3		T233	1		T277	1
all_values[0]	auto[0]	auto[0]	auto[1]	58	1			T183	2		T233	1		T120	1
all_values[0]	auto[0]	auto[1]	auto[0]	20	1			T35	2		T233	1		T245	3
all_values[0]	auto[0]	auto[1]	auto[1]	83	1			T35	3		T183	1		T184	2
all_values[0]	auto[1]	auto[0]	auto[1]	68	1			T35	3		T233	2		T120	1
all_values[0]	auto[1]	auto[1]	auto[1]	76	1			T35	1		T183	1		T184	2
all_values[1]	auto[0]	auto[0]	auto[0]	33	1			T35	2		T120	2		T122	1
all_values[1]	auto[0]	auto[0]	auto[1]	76	1			T35	5		T184	3		T233	1
all_values[1]	auto[0]	auto[1]	auto[0]	18	1			T120	2		T122	1		T246	1
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T35	2		T183	1		T233	4
all_values[1]	auto[1]	auto[0]	auto[1]	69	1			T233	1		T120	1		T122	2
all_values[1]	auto[1]	auto[1]	auto[1]	79	1			T35	3		T183	3		T184	1
all_values[2]	auto[0]	auto[0]	auto[0]	42	1			T35	1		T246	1		T278	1
all_values[2]	auto[0]	auto[0]	auto[1]	65	1			T35	3		T184	1		T233	3
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T183	1		T122	1		T279	1
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T35	4		T183	2		T184	1
all_values[2]	auto[1]	auto[0]	auto[1]	66	1			T35	3		T233	2		T122	1
all_values[2]	auto[1]	auto[1]	auto[1]	65	1			T35	1		T183	1		T184	2
all_values[3]	auto[0]	auto[0]	auto[0]	48	1			T35	1		T277	4		T280	3
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T35	3		T183	1		T184	1
all_values[3]	auto[0]	auto[1]	auto[0]	23	1			T183	1		T184	1		T120	1
all_values[3]	auto[0]	auto[1]	auto[1]	60	1			T35	3		T184	1		T233	1
all_values[3]	auto[1]	auto[0]	auto[1]	81	1			T35	4		T183	1		T184	1
all_values[3]	auto[1]	auto[1]	auto[1]	55	1			T35	1		T183	1		T233	2
all_values[4]	auto[0]	auto[0]	auto[0]	41	1			T35	1		T233	1		T120	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T35	4		T183	3		T184	1
all_values[4]	auto[0]	auto[1]	auto[0]	21	1			T184	1		T120	1		T122	1
all_values[4]	auto[0]	auto[1]	auto[1]	58	1			T35	2		T184	1		T120	3
all_values[4]	auto[1]	auto[0]	auto[1]	91	1			T35	4		T183	1		T122	1
all_values[4]	auto[1]	auto[1]	auto[1]	54	1			T35	1		T184	1		T233	4
all_values[5]	auto[0]	auto[0]	auto[0]	40	1			T35	1		T183	1		T233	2
all_values[5]	auto[0]	auto[0]	auto[1]	73	1			T35	2		T233	1		T120	4
all_values[5]	auto[0]	auto[1]	auto[0]	38	1			T35	4		T122	1		T277	1
all_values[5]	auto[0]	auto[1]	auto[1]	68	1			T35	1		T183	2		T184	2
all_values[5]	auto[1]	auto[0]	auto[1]	73	1			T35	1		T183	1		T184	1
all_values[5]	auto[1]	auto[1]	auto[1]	60	1			T35	3		T184	1		T233	2
all_values[6]	auto[0]	auto[0]	auto[0]	28	1			T183	1		T279	1		T281	2
all_values[6]	auto[0]	auto[0]	auto[1]	77	1			T35	2		T184	1		T233	3
all_values[6]	auto[0]	auto[1]	auto[0]	18	1			T128	1		T246	1		T282	2
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T35	3		T183	1		T184	2
all_values[6]	auto[1]	auto[0]	auto[1]	90	1			T35	6		T183	1		T233	1
all_values[6]	auto[1]	auto[1]	auto[1]	54	1			T35	1		T183	1		T184	1
all_values[7]	auto[0]	auto[0]	auto[0]	50	1			T35	2		T184	3		T277	1
all_values[7]	auto[0]	auto[0]	auto[1]	61	1			T35	1		T183	1		T233	2
all_values[7]	auto[0]	auto[1]	auto[0]	29	1			T183	1		T184	1		T120	1
all_values[7]	auto[0]	auto[1]	auto[1]	64	1			T35	3		T233	1		T120	3
all_values[7]	auto[1]	auto[0]	auto[1]	92	1			T35	2		T183	1		T233	4
all_values[7]	auto[1]	auto[1]	auto[1]	56	1			T35	4		T183	1		T233	1
all_values[8]	auto[0]	auto[0]	auto[0]	39	1			T183	2		T233	1		T277	1
all_values[8]	auto[0]	auto[0]	auto[1]	70	1			T35	5		T233	3		T120	2
all_values[8]	auto[0]	auto[1]	auto[0]	32	1			T35	1		T184	2		T120	1
all_values[8]	auto[0]	auto[1]	auto[1]	74	1			T35	1		T183	1		T184	1
all_values[8]	auto[1]	auto[0]	auto[1]	78	1			T35	4		T184	1		T233	2
all_values[8]	auto[1]	auto[1]	auto[1]	59	1			T35	1		T183	1		T120	1
all_values[9]	auto[0]	auto[0]	auto[0]	43	1			T184	2		T233	2		T277	7
all_values[9]	auto[0]	auto[0]	auto[1]	61	1			T35	3		T233	1		T120	1
all_values[9]	auto[0]	auto[1]	auto[0]	20	1			T183	1		T184	2		T233	3
all_values[9]	auto[0]	auto[1]	auto[1]	83	1			T35	3		T183	2		T233	1
all_values[9]	auto[1]	auto[0]	auto[1]	74	1			T35	4		T233	1		T120	1
all_values[9]	auto[1]	auto[1]	auto[1]	71	1			T35	2		T183	1		T120	1
all_values[10]	auto[0]	auto[0]	auto[0]	48	1			T183	2		T233	1		T277	4
all_values[10]	auto[0]	auto[0]	auto[1]	68	1			T35	3		T184	1		T233	1
all_values[10]	auto[0]	auto[1]	auto[0]	28	1			T183	2		T120	1		T277	3
all_values[10]	auto[0]	auto[1]	auto[1]	63	1			T35	2		T233	2		T120	2
all_values[10]	auto[1]	auto[0]	auto[1]	80	1			T35	3		T184	1		T233	3
all_values[10]	auto[1]	auto[1]	auto[1]	65	1			T35	4		T184	2		T233	1
all_values[11]	auto[0]	auto[0]	auto[0]	44	1			T35	1		T277	1		T245	1
all_values[11]	auto[0]	auto[0]	auto[1]	69	1			T35	4		T183	3		T184	2
all_values[11]	auto[0]	auto[1]	auto[0]	18	1			T120	1		T246	1		T279	3
all_values[11]	auto[0]	auto[1]	auto[1]	81	1			T35	3		T184	1		T233	4
all_values[11]	auto[1]	auto[0]	auto[1]	80	1			T35	4		T183	1		T233	1
all_values[11]	auto[1]	auto[1]	auto[1]	60	1			T184	1		T233	1		T122	3
all_values[12]	auto[0]	auto[0]	auto[0]	32	1			T35	2		T277	2		T245	2
all_values[12]	auto[0]	auto[0]	auto[1]	90	1			T35	4		T183	2		T233	3
all_values[12]	auto[0]	auto[1]	auto[0]	26	1			T184	1		T120	2		T122	1
all_values[12]	auto[0]	auto[1]	auto[1]	76	1			T35	3		T184	2		T233	2
all_values[12]	auto[1]	auto[0]	auto[1]	67	1			T35	1		T183	2		T233	2
all_values[12]	auto[1]	auto[1]	auto[1]	61	1			T35	2		T184	1		T233	1
all_values[13]	auto[0]	auto[0]	auto[0]	47	1			T35	1		T233	2		T120	2
all_values[13]	auto[0]	auto[0]	auto[1]	84	1			T35	2		T183	2		T233	2
all_values[13]	auto[0]	auto[1]	auto[0]	31	1			T35	4		T183	1		T233	2
all_values[13]	auto[0]	auto[1]	auto[1]	52	1			T184	1		T122	2		T245	1
all_values[13]	auto[1]	auto[0]	auto[1]	80	1			T35	2		T184	1		T233	1
all_values[13]	auto[1]	auto[1]	auto[1]	58	1			T35	3		T183	1		T184	2
all_values[14]	auto[0]	auto[0]	auto[0]	32	1			T35	2		T245	1		T283	2
all_values[14]	auto[0]	auto[0]	auto[1]	75	1			T35	7		T183	1		T233	4
all_values[14]	auto[0]	auto[1]	auto[0]	24	1			T184	1		T122	1		T278	1
all_values[14]	auto[0]	auto[1]	auto[1]	77	1			T184	1		T233	1		T128	2
all_values[14]	auto[1]	auto[0]	auto[1]	79	1			T35	1		T183	1		T233	3
all_values[14]	auto[1]	auto[1]	auto[1]	65	1			T35	2		T183	2		T184	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal