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 LINE       3661
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T75,T44
1	1	0	Covered	T198,T206,T207
1	1	1	Covered	T105,T208,T187

 LINE       3662
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T75,T44
1	1	0	Covered	T188,T193,T114
1	1	1	Covered	T44,T45,T46

 LINE       3667
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T73,T11
1	1	0	Covered	T194,T203,T204
1	1	1	Not Covered

 LINE       3668
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T43,T47,T73
1	1	0	Covered	T188,T193,T114
1	1	1	Covered	T11,T12,T13

 LINE       3673
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T188,T193,T114
1	1	1	Covered	T1,T3,T4

 LINE       3682
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T47,T75,T73
1	1	0	Covered	T188,T193,T197
1	1	1	Covered	T70,T60,T71